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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [mpy_macs.s43] - Blame information for rev 67

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                          HARDWARE MULTIPLIER                              */
/*---------------------------------------------------------------------------*/
/* Test the hardware multiplier:                                             */
/*                                - MACS  mode.                              */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 18 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
.global main
 
.set   WDTCTL, 0x0120
 
.set   MPY,    0x0130
.set   MPYS,   0x0132
.set   MAC,    0x0134
.set   MACS,   0x0136
.set   OP2,    0x0138
.set   RESLO,  0x013A
.set   RESHI,  0x013C
.set   SUMEXT, 0x013E
 
 
main:
 
        /* --------------   SIGNED MULTIPLY ACCUMULATE   --------------- */
 
        ;; Disable watchdog
        mov #0x5A80, &WDTCTL
 
        ;; Initialize variables
        mov #0x0000, R15
        mov #0x0000, R8
        mov #0x0000, R9
 
mpy_loop:
 
        ;; Initialize RESLO and RESHI to make sure it is added
        mov #0x0000, &RESLO
        mov #0xC000, &RESHI
 
        ;; Perform unsigned R8*R9
        mov R8, &MACS
        mov R9, &OP2
 
        ;; Read result
        mov &RESLO,  R10
        mov &RESHI,  R11
        mov &SUMEXT, R12
 
        ;; Notify verilog checker
        add #1, R15
 
        ;; Update next OP1 (R8)
        cmp #0xF0F0, R8
        jeq op2_update
 
        mov #0x00FF, R7
        and R8, R7
        cmp #0x00F0, R7
        jeq op1_hi_update
 
        add #0x0010, R8
        jmp mpy_loop
  op1_hi_update:
        and #0xff00, R8
        add #0x1000, R8
        jmp mpy_loop
 
 
        ;; Update next OP2 (R9)
  op2_update:
        cmp #0xF0F0, R9
        jeq end_of_test
 
        mov #0x0000, R8
 
        mov #0x00FF, R7
        and R9, R7
        cmp #0x00F0, R7
        jeq op2_hi_update
 
        add #0x0010, R9
        jmp mpy_loop
  op2_hi_update:
        and #0xff00, R9
        add #0x1000, R9
        jmp mpy_loop
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	67	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* HARDWARE MULTIPLIER */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the hardware multiplier: */`
27			`/* - MACS mode. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 18 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */`
36			`/===========================================================================/`
37
38			`.global main`
39
40			`.set WDTCTL, 0x0120`
41
42			`.set MPY, 0x0130`
43			`.set MPYS, 0x0132`
44			`.set MAC, 0x0134`
45			`.set MACS, 0x0136`
46			`.set OP2, 0x0138`
47			`.set RESLO, 0x013A`
48			`.set RESHI, 0x013C`
49			`.set SUMEXT, 0x013E`
50
51
52			`main:`
53
54			`/* -------------- SIGNED MULTIPLY ACCUMULATE --------------- */`
55
56			`;; Disable watchdog`
57			`mov #0x5A80, &WDTCTL`
58
59			`;; Initialize variables`
60			`mov #0x0000, R15`
61			`mov #0x0000, R8`
62			`mov #0x0000, R9`
63
64			`mpy_loop:`
65
66			`;; Initialize RESLO and RESHI to make sure it is added`
67			`mov #0x0000, &RESLO`
68			`mov #0xC000, &RESHI`
69
70			`;; Perform unsigned R8*R9`
71			`mov R8, &MACS`
72			`mov R9, &OP2`
73
74			`;; Read result`
75			`mov &RESLO, R10`
76			`mov &RESHI, R11`
77			`mov &SUMEXT, R12`
78
79			`;; Notify verilog checker`
80			`add #1, R15`
81
82			`;; Update next OP1 (R8)`
83			`cmp #0xF0F0, R8`
84			`jeq op2_update`
85
86			`mov #0x00FF, R7`
87			`and R8, R7`
88			`cmp #0x00F0, R7`
89			`jeq op1_hi_update`
90
91			`add #0x0010, R8`
92			`jmp mpy_loop`
93			`op1_hi_update:`
94			`and #0xff00, R8`
95			`add #0x1000, R8`
96			`jmp mpy_loop`
97
98
99			`;; Update next OP2 (R9)`
100			`op2_update:`
101			`cmp #0xF0F0, R9`
102			`jeq end_of_test`
103
104			`mov #0x0000, R8`
105
106			`mov #0x00FF, R7`
107			`and R9, R7`
108			`cmp #0x00F0, R7`
109			`jeq op2_hi_update`
110
111			`add #0x0010, R9`
112			`jmp mpy_loop`
113			`op2_hi_update:`
114			`and #0xff00, R9`
115			`add #0x1000, R9`
116			`jmp mpy_loop`
117
118
119
120			`/* ---------------------- END OF TEST --------------- */`
121			`end_of_test:`
122			`nop`
123			`br #0xffff`
124
125
126
127
128			`/* ---------------------- INTERRUPT VECTORS --------------- */`
129
130			`.section .vectors, "a"`
131			`.word end_of_test ; Interrupt 0 (lowest priority)`
132			`.word end_of_test ; Interrupt 1`
133			`.word end_of_test ; Interrupt 2`
134			`.word end_of_test ; Interrupt 3`
135			`.word end_of_test ; Interrupt 4`
136			`.word end_of_test ; Interrupt 5`
137			`.word end_of_test ; Interrupt 6`
138			`.word end_of_test ; Interrupt 7`
139			`.word end_of_test ; Interrupt 8`
140			`.word end_of_test ; Interrupt 9`
141			`.word end_of_test ; Interrupt 10 Watchdog timer`
142			`.word end_of_test ; Interrupt 11`
143			`.word end_of_test ; Interrupt 12`
144			`.word end_of_test ; Interrupt 13`
145			`.word end_of_test ; Interrupt 14 NMI`
146			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [mpy_macs.s43] - Blame information for rev 67