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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [mpy_mpys.s43] - Blame information for rev 141

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                          HARDWARE MULTIPLIER                              */
/*---------------------------------------------------------------------------*/
/* Test the hardware multiplier:                                             */
/*                                - MPYS  mode.                              */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 18 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
.include "pmem_defs.asm"
 
.global main
 
main:
 
        /* --------------   SIGNED MULTIPLICATION   --------------- */
 
        ;; Disable watchdog
        mov #0x5A80, &WDTCTL
 
        ;; Initialize variables
        mov #0x0000, R15
        mov #0x0000, R8
        mov #0x0000, R9
 
mpy_loop:
 
        ;; Initialize RESLO and RESHI to make sure it is overwritten
        mov #0x0000, &RESLO
        mov #0xC000, &RESHI
 
        ;; Perform unsigned R8*R9
        mov R8, &MPYS
        mov R9, &OP2
 
        ;; Read result
        mov &RESLO,  R10
        mov &RESHI,  R11
        mov &SUMEXT, R12
 
        ;; Notify verilog checker
        add #1, R15
 
        ;; Update next OP1 (R8)
        cmp #0xF0F0, R8
        jeq op2_update
 
        mov #0x00FF, R7
        and R8, R7
        cmp #0x00F0, R7
        jeq op1_hi_update
 
        add #0x0010, R8
        jmp mpy_loop
  op1_hi_update:
        and #0xff00, R8
        add #0x1000, R8
        jmp mpy_loop
 
 
        ;; Update next OP2 (R9)
  op2_update:
        cmp #0xF0F0, R9
        jeq end_of_test
 
        mov #0x0000, R8
 
        mov #0x00FF, R7
        and R9, R7
        cmp #0x00F0, R7
        jeq op2_hi_update
 
        add #0x0010, R9
        jmp mpy_loop
  op2_hi_update:
        and #0xff00, R9
        add #0x1000, R9
        jmp mpy_loop
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	67	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* HARDWARE MULTIPLIER */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the hardware multiplier: */`
27			`/* - MPYS mode. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 18 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */`
36			`/===========================================================================/`
37
38	141	olivier.gi	`.include "pmem_defs.asm"`
39
40	67	olivier.gi	`.global main`
41
42			`main:`
43
44			`/* -------------- SIGNED MULTIPLICATION --------------- */`
45
46			`;; Disable watchdog`
47			`mov #0x5A80, &WDTCTL`
48
49			`;; Initialize variables`
50			`mov #0x0000, R15`
51			`mov #0x0000, R8`
52			`mov #0x0000, R9`
53
54			`mpy_loop:`
55
56			`;; Initialize RESLO and RESHI to make sure it is overwritten`
57			`mov #0x0000, &RESLO`
58			`mov #0xC000, &RESHI`
59
60			`;; Perform unsigned R8*R9`
61			`mov R8, &MPYS`
62			`mov R9, &OP2`
63
64			`;; Read result`
65			`mov &RESLO, R10`
66			`mov &RESHI, R11`
67			`mov &SUMEXT, R12`
68
69			`;; Notify verilog checker`
70			`add #1, R15`
71
72			`;; Update next OP1 (R8)`
73			`cmp #0xF0F0, R8`
74			`jeq op2_update`
75
76			`mov #0x00FF, R7`
77			`and R8, R7`
78			`cmp #0x00F0, R7`
79			`jeq op1_hi_update`
80
81			`add #0x0010, R8`
82			`jmp mpy_loop`
83			`op1_hi_update:`
84			`and #0xff00, R8`
85			`add #0x1000, R8`
86			`jmp mpy_loop`
87
88
89			`;; Update next OP2 (R9)`
90			`op2_update:`
91			`cmp #0xF0F0, R9`
92			`jeq end_of_test`
93
94			`mov #0x0000, R8`
95
96			`mov #0x00FF, R7`
97			`and R9, R7`
98			`cmp #0x00F0, R7`
99			`jeq op2_hi_update`
100
101			`add #0x0010, R9`
102			`jmp mpy_loop`
103			`op2_hi_update:`
104			`and #0xff00, R9`
105			`add #0x1000, R9`
106			`jmp mpy_loop`
107
108
109
110			`/* ---------------------- END OF TEST --------------- */`
111			`end_of_test:`
112			`nop`
113			`br #0xffff`
114
115
116
117
118			`/* ---------------------- INTERRUPT VECTORS --------------- */`
119
120			`.section .vectors, "a"`
121			`.word end_of_test ; Interrupt 0 (lowest priority)`
122			`.word end_of_test ; Interrupt 1`
123			`.word end_of_test ; Interrupt 2`
124			`.word end_of_test ; Interrupt 3`
125			`.word end_of_test ; Interrupt 4`
126			`.word end_of_test ; Interrupt 5`
127			`.word end_of_test ; Interrupt 6`
128			`.word end_of_test ; Interrupt 7`
129			`.word end_of_test ; Interrupt 8`
130			`.word end_of_test ; Interrupt 9`
131			`.word end_of_test ; Interrupt 10 Watchdog timer`
132			`.word end_of_test ; Interrupt 11`
133			`.word end_of_test ; Interrupt 12`
134			`.word end_of_test ; Interrupt 13`
135			`.word end_of_test ; Interrupt 14 NMI`
136			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [mpy_mpys.s43] - Blame information for rev 141