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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [op_modes.s43] - Blame information for rev 2

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            CPU OPERATING MODES                            */
/*---------------------------------------------------------------------------*/
/* Test the CPU Operating modes:                                             */
/*                                 - CPUOFF (<=> R2[4]): turn off CPU.       */
/*                                 - OSCOFF (<=> R2[5]): turn off LFXT_CLK.  */
/*                                 - SCG1   (<=> R2[7]): turn off SMCLK.     */
/*===========================================================================*/
 
.global main
 
.set   P1IN,  0x0020
.set   P1OUT, 0x0021
.set   P1DIR, 0x0022
.set   P1IFG, 0x0023
.set   P1IES, 0x0024
.set   P1IE,  0x0025
.set   P1SEL, 0x0026
.set   P2IN,  0x0028
.set   P2OUT, 0x0029
.set   P2DIR, 0x002A
.set   P2IFG, 0x002B
.set   P2IES, 0x002C
.set   P2IE,  0x002D
.set   P2SEL, 0x002E
 
.set   BCSCTL1, 0x0057
.set   BCSCTL2, 0x0058
 
 
WAIT_FUNC:
        dec r14
        jnz WAIT_FUNC
        ret
 
main:
        ; Enable GPIO interrupts on P1[0]
        mov.b #0x00, &P1DIR
        mov.b #0x00, &P1IFG
        mov.b #0x00, &P1IES
        mov.b #0x01, &P1IE
 
        ; Initialize stack and enable global interrupts
        mov   #0x0250, r1
        eint
 
        mov    #0x1000, r15
 
 
        /* -------------- SCG1   (<=> R2[7]): turn off SMCLK --------------- */
 
        mov.b  #0x06, &BCSCTL2  ; # Div /8
 
        mov    #0x0008, r2      ; # SCG1=0 (SMCLK on)
        mov    #0x1001, r15
        mov    #0x0020, r14
        call   #WAIT_FUNC
 
        mov    #0x0088, r2      ; # SCG1=1 (SMCLK off)
        mov    #0x1002, r15
        mov    #0x0020, r14
        call   #WAIT_FUNC
 
        mov    #0x1003, r15      ; # SCG1=1 (SMCLK off) with IRQ
        mov    #0x0020, r14
        call   #WAIT_FUNC
 
        mov    #0x1004, r15      ; # SCG1=1 (SMCLK off) return from IRQ
        mov    #0x0020, r14
        call   #WAIT_FUNC
 
        mov    #0x0008, r2      ; # SCG1=0 (SMCLK on)
        mov    #0x1005, r15
        mov    #0x0020, r14
        call   #WAIT_FUNC
 
        mov     #0x2000, r15
 
 
        /* -------------- OSCOFF (<=> R2[5]): turn off LFXT1CLK --------------- */
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1 --> select DCOCLK
        mov    #0x0008, r2      ; # OSCOFF=0 (LFXT1 on)
        mov    #0x2001, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1 --> select DCOCLK
        mov    #0x0028, r2      ; # OSCOFF=1 (LFXT1 off)
        mov    #0x2002, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov    #0x2003, r15      ; # OSCOFF=1 (LFXT1 off) with IRQ
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov    #0x2004, r15      ; # OSCOFF=1 (LFXT1 off) return from IRQ
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov.b  #0x08, &BCSCTL2  ; # Div /1 --> select LFXT1CLK
        mov    #0x0028, r2      ; # OSCOFF=1 (LFXT1 off)
        mov    #0x2005, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1 --> select DCOCLK
        mov    #0x0008, r2      ; # OSCOFF=0 (LFXT1 on)
        mov    #0x2006, r15
        mov    #0x0050, r14
        call   #WAIT_FUNC
 
        mov     #0x3000, r15
 
 
        /* -------------- CPUOFF (<=> R2[4]): turn off CPU    --------------- */
 
        ; Enable GPIO interrupts on P2[0]
        mov.b #0x00, &P2DIR
        mov.b #0x00, &P2IFG
        mov.b #0x00, &P2IES
        mov.b #0x01, &P2IE
 
        mov.b  #0x00, &BCSCTL2  ; # Div /1 --> select DCOCLK
 
        mov    #0x3001, r15
        mov    #0x0008, r2      ; # CPUOFF=0 (CPU on)
        mov    #0x0020, r14
        call   #WAIT_FUNC
 
        mov    #0x3002, r15
        mov    #0x0018, r2      ; # CPUOFF=1 (CPU off)
        mov    #0x0020, r14
        call   #WAIT_FUNC
 
        mov    #0x3003, r15
        mov    #0x0008, r2      ; # CPUOFF=0 (CPU on)
        mov    #0x0020, r14
        call   #WAIT_FUNC
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
 
PORT1_VECTOR:
        push       r14
        mov    #0x0050, r14
        call   #WAIT_FUNC
        pop        r14
        mov.b #0x00, &P1IFG
        reti
 
PORT2_VECTOR:
        push       r14
        mov    #0x0050, r14
        call   #WAIT_FUNC
        pop        r14
        mov.b #0x00, &P2IFG
        bic    #0x10, 0(r1) ;exit lowpower mode
        reti
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word PORT1_VECTOR ; Interrupt  2                      
.word PORT2_VECTOR ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [op_modes.s43] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* CPU OPERATING MODES */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the CPU Operating modes: */`
27			`/* - CPUOFF (<=> R2[4]): turn off CPU. */`
28			`/* - OSCOFF (<=> R2[5]): turn off LFXT_CLK. */`
29			`/* - SCG1 (<=> R2[7]): turn off SMCLK. */`
30			`/===========================================================================/`
31
32			`.global main`
33
34			`.set P1IN, 0x0020`
35			`.set P1OUT, 0x0021`
36			`.set P1DIR, 0x0022`
37			`.set P1IFG, 0x0023`
38			`.set P1IES, 0x0024`
39			`.set P1IE, 0x0025`
40			`.set P1SEL, 0x0026`
41			`.set P2IN, 0x0028`
42			`.set P2OUT, 0x0029`
43			`.set P2DIR, 0x002A`
44			`.set P2IFG, 0x002B`
45			`.set P2IES, 0x002C`
46			`.set P2IE, 0x002D`
47			`.set P2SEL, 0x002E`
48
49			`.set BCSCTL1, 0x0057`
50			`.set BCSCTL2, 0x0058`
51
52
53			`WAIT_FUNC:`
54			`dec r14`
55			`jnz WAIT_FUNC`
56			`ret`
57
58			`main:`
59			`; Enable GPIO interrupts on P1[0]`
60			`mov.b #0x00, &P1DIR`
61			`mov.b #0x00, &P1IFG`
62			`mov.b #0x00, &P1IES`
63			`mov.b #0x01, &P1IE`
64
65			`; Initialize stack and enable global interrupts`
66			`mov #0x0250, r1`
67			`eint`
68
69			`mov #0x1000, r15`
70
71
72			`/* -------------- SCG1 (<=> R2[7]): turn off SMCLK --------------- */`
73
74			`mov.b #0x06, &BCSCTL2 ; # Div /8`
75
76			`mov #0x0008, r2 ; # SCG1=0 (SMCLK on)`
77			`mov #0x1001, r15`
78			`mov #0x0020, r14`
79			`call #WAIT_FUNC`
80
81			`mov #0x0088, r2 ; # SCG1=1 (SMCLK off)`
82			`mov #0x1002, r15`
83			`mov #0x0020, r14`
84			`call #WAIT_FUNC`
85
86			`mov #0x1003, r15 ; # SCG1=1 (SMCLK off) with IRQ`
87			`mov #0x0020, r14`
88			`call #WAIT_FUNC`
89
90			`mov #0x1004, r15 ; # SCG1=1 (SMCLK off) return from IRQ`
91			`mov #0x0020, r14`
92			`call #WAIT_FUNC`
93
94			`mov #0x0008, r2 ; # SCG1=0 (SMCLK on)`
95			`mov #0x1005, r15`
96			`mov #0x0020, r14`
97			`call #WAIT_FUNC`
98
99			`mov #0x2000, r15`
100
101
102			`/* -------------- OSCOFF (<=> R2[5]): turn off LFXT1CLK --------------- */`
103
104			`mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK`
105			`mov #0x0008, r2 ; # OSCOFF=0 (LFXT1 on)`
106			`mov #0x2001, r15`
107			`mov #0x0050, r14`
108			`call #WAIT_FUNC`
109
110			`mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK`
111			`mov #0x0028, r2 ; # OSCOFF=1 (LFXT1 off)`
112			`mov #0x2002, r15`
113			`mov #0x0050, r14`
114			`call #WAIT_FUNC`
115
116			`mov #0x2003, r15 ; # OSCOFF=1 (LFXT1 off) with IRQ`
117			`mov #0x0050, r14`
118			`call #WAIT_FUNC`
119
120			`mov #0x2004, r15 ; # OSCOFF=1 (LFXT1 off) return from IRQ`
121			`mov #0x0050, r14`
122			`call #WAIT_FUNC`
123
124			`mov.b #0x08, &BCSCTL2 ; # Div /1 --> select LFXT1CLK`
125			`mov #0x0028, r2 ; # OSCOFF=1 (LFXT1 off)`
126			`mov #0x2005, r15`
127			`mov #0x0050, r14`
128			`call #WAIT_FUNC`
129
130			`mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK`
131			`mov #0x0008, r2 ; # OSCOFF=0 (LFXT1 on)`
132			`mov #0x2006, r15`
133			`mov #0x0050, r14`
134			`call #WAIT_FUNC`
135
136			`mov #0x3000, r15`
137
138
139			`/* -------------- CPUOFF (<=> R2[4]): turn off CPU --------------- */`
140
141			`; Enable GPIO interrupts on P2[0]`
142			`mov.b #0x00, &P2DIR`
143			`mov.b #0x00, &P2IFG`
144			`mov.b #0x00, &P2IES`
145			`mov.b #0x01, &P2IE`
146
147			`mov.b #0x00, &BCSCTL2 ; # Div /1 --> select DCOCLK`
148
149			`mov #0x3001, r15`
150			`mov #0x0008, r2 ; # CPUOFF=0 (CPU on)`
151			`mov #0x0020, r14`
152			`call #WAIT_FUNC`
153
154			`mov #0x3002, r15`
155			`mov #0x0018, r2 ; # CPUOFF=1 (CPU off)`
156			`mov #0x0020, r14`
157			`call #WAIT_FUNC`
158
159			`mov #0x3003, r15`
160			`mov #0x0008, r2 ; # CPUOFF=0 (CPU on)`
161			`mov #0x0020, r14`
162			`call #WAIT_FUNC`
163
164
165
166			`/* ---------------------- END OF TEST --------------- */`
167			`end_of_test:`
168			`nop`
169			`br #0xffff`
170
171
172			`/* ---------------------- INTERRUPT ROUTINES --------------- */`
173
174			`PORT1_VECTOR:`
175			`push r14`
176			`mov #0x0050, r14`
177			`call #WAIT_FUNC`
178			`pop r14`
179			`mov.b #0x00, &P1IFG`
180			`reti`
181
182			`PORT2_VECTOR:`
183			`push r14`
184			`mov #0x0050, r14`
185			`call #WAIT_FUNC`
186			`pop r14`
187			`mov.b #0x00, &P2IFG`
188			`bic #0x10, 0(r1) ;exit lowpower mode`
189			`reti`
190
191
192			`/* ---------------------- INTERRUPT VECTORS --------------- */`
193
194			`.section .vectors, "a"`
195			`.word end_of_test ; Interrupt 0 (lowest priority)`
196			`.word end_of_test ; Interrupt 1`
197			`.word PORT1_VECTOR ; Interrupt 2`
198			`.word PORT2_VECTOR ; Interrupt 3`
199			`.word end_of_test ; Interrupt 4`
200			`.word end_of_test ; Interrupt 5`
201			`.word end_of_test ; Interrupt 6`
202			`.word end_of_test ; Interrupt 7`
203			`.word end_of_test ; Interrupt 8`
204			`.word end_of_test ; Interrupt 9`
205			`.word end_of_test ; Interrupt 10 Watchdog timer`
206			`.word end_of_test ; Interrupt 11`
207			`.word end_of_test ; Interrupt 12`
208			`.word end_of_test ; Interrupt 13`
209			`.word end_of_test ; Interrupt 14 NMI`
210			`.word main ; Interrupt 15 (highest priority) RESET`