OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [op_modes.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                            CPU OPERATING MODES                            */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the CPU Operating modes:                                             */
27 
/*                                 - CPUOFF (<=> R2[4]): turn off CPU.       */
28 
/*                                 - OSCOFF (<=> R2[5]): turn off LFXT_CLK.  */
29 
/*                                 - SCG1   (<=> R2[7]): turn off SMCLK.     */
30 
/*===========================================================================*/
31 
 
32 
integer smclk_cnt;
33 
always @(negedge mclk)
34 
  if (smclk_en) smclk_cnt <= smclk_cnt+1;
35 
 
36 
integer aclk_cnt;
37 
always @(negedge mclk)
38 
  if (aclk_en) aclk_cnt <= aclk_cnt+1;
39 
 
40 
integer inst_cnt;
41 
always @(inst_number)
42 
  inst_cnt = inst_cnt+1;
43 
 
44 
initial
45 
   begin
46 
      $display(" ===============================================");
47 
      $display("|                 START SIMULATION              |");
48 
      $display(" ===============================================");
49 
      repeat(5) @(posedge mclk);
50 
      stimulus_done = 0;
51 
 
52 
 
53 
      // SCG1   (<=> R2[7]): turn off SMCLK
54 
      //--------------------------------------------------------
55 
 
56 
      @(r15==16'h1001);
57 
      smclk_cnt = 0;
58 
      repeat (84) @(posedge mclk);
59 
      if (smclk_cnt !== 16'h000a) tb_error("====== SCG1 TEST 1: SMCLK IS NOT RUNNING =====");
60 
 
61 
      @(r15==16'h1002);
62 
      smclk_cnt = 0;
63 
      repeat (84) @(posedge mclk);
64 
      if (smclk_cnt !== 16'h0000) tb_error("====== SCG1 TEST 2: SMCLK IS NOT STOPPED =====");
65 
 
66 
      @(r15==16'h1003);
67 
      p1_din[0] = 1'b1;
68 
      repeat (2) @(posedge mclk);
69 
      p1_din[0] = 1'b0;
70 
      smclk_cnt = 0;
71 
      repeat (84) @(posedge mclk);
72 
      if (smclk_cnt !== 16'h000a) tb_error("====== SCG1 TEST 3: SMCLK IS NOT RUNNING DURING IRQ =====");
73 
 
74 
      @(r15==16'h1004);
75 
      smclk_cnt = 0;
76 
      repeat (84) @(posedge mclk);
77 
      if (smclk_cnt !== 16'h0000) tb_error("====== SCG1 TEST 4: SMCLK IS NOT STOPPED =====");
78 
 
79 
      @(r15==16'h1005);
80 
      smclk_cnt = 0;
81 
      repeat (80) @(posedge mclk);
82 
      if (smclk_cnt !== 16'h000a) tb_error("====== SCG1 TEST 5: SMCLK IS NOT RUNNING =====");
83 
 
84 
 
85 
      // OSCOFF  (<=> R2[5]): turn off LFXT1CLK
86 
      //--------------------------------------------------------
87 
 
88 
      @(r15==16'h2001);
89 
      aclk_cnt  = 0;
90 
      smclk_cnt = 0;
91 
      repeat (104) @(posedge mclk);
92 
      if (aclk_cnt  !== 16'h0004) tb_error("====== OSCOFF TEST 1: ACLK  IS NOT RUNNING =====");
93 
      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 1: SMCLK IS NOT RUNNING ON MCLK =====");
94 
 
95 
      @(r15==16'h2002);
96 
      aclk_cnt  = 0;
97 
      smclk_cnt = 0;
98 
      repeat (104) @(posedge mclk);
99 
      if (aclk_cnt  !== 16'h0000) tb_error("====== OSCOFF TEST 2: ACLK  IS NOT STOPPED =====");
100 
      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 2: SMCLK IS NOT RUNNING ON MCLK =====");
101 
 
102 
      @(r15==16'h2003);
103 
      p1_din[0] = 1'b1;
104 
      repeat (2) @(posedge mclk);
105 
      p1_din[0] = 1'b0;
106 
      aclk_cnt  = 0;
107 
      smclk_cnt = 0;
108 
      repeat (104) @(posedge mclk);
109 
      if (aclk_cnt  !== 16'h0003) tb_error("====== OSCOFF TEST 3: ACLK  IS NOT RUNNING DURING IRQ =====");
110 
      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 3: SMCLK IS NOT RUNNING ON MCLK =====");
111 
 
112 
       @(r15==16'h2004);
113 
      aclk_cnt  = 0;
114 
      smclk_cnt = 0;
115 
      repeat (104) @(posedge mclk);
116 
      if (aclk_cnt  !== 16'h0000) tb_error("====== OSCOFF TEST 4: ACLK  IS NOT STOPPED =====");
117 
      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 4: SMCLK IS NOT RUNNING ON MCLK =====");
118 
 
119 
      @(r15==16'h2005);
120 
      aclk_cnt  = 0;
121 
      smclk_cnt = 0;
122 
      repeat (104) @(posedge mclk);
123 
      if (aclk_cnt  !== 16'h0004) tb_error("====== OSCOFF TEST 5: ACLK  IS NOT RUNNING =====");
124 
      if (smclk_cnt !== 16'h0004) tb_error("====== OSCOFF TEST 5: SMCLK IS NOT RUNNING ON LFXT1 =====");
125 
 
126 
      @(r15==16'h2006);
127 
      aclk_cnt  = 0;
128 
      smclk_cnt = 0;
129 
      repeat (104) @(posedge mclk);
130 
      if (aclk_cnt  !== 16'h0003) tb_error("====== OSCOFF TEST 6: ACLK  IS NOT RUNNING =====");
131 
      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 6: SMCLK IS NOT RUNNING ON MCLK =====");
132 
 
133 
 
134 
      // CPUOFF  (<=> R2[4]): turn off CPU
135 
      //--------------------------------------------------------
136 
 
137 
      @(r15==16'h3001);
138 
      @(negedge mclk);
139 
      inst_cnt  = 0;
140 
      repeat (80) @(negedge mclk);
141 
      if (inst_cnt  !== 16'h0034) tb_error("====== CPUOFF TEST 1: CPU IS NOT RUNNING =====");
142 
 
143 
      @(r15==16'h3002);
144 
      repeat (3) @(negedge mclk);
145 
      inst_cnt  = 0;
146 
      repeat (80) @(negedge mclk);
147 
      if (inst_cnt  !== 16'h0000) tb_error("====== CPUOFF TEST 2: CPU IS NOT STOPPED =====");
148 
 
149 
      @(posedge mclk);
150 
      p1_din[0] = 1'b1;
151 
      repeat (2) @(posedge mclk);
152 
      p1_din[0] = 1'b0;
153 
      @(negedge mclk);
154 
      inst_cnt  = 0;
155 
      repeat (80) @(negedge mclk);
156 
      if (inst_cnt !== 16'h002f) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
157 
 
158 
      @(r1==16'h0250);
159 
      repeat (3) @(negedge mclk);
160 
      inst_cnt  = 0;
161 
      repeat (80) @(negedge mclk);
162 
      if (inst_cnt  !== 16'h0000) tb_error("====== CPUOFF TEST 4: CPU IS NOT STOPPED AFTER IRQ =====");
163 
 
164 
      @(posedge mclk);
165 
      p2_din[0] = 1'b1;
166 
      repeat (2) @(posedge mclk);
167 
      p2_din[0] = 1'b0;
168 
      @(negedge mclk);
169 
      inst_cnt  = 0;
170 
      repeat (80) @(negedge mclk);
171 
      if (inst_cnt !== 16'h002f) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ (PORT 2) =====");
172 
 
173 
      @(r15==16'h3003);
174 
      @(negedge mclk);
175 
      inst_cnt  = 0;
176 
      repeat (80) @(negedge mclk);
177 
      if (inst_cnt  !== 16'h0034) tb_error("====== CPUOFF TEST 6: CPU IS NOT RUNNING =====");
178 
 
179 
 
180 
      stimulus_done = 1;
181 
   end
182 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.