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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_push_rom-rd.s43] - Blame information for rev 2

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                     PUSH:   DATA READ ACCESS FROM ROM                     */
/*---------------------------------------------------------------------------*/
/* Test the PUSH instruction with all addressing modes making a read access  */
/* to the ROM.                                                               */
/*===========================================================================*/
 
 
.global main
 
main:
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
 
        # Initialization
        #------------------------
 
        mov     #0x0020, r4        ;# Initialize RAM
        mov     #0x0230, r5
clear_mem_loop:
        clr    0(r5)
        incd     r5
        dec      r4
        jnz     clear_mem_loop
 
 
        mov     #0x0252, r1        ;# Initialize stack pointer
 
 
        mov     #0x1000, r15
 
 
        # Addressing mode: @Rn
        #------------------------
 
        mov     #data_aRn_0x1234, r4
        push                     @r4           ;# PUSH (0x1234  =>  @=0x0250)
 
        mov     #data_aRn_0x5678, r6
        push                     @r6           ;# PUSH (0x5678  =>  @=0x024E)
 
        mov              #0x2000, r15
 
 
        # Addressing mode: @Rn+
        #------------------------
 
        mov     #data_aRni_0x9abc, r4
        push                      @r4+         ;# PUSH (0x9abc  =>  @=0x024C)
        push                      @r4+         ;# PUSH (0xdef0  =>  @=0x024A)
 
        mov     #0x3000, r15
 
 
        # Addressing mode: X(Rn)
        #------------------------
 
        mov     #data_xRn_0x0fed, r4
        push                   26(r4)          ;# PUSH (0x0fed  =>  @=0x0248)
        push                   28(r4)          ;# PUSH (0xcba9  =>  @=0x0246)
 
        mov     #0x4000, r15
 
 
        # Addressing mode: EDE
        #------------------------
.set   EDE_21E,  (__data_start+0x001E)
.set   EDE_220,  (__data_start+0x0020)
 
        push    data_EDE_0x8765                ;# PUSH (0x8765  =>  @=0x0244)
        push    data_EDE_0x4321                ;# PUSH (0x4321  =>  @=0x0242)
 
        mov     #0x5000, r15
 
 
        # Addressing mode: &EDE
        #------------------------
.set   aEDE_222,  0x0222
.set   aEDE_224,  0x0224
 
        push  &data_aEDE_0x1f2e                ;# PUSH (0x1f2e  =>  @=0x0240)
        push  &data_aEDE_0x3d4c                ;# PUSH (0x3d4c  =>  @=0x023E)
 
        mov     #0x6000, r15
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------            DATA TABLE      --------------- */
data_aRn_0x1234:
        .word 0x1234
data_aRn_0x5678:
        .word 0x5678
 
data_aRni_0x9abc:
        .word 0x9abc
        .word 0xdef0
 
data_xRn_0x0fed:
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0000
        .word 0x0fed
        .word 0xcba9
 
data_EDE_0x8765:
        .word 0x8765
data_EDE_0x4321:
        .word 0x4321
 
data_aEDE_0x1f2e:
        .word 0x1f2e
data_aEDE_0x3d4c:
        .word 0x3d4c
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* PUSH: DATA READ ACCESS FROM ROM */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the PUSH instruction with all addressing modes making a read access */`
27			`/* to the ROM. */`
28			`/===========================================================================/`
29
30
31			`.global main`
32
33			`main:`
34			`/* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */`
35
36			`# Initialization`
37			`#------------------------`
38
39			`mov #0x0020, r4 ;# Initialize RAM`
40			`mov #0x0230, r5`
41			`clear_mem_loop:`
42			`clr 0(r5)`
43			`incd r5`
44			`dec r4`
45			`jnz clear_mem_loop`
46
47
48			`mov #0x0252, r1 ;# Initialize stack pointer`
49
50
51			`mov #0x1000, r15`
52
53
54			`# Addressing mode: @Rn`
55			`#------------------------`
56
57			`mov #data_aRn_0x1234, r4`
58			`push @r4 ;# PUSH (0x1234 => @=0x0250)`
59
60			`mov #data_aRn_0x5678, r6`
61			`push @r6 ;# PUSH (0x5678 => @=0x024E)`
62
63			`mov #0x2000, r15`
64
65
66			`# Addressing mode: @Rn+`
67			`#------------------------`
68
69			`mov #data_aRni_0x9abc, r4`
70			`push @r4+ ;# PUSH (0x9abc => @=0x024C)`
71			`push @r4+ ;# PUSH (0xdef0 => @=0x024A)`
72
73			`mov #0x3000, r15`
74
75
76			`# Addressing mode: X(Rn)`
77			`#------------------------`
78
79			`mov #data_xRn_0x0fed, r4`
80			`push 26(r4) ;# PUSH (0x0fed => @=0x0248)`
81			`push 28(r4) ;# PUSH (0xcba9 => @=0x0246)`
82
83			`mov #0x4000, r15`
84
85
86			`# Addressing mode: EDE`
87			`#------------------------`
88			`.set EDE_21E, (__data_start+0x001E)`
89			`.set EDE_220, (__data_start+0x0020)`
90
91			`push data_EDE_0x8765 ;# PUSH (0x8765 => @=0x0244)`
92			`push data_EDE_0x4321 ;# PUSH (0x4321 => @=0x0242)`
93
94			`mov #0x5000, r15`
95
96
97			`# Addressing mode: &EDE`
98			`#------------------------`
99			`.set aEDE_222, 0x0222`
100			`.set aEDE_224, 0x0224`
101
102			`push &data_aEDE_0x1f2e ;# PUSH (0x1f2e => @=0x0240)`
103			`push &data_aEDE_0x3d4c ;# PUSH (0x3d4c => @=0x023E)`
104
105			`mov #0x6000, r15`
106
107
108
109			`/* ---------------------- END OF TEST --------------- */`
110			`end_of_test:`
111			`nop`
112			`br #0xffff`
113
114
115			`/* ---------------------- DATA TABLE --------------- */`
116			`data_aRn_0x1234:`
117			`.word 0x1234`
118			`data_aRn_0x5678:`
119			`.word 0x5678`
120
121			`data_aRni_0x9abc:`
122			`.word 0x9abc`
123			`.word 0xdef0`
124
125			`data_xRn_0x0fed:`
126			`.word 0x0000`
127			`.word 0x0000`
128			`.word 0x0000`
129			`.word 0x0000`
130			`.word 0x0000`
131			`.word 0x0000`
132			`.word 0x0000`
133			`.word 0x0000`
134			`.word 0x0000`
135			`.word 0x0000`
136			`.word 0x0000`
137			`.word 0x0000`
138			`.word 0x0000`
139			`.word 0x0fed`
140			`.word 0xcba9`
141
142			`data_EDE_0x8765:`
143			`.word 0x8765`
144			`data_EDE_0x4321:`
145			`.word 0x4321`
146
147			`data_aEDE_0x1f2e:`
148			`.word 0x1f2e`
149			`data_aEDE_0x3d4c:`
150			`.word 0x3d4c`
151
152
153			`/* ---------------------- INTERRUPT VECTORS --------------- */`
154
155			`.section .vectors, "a"`
156			`.word end_of_test ; Interrupt 0 (lowest priority)`
157			`.word end_of_test ; Interrupt 1`
158			`.word end_of_test ; Interrupt 2`
159			`.word end_of_test ; Interrupt 3`
160			`.word end_of_test ; Interrupt 4`
161			`.word end_of_test ; Interrupt 5`
162			`.word end_of_test ; Interrupt 6`
163			`.word end_of_test ; Interrupt 7`
164			`.word end_of_test ; Interrupt 8`
165			`.word end_of_test ; Interrupt 9`
166			`.word end_of_test ; Interrupt 10 Watchdog timer`
167			`.word end_of_test ; Interrupt 11`
168			`.word end_of_test ; Interrupt 12`
169			`.word end_of_test ; Interrupt 13`
170			`.word end_of_test ; Interrupt 14 NMI`
171			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_push_rom-rd.s43] - Blame information for rev 2