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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_push_rom-rd.v] - Blame information for rev 2

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1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
18 
/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                     PUSH:   DATA READ ACCESS FROM ROM                     */
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/*---------------------------------------------------------------------------*/
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/* Test the PUSH instruction with all addressing modes making a read access  */
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/* to the ROM.                                                               */
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/*===========================================================================*/
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30 
initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
37 
 
38 
      /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
39 
 
40 
      // Initialization
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      @(r15==16'h1000);
42 
      if (r1     !==16'h0252) tb_error("====== SP  initialization (R1 value)      =====");
43 
      if (mem250 !==16'h0000) tb_error("====== RAM Initialization (@0x0250 value) =====");
44 
      if (mem24E !==16'h0000) tb_error("====== RAM Initialization (@0x024e value) =====");
45 
      if (mem24C !==16'h0000) tb_error("====== RAM Initialization (@0x024c value) =====");
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      if (mem24A !==16'h0000) tb_error("====== RAM Initialization (@0x024a value) =====");
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      if (mem248 !==16'h0000) tb_error("====== RAM Initialization (@0x0248 value) =====");
48 
      if (mem246 !==16'h0000) tb_error("====== RAM Initialization (@0x0246 value) =====");
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      if (mem244 !==16'h0000) tb_error("====== RAM Initialization (@0x0244 value) =====");
50 
      if (mem242 !==16'h0000) tb_error("====== RAM Initialization (@0x0242 value) =====");
51 
      if (mem240 !==16'h0000) tb_error("====== RAM Initialization (@0x0240 value) =====");
52 
      if (mem23E !==16'h0000) tb_error("====== RAM Initialization (@0x023e value) =====");
53 
      if (mem23C !==16'h0000) tb_error("====== RAM Initialization (@0x023c value) =====");
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      if (mem23A !==16'h0000) tb_error("====== RAM Initialization (@0x023a value) =====");
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      if (mem238 !==16'h0000) tb_error("====== RAM Initialization (@0x0238 value) =====");
56 
      if (mem236 !==16'h0000) tb_error("====== RAM Initialization (@0x0236 value) =====");
57 
      if (mem234 !==16'h0000) tb_error("====== RAM Initialization (@0x0234 value) =====");
58 
      if (mem232 !==16'h0000) tb_error("====== RAM Initialization (@0x0232 value) =====");
59 
      if (mem230 !==16'h0000) tb_error("====== RAM Initialization (@0x0230 value) =====");
60 
 
61 
 
62 
      // Addressing mode: @Rn
63 
      @(r15==16'h2000);
64 
      if (r1     !==16'h024E) tb_error("====== PUSH (@Rn mode): SP value      =====");
65 
      if (mem250 !==16'h1234) tb_error("====== PUSH (@Rn mode): @0x0250 value =====");
66 
      if (mem24E !==16'h5678) tb_error("====== PUSH (@Rn mode): @0x024E value =====");
67 
      if (mem24C !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x024c value =====");
68 
      if (mem24A !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x024a value =====");
69 
      if (mem248 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0248 value =====");
70 
      if (mem246 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0246 value =====");
71 
      if (mem244 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0244 value =====");
72 
      if (mem242 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0242 value =====");
73 
      if (mem240 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0240 value =====");
74 
      if (mem23E !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x023e value =====");
75 
      if (mem23C !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x023c value =====");
76 
      if (mem23A !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x023a value =====");
77 
      if (mem238 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0238 value =====");
78 
      if (mem236 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0236 value =====");
79 
      if (mem234 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0234 value =====");
80 
      if (mem232 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0232 value =====");
81 
      if (mem230 !==16'h0000) tb_error("====== PUSH (@Rn mode): @0x0230 value =====");
82 
 
83 
 
84 
      // Addressing mode: @Rn+
85 
      @(r15==16'h3000);
86 
      if (r1     !==16'h024a) tb_error("====== PUSH (@Rn+ mode): SP value      =====");
87 
      if (mem250 !==16'h1234) tb_error("====== PUSH (@Rn+ mode): @0x0250 value =====");
88 
      if (mem24E !==16'h5678) tb_error("====== PUSH (@Rn+ mode): @0x024E value =====");
89 
      if (mem24C !==16'h9abc) tb_error("====== PUSH (@Rn+ mode): @0x024c value =====");
90 
      if (mem24A !==16'hdef0) tb_error("====== PUSH (@Rn+ mode): @0x024a value =====");
91 
      if (mem248 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0248 value =====");
92 
      if (mem246 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0246 value =====");
93 
      if (mem244 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0244 value =====");
94 
      if (mem242 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0242 value =====");
95 
      if (mem240 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0240 value =====");
96 
      if (mem23E !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x023e value =====");
97 
      if (mem23C !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x023c value =====");
98 
      if (mem23A !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x023a value =====");
99 
      if (mem238 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0238 value =====");
100 
      if (mem236 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0236 value =====");
101 
      if (mem234 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0234 value =====");
102 
      if (mem232 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0232 value =====");
103 
      if (mem230 !==16'h0000) tb_error("====== PUSH (@Rn+ mode): @0x0230 value =====");
104 
 
105 
 
106 
      // Addressing mode: X(Rn)
107 
      @(r15==16'h4000);
108 
      if (r1     !==16'h0246) tb_error("====== PUSH (X(Rn) mode): SP value      =====");
109 
      if (mem250 !==16'h1234) tb_error("====== PUSH (X(Rn) mode): @0x0250 value =====");
110 
      if (mem24E !==16'h5678) tb_error("====== PUSH (X(Rn) mode): @0x024E value =====");
111 
      if (mem24C !==16'h9abc) tb_error("====== PUSH (X(Rn) mode): @0x024c value =====");
112 
      if (mem24A !==16'hdef0) tb_error("====== PUSH (X(Rn) mode): @0x024a value =====");
113 
      if (mem248 !==16'h0fed) tb_error("====== PUSH (X(Rn) mode): @0x0248 value =====");
114 
      if (mem246 !==16'hcba9) tb_error("====== PUSH (X(Rn) mode): @0x0246 value =====");
115 
      if (mem244 !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x0244 value =====");
116 
      if (mem242 !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x0242 value =====");
117 
      if (mem240 !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x0240 value =====");
118 
      if (mem23E !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x023e value =====");
119 
      if (mem23C !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x023c value =====");
120 
      if (mem23A !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x023a value =====");
121 
      if (mem238 !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x0238 value =====");
122 
      if (mem236 !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x0236 value =====");
123 
      if (mem234 !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x0234 value =====");
124 
      if (mem232 !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x0232 value =====");
125 
      if (mem230 !==16'h0000) tb_error("====== PUSH (X(Rn) mode): @0x0230 value =====");
126 
 
127 
 
128 
      // Addressing mode: EDE
129 
      @(r15==16'h5000);
130 
      if (r1     !==16'h0242) tb_error("====== PUSH (EDE mode): SP value      =====");
131 
      if (mem250 !==16'h1234) tb_error("====== PUSH (EDE mode): @0x0250 value =====");
132 
      if (mem24E !==16'h5678) tb_error("====== PUSH (EDE mode): @0x024E value =====");
133 
      if (mem24C !==16'h9abc) tb_error("====== PUSH (EDE mode): @0x024c value =====");
134 
      if (mem24A !==16'hdef0) tb_error("====== PUSH (EDE mode): @0x024a value =====");
135 
      if (mem248 !==16'h0fed) tb_error("====== PUSH (EDE mode): @0x0248 value =====");
136 
      if (mem246 !==16'hcba9) tb_error("====== PUSH (EDE mode): @0x0246 value =====");
137 
      if (mem244 !==16'h8765) tb_error("====== PUSH (EDE mode): @0x0244 value =====");
138 
      if (mem242 !==16'h4321) tb_error("====== PUSH (EDE mode): @0x0242 value =====");
139 
      if (mem240 !==16'h0000) tb_error("====== PUSH (EDE mode): @0x0240 value =====");
140 
      if (mem23E !==16'h0000) tb_error("====== PUSH (EDE mode): @0x023e value =====");
141 
      if (mem23C !==16'h0000) tb_error("====== PUSH (EDE mode): @0x023c value =====");
142 
      if (mem23A !==16'h0000) tb_error("====== PUSH (EDE mode): @0x023a value =====");
143 
      if (mem238 !==16'h0000) tb_error("====== PUSH (EDE mode): @0x0238 value =====");
144 
      if (mem236 !==16'h0000) tb_error("====== PUSH (EDE mode): @0x0236 value =====");
145 
      if (mem234 !==16'h0000) tb_error("====== PUSH (EDE mode): @0x0234 value =====");
146 
      if (mem232 !==16'h0000) tb_error("====== PUSH (EDE mode): @0x0232 value =====");
147 
      if (mem230 !==16'h0000) tb_error("====== PUSH (EDE mode): @0x0230 value =====");
148 
 
149 
 
150 
      // Addressing mode: &EDE
151 
      @(r15==16'h6000);
152 
      if (r1     !==16'h023E) tb_error("====== PUSH (&EDE mode): SP value      =====");
153 
      if (mem250 !==16'h1234) tb_error("====== PUSH (&EDE mode): @0x0250 value =====");
154 
      if (mem24E !==16'h5678) tb_error("====== PUSH (&EDE mode): @0x024E value =====");
155 
      if (mem24C !==16'h9abc) tb_error("====== PUSH (&EDE mode): @0x024c value =====");
156 
      if (mem24A !==16'hdef0) tb_error("====== PUSH (&EDE mode): @0x024a value =====");
157 
      if (mem248 !==16'h0fed) tb_error("====== PUSH (&EDE mode): @0x0248 value =====");
158 
      if (mem246 !==16'hcba9) tb_error("====== PUSH (&EDE mode): @0x0246 value =====");
159 
      if (mem244 !==16'h8765) tb_error("====== PUSH (&EDE mode): @0x0244 value =====");
160 
      if (mem242 !==16'h4321) tb_error("====== PUSH (&EDE mode): @0x0242 value =====");
161 
      if (mem240 !==16'h1f2e) tb_error("====== PUSH (&EDE mode): @0x0240 value =====");
162 
      if (mem23E !==16'h3d4c) tb_error("====== PUSH (&EDE mode): @0x023e value =====");
163 
      if (mem23C !==16'h0000) tb_error("====== PUSH (&EDE mode): @0x023c value =====");
164 
      if (mem23A !==16'h0000) tb_error("====== PUSH (&EDE mode): @0x023a value =====");
165 
      if (mem238 !==16'h0000) tb_error("====== PUSH (&EDE mode): @0x0238 value =====");
166 
      if (mem236 !==16'h0000) tb_error("====== PUSH (&EDE mode): @0x0236 value =====");
167 
      if (mem234 !==16'h0000) tb_error("====== PUSH (&EDE mode): @0x0234 value =====");
168 
      if (mem232 !==16'h0000) tb_error("====== PUSH (&EDE mode): @0x0232 value =====");
169 
      if (mem230 !==16'h0000) tb_error("====== PUSH (&EDE mode): @0x0230 value =====");
170 
 
171 
 
172 
 
173 
 
174 
      stimulus_done = 1;
175 
   end
176 
 

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