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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_reti.s43] - Blame information for rev 2

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                 SINGLE-OPERAND ARITHMETIC: CALL  INSTRUCTION              */
/*---------------------------------------------------------------------------*/
/* Test the CALL  instruction.                                               */
/*===========================================================================*/
 
 
.global main
 
        mov     #0x1234, r3
        mov     #0x1234, r4
        mov     #0x1234, r5
        mov     #0x1234, r6
        mov     #0x1234, r7
        mov     #0x1234, r8
        mov     #0x1234, r9
        mov     #0x1234, r10
        mov     #0x1234, r11
        mov     #0x1234, r12
        mov     #0x1234, r13
        mov     #0x1234, r14
main:
        # Test RESET vector
        #------------------------
        mov     #0x1000, r15
 
 
        # Test RETI instruction
        #------------------------
 
        # Pre-initialize stack
        mov             #0x0252, r1
        push #RETI_ROUTINE
        push            #0x0145
        mov     #0x0000, &0x0200
 
        # Run RETI test
        mov     #0x0000, r2
        mov     #0x0000, r5
        reti
end_of_reti_test:
 
        mov     #0x2000, r15
 
 
        # Test IRQ  0
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x3000, r15
 
wait_irq00:
        cmp     #0x5678, r6
        jne     wait_irq00
 
        mov     #0x3001, r15
 
 
        # Test IRQ  1
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x4000, r15
 
wait_irq01:
        cmp     #0x9abc, r6
        jne     wait_irq01
 
        mov     #0x4001, r15
 
 
        # Test IRQ  2
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x5000, r15
 
wait_irq02:
        cmp     #0xdef1, r6
        jne     wait_irq02
 
        mov     #0x5001, r15
 
 
        # Test IRQ  3
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x6000, r15
 
wait_irq03:
        cmp     #0x2345, r6
        jne     wait_irq03
 
        mov     #0x6001, r15
 
 
        # Test IRQ  4
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x7000, r15
 
wait_irq04:
        cmp     #0x6789, r6
        jne     wait_irq04
 
        mov     #0x7001, r15
 
 
        # Test IRQ  5
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x8000, r15
 
wait_irq05:
        cmp     #0xabcd, r6
        jne     wait_irq05
 
        mov     #0x8001, r15
 
 
        # Test IRQ  6
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x9000, r15
 
wait_irq06:
        cmp     #0xef12, r6
        jne     wait_irq06
 
        mov     #0x9001, r15
 
 
        # Test IRQ  7
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xa000, r15
 
wait_irq07:
        cmp     #0x3456, r6
        jne     wait_irq07
 
        mov     #0xa001, r15
 
 
        # Test IRQ  8
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xb000, r15
 
wait_irq08:
        cmp     #0x789a, r6
        jne     wait_irq08
 
        mov     #0xb001, r15
 
 
        # Test IRQ  9
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xc000, r15
 
wait_irq09:
        cmp     #0xbcde, r6
        jne     wait_irq09
 
        mov     #0xc001, r15
 
 
        # Test IRQ 10
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xd000, r15
 
wait_irq10:
        cmp     #0xf123, r6
        jne     wait_irq10
 
        mov     #0xd001, r15
 
 
        # Test IRQ 11
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xe000, r15
 
wait_irq11:
        cmp     #0x4567, r6
        jne     wait_irq11
 
        mov     #0xe001, r15
 
 
        # Test IRQ 12
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf000, r15
 
wait_irq12:
        cmp     #0x89ab, r6
        jne     wait_irq12
 
        mov     #0xf001, r15
 
 
        # Test IRQ 13
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf100, r15
 
wait_irq13:
        cmp     #0xcdef, r6
        jne     wait_irq13
 
        mov     #0xf101, r15
 
 
        # Test IRQ NMI:  rising edge
        #----------------------------
.set   WDTCTL, 0x0120
.set   IE1,    0x0000
.set   IFG1,   0x0002
 
        mov     #0x5a00, &WDTCTL  ; NMI Edge selection: rising
        bic.b   #0x0010, &IFG1    ; Clear NMI flag
        bis.b   #0x0010, &IE1     ; Enable NMI
 
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf200, r15
 
wait_nmi:
        mov     #0xa5a5, &0x0200
        cmp     #0x0123, r6
        jne    wait_nmi
 
        mov.b      &IE1,  r9
        mov.b      &IFG1, r10
 
        mov     #0xf201, r15
 
 
 
        /* ----------------------    END OF TEST   --------------- */
end_of_test:
        nop
        br #0xffff
 
 
 
        /* ----------------------    FUNCTIONS    --------------- */
 
RETI_ROUTINE:
        mov #0x1234, r5
        jmp end_of_reti_test
 
 
IRQ00_ROUTINE:
        mov #0x5678, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ01_ROUTINE:
        mov #0x9abc, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ02_ROUTINE:
        mov #0xdef1, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ03_ROUTINE:
        mov #0x2345, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ04_ROUTINE:
        mov #0x6789, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ05_ROUTINE:
        mov #0xabcd, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ06_ROUTINE:
        mov #0xef12, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ07_ROUTINE:
        mov #0x3456, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ08_ROUTINE:
        mov #0x789a, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ09_ROUTINE:
        mov #0xbcde, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ10_ROUTINE:
        mov #0xf123, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ11_ROUTINE:
        mov #0x4567, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ12_ROUTINE:
        mov #0x89ab, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ13_ROUTINE:
        mov #0xcdef, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
NMI_ROUTINE:
        mov #0x0123, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
        nop
        nop
        nop
        nop
        nop
 
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word IRQ00_ROUTINE     ; Interrupt  0 (lowest priority)    
.word IRQ01_ROUTINE     ; Interrupt  1                      
.word IRQ02_ROUTINE     ; Interrupt  2                      
.word IRQ03_ROUTINE     ; Interrupt  3                      
.word IRQ04_ROUTINE     ; Interrupt  4                      
.word IRQ05_ROUTINE     ; Interrupt  5                      
.word IRQ06_ROUTINE     ; Interrupt  6                      
.word IRQ07_ROUTINE     ; Interrupt  7                      
.word IRQ08_ROUTINE     ; Interrupt  8                      
.word IRQ09_ROUTINE     ; Interrupt  9                      
.word IRQ10_ROUTINE     ; Interrupt 10                      Watchdog timer
.word IRQ11_ROUTINE     ; Interrupt 11                      
.word IRQ12_ROUTINE     ; Interrupt 12                      
.word IRQ13_ROUTINE     ; Interrupt 13                      
.word NMI_ROUTINE       ; Interrupt 14                      NMI
.word main              ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_reti.s43] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* SINGLE-OPERAND ARITHMETIC: CALL INSTRUCTION */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the CALL instruction. */`
27			`/===========================================================================/`
28
29
30			`.global main`
31
32			`mov #0x1234, r3`
33			`mov #0x1234, r4`
34			`mov #0x1234, r5`
35			`mov #0x1234, r6`
36			`mov #0x1234, r7`
37			`mov #0x1234, r8`
38			`mov #0x1234, r9`
39			`mov #0x1234, r10`
40			`mov #0x1234, r11`
41			`mov #0x1234, r12`
42			`mov #0x1234, r13`
43			`mov #0x1234, r14`
44			`main:`
45			`# Test RESET vector`
46			`#------------------------`
47			`mov #0x1000, r15`
48
49
50			`# Test RETI instruction`
51			`#------------------------`
52
53			`# Pre-initialize stack`
54			`mov #0x0252, r1`
55			`push #RETI_ROUTINE`
56			`push #0x0145`
57			`mov #0x0000, &0x0200`
58
59			`# Run RETI test`
60			`mov #0x0000, r2`
61			`mov #0x0000, r5`
62			`reti`
63			`end_of_reti_test:`
64
65			`mov #0x2000, r15`
66
67
68			`# Test IRQ 0`
69			`#-------------------------`
70
71			`mov #0x0008, r2 ; Enable interrupts`
72			`mov #0x0000, r6`
73			`mov #0xaaaa, r7`
74			`mov #0x5555, r8`
75			`mov #0x3000, r15`
76
77			`wait_irq00:`
78			`cmp #0x5678, r6`
79			`jne wait_irq00`
80
81			`mov #0x3001, r15`
82
83
84			`# Test IRQ 1`
85			`#-------------------------`
86
87			`mov #0x0008, r2 ; Enable interrupts`
88			`mov #0x0000, r6`
89			`mov #0xaaaa, r7`
90			`mov #0x5555, r8`
91			`mov #0x4000, r15`
92
93			`wait_irq01:`
94			`cmp #0x9abc, r6`
95			`jne wait_irq01`
96
97			`mov #0x4001, r15`
98
99
100			`# Test IRQ 2`
101			`#-------------------------`
102
103			`mov #0x0008, r2 ; Enable interrupts`
104			`mov #0x0000, r6`
105			`mov #0xaaaa, r7`
106			`mov #0x5555, r8`
107			`mov #0x5000, r15`
108
109			`wait_irq02:`
110			`cmp #0xdef1, r6`
111			`jne wait_irq02`
112
113			`mov #0x5001, r15`
114
115
116			`# Test IRQ 3`
117			`#-------------------------`
118
119			`mov #0x0008, r2 ; Enable interrupts`
120			`mov #0x0000, r6`
121			`mov #0xaaaa, r7`
122			`mov #0x5555, r8`
123			`mov #0x6000, r15`
124
125			`wait_irq03:`
126			`cmp #0x2345, r6`
127			`jne wait_irq03`
128
129			`mov #0x6001, r15`
130
131
132			`# Test IRQ 4`
133			`#-------------------------`
134
135			`mov #0x0008, r2 ; Enable interrupts`
136			`mov #0x0000, r6`
137			`mov #0xaaaa, r7`
138			`mov #0x5555, r8`
139			`mov #0x7000, r15`
140
141			`wait_irq04:`
142			`cmp #0x6789, r6`
143			`jne wait_irq04`
144
145			`mov #0x7001, r15`
146
147
148			`# Test IRQ 5`
149			`#-------------------------`
150
151			`mov #0x0008, r2 ; Enable interrupts`
152			`mov #0x0000, r6`
153			`mov #0xaaaa, r7`
154			`mov #0x5555, r8`
155			`mov #0x8000, r15`
156
157			`wait_irq05:`
158			`cmp #0xabcd, r6`
159			`jne wait_irq05`
160
161			`mov #0x8001, r15`
162
163
164			`# Test IRQ 6`
165			`#-------------------------`
166
167			`mov #0x0008, r2 ; Enable interrupts`
168			`mov #0x0000, r6`
169			`mov #0xaaaa, r7`
170			`mov #0x5555, r8`
171			`mov #0x9000, r15`
172
173			`wait_irq06:`
174			`cmp #0xef12, r6`
175			`jne wait_irq06`
176
177			`mov #0x9001, r15`
178
179
180			`# Test IRQ 7`
181			`#-------------------------`
182
183			`mov #0x0008, r2 ; Enable interrupts`
184			`mov #0x0000, r6`
185			`mov #0xaaaa, r7`
186			`mov #0x5555, r8`
187			`mov #0xa000, r15`
188
189			`wait_irq07:`
190			`cmp #0x3456, r6`
191			`jne wait_irq07`
192
193			`mov #0xa001, r15`
194
195
196			`# Test IRQ 8`
197			`#-------------------------`
198
199			`mov #0x0008, r2 ; Enable interrupts`
200			`mov #0x0000, r6`
201			`mov #0xaaaa, r7`
202			`mov #0x5555, r8`
203			`mov #0xb000, r15`
204
205			`wait_irq08:`
206			`cmp #0x789a, r6`
207			`jne wait_irq08`
208
209			`mov #0xb001, r15`
210
211
212			`# Test IRQ 9`
213			`#-------------------------`
214
215			`mov #0x0008, r2 ; Enable interrupts`
216			`mov #0x0000, r6`
217			`mov #0xaaaa, r7`
218			`mov #0x5555, r8`
219			`mov #0xc000, r15`
220
221			`wait_irq09:`
222			`cmp #0xbcde, r6`
223			`jne wait_irq09`
224
225			`mov #0xc001, r15`
226
227
228			`# Test IRQ 10`
229			`#-------------------------`
230
231			`mov #0x0008, r2 ; Enable interrupts`
232			`mov #0x0000, r6`
233			`mov #0xaaaa, r7`
234			`mov #0x5555, r8`
235			`mov #0xd000, r15`
236
237			`wait_irq10:`
238			`cmp #0xf123, r6`
239			`jne wait_irq10`
240
241			`mov #0xd001, r15`
242
243
244			`# Test IRQ 11`
245			`#-------------------------`
246
247			`mov #0x0008, r2 ; Enable interrupts`
248			`mov #0x0000, r6`
249			`mov #0xaaaa, r7`
250			`mov #0x5555, r8`
251			`mov #0xe000, r15`
252
253			`wait_irq11:`
254			`cmp #0x4567, r6`
255			`jne wait_irq11`
256
257			`mov #0xe001, r15`
258
259
260			`# Test IRQ 12`
261			`#-------------------------`
262
263			`mov #0x0008, r2 ; Enable interrupts`
264			`mov #0x0000, r6`
265			`mov #0xaaaa, r7`
266			`mov #0x5555, r8`
267			`mov #0xf000, r15`
268
269			`wait_irq12:`
270			`cmp #0x89ab, r6`
271			`jne wait_irq12`
272
273			`mov #0xf001, r15`
274
275
276			`# Test IRQ 13`
277			`#-------------------------`
278
279			`mov #0x0008, r2 ; Enable interrupts`
280			`mov #0x0000, r6`
281			`mov #0xaaaa, r7`
282			`mov #0x5555, r8`
283			`mov #0xf100, r15`
284
285			`wait_irq13:`
286			`cmp #0xcdef, r6`
287			`jne wait_irq13`
288
289			`mov #0xf101, r15`
290
291
292			`# Test IRQ NMI: rising edge`
293			`#----------------------------`
294			`.set WDTCTL, 0x0120`
295			`.set IE1, 0x0000`
296			`.set IFG1, 0x0002`
297
298			`mov #0x5a00, &WDTCTL ; NMI Edge selection: rising`
299			`bic.b #0x0010, &IFG1 ; Clear NMI flag`
300			`bis.b #0x0010, &IE1 ; Enable NMI`
301
302			`mov #0x0000, r6`
303			`mov #0xaaaa, r7`
304			`mov #0x5555, r8`
305			`mov #0xf200, r15`
306
307			`wait_nmi:`
308			`mov #0xa5a5, &0x0200`
309			`cmp #0x0123, r6`
310			`jne wait_nmi`
311
312			`mov.b &IE1, r9`
313			`mov.b &IFG1, r10`
314
315			`mov #0xf201, r15`
316
317
318
319			`/* ---------------------- END OF TEST --------------- */`
320			`end_of_test:`
321			`nop`
322			`br #0xffff`
323
324
325
326			`/* ---------------------- FUNCTIONS --------------- */`
327
328			`RETI_ROUTINE:`
329			`mov #0x1234, r5`
330			`jmp end_of_reti_test`
331
332
333			`IRQ00_ROUTINE:`
334			`mov #0x5678, r6`
335			`mov r2, r7 ; Save Status register`
336			`mov r1, r8 ; Save Stack register`
337			`reti`
338
339			`IRQ01_ROUTINE:`
340			`mov #0x9abc, r6`
341			`mov r2, r7 ; Save Status register`
342			`mov r1, r8 ; Save Stack register`
343			`reti`
344
345			`IRQ02_ROUTINE:`
346			`mov #0xdef1, r6`
347			`mov r2, r7 ; Save Status register`
348			`mov r1, r8 ; Save Stack register`
349			`reti`
350
351			`IRQ03_ROUTINE:`
352			`mov #0x2345, r6`
353			`mov r2, r7 ; Save Status register`
354			`mov r1, r8 ; Save Stack register`
355			`reti`
356
357			`IRQ04_ROUTINE:`
358			`mov #0x6789, r6`
359			`mov r2, r7 ; Save Status register`
360			`mov r1, r8 ; Save Stack register`
361			`reti`
362
363			`IRQ05_ROUTINE:`
364			`mov #0xabcd, r6`
365			`mov r2, r7 ; Save Status register`
366			`mov r1, r8 ; Save Stack register`
367			`reti`
368
369			`IRQ06_ROUTINE:`
370			`mov #0xef12, r6`
371			`mov r2, r7 ; Save Status register`
372			`mov r1, r8 ; Save Stack register`
373			`reti`
374
375			`IRQ07_ROUTINE:`
376			`mov #0x3456, r6`
377			`mov r2, r7 ; Save Status register`
378			`mov r1, r8 ; Save Stack register`
379			`reti`
380
381			`IRQ08_ROUTINE:`
382			`mov #0x789a, r6`
383			`mov r2, r7 ; Save Status register`
384			`mov r1, r8 ; Save Stack register`
385			`reti`
386
387			`IRQ09_ROUTINE:`
388			`mov #0xbcde, r6`
389			`mov r2, r7 ; Save Status register`
390			`mov r1, r8 ; Save Stack register`
391			`reti`
392
393			`IRQ10_ROUTINE:`
394			`mov #0xf123, r6`
395			`mov r2, r7 ; Save Status register`
396			`mov r1, r8 ; Save Stack register`
397			`reti`
398
399			`IRQ11_ROUTINE:`
400			`mov #0x4567, r6`
401			`mov r2, r7 ; Save Status register`
402			`mov r1, r8 ; Save Stack register`
403			`reti`
404
405			`IRQ12_ROUTINE:`
406			`mov #0x89ab, r6`
407			`mov r2, r7 ; Save Status register`
408			`mov r1, r8 ; Save Stack register`
409			`reti`
410
411			`IRQ13_ROUTINE:`
412			`mov #0xcdef, r6`
413			`mov r2, r7 ; Save Status register`
414			`mov r1, r8 ; Save Stack register`
415			`reti`
416
417			`NMI_ROUTINE:`
418			`mov #0x0123, r6`
419			`mov r2, r7 ; Save Status register`
420			`mov r1, r8 ; Save Stack register`
421			`reti`
422
423			`nop`
424			`nop`
425			`nop`
426			`nop`
427			`nop`
428
429
430
431			`/* ---------------------- INTERRUPT VECTORS --------------- */`
432
433			`.section .vectors, "a"`
434			`.word IRQ00_ROUTINE ; Interrupt 0 (lowest priority)`
435			`.word IRQ01_ROUTINE ; Interrupt 1`
436			`.word IRQ02_ROUTINE ; Interrupt 2`
437			`.word IRQ03_ROUTINE ; Interrupt 3`
438			`.word IRQ04_ROUTINE ; Interrupt 4`
439			`.word IRQ05_ROUTINE ; Interrupt 5`
440			`.word IRQ06_ROUTINE ; Interrupt 6`
441			`.word IRQ07_ROUTINE ; Interrupt 7`
442			`.word IRQ08_ROUTINE ; Interrupt 8`
443			`.word IRQ09_ROUTINE ; Interrupt 9`
444			`.word IRQ10_ROUTINE ; Interrupt 10 Watchdog timer`
445			`.word IRQ11_ROUTINE ; Interrupt 11`
446			`.word IRQ12_ROUTINE ; Interrupt 12`
447			`.word IRQ13_ROUTINE ; Interrupt 13`
448			`.word NMI_ROUTINE ; Interrupt 14 NMI`
449			`.word main ; Interrupt 15 (highest priority) RESET`