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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
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olivier.gi |
//=============================================================================
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// Module specific modules
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//=============================================================================
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+incdir+../../../rtl/verilog/
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../../../rtl/verilog/openMSP430.inc
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../../../rtl/verilog/openMSP430.v
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../../../rtl/verilog/frontend.v
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../../../rtl/verilog/execution_unit.v
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../../../rtl/verilog/register_file.v
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../../../rtl/verilog/alu.v
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../../../rtl/verilog/mem_backbone.v
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../../../rtl/verilog/clock_module.v
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../../../rtl/verilog/sfr.v
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../../../rtl/verilog/dbg.v
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../../../rtl/verilog/dbg_hwbrk.v
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../../../rtl/verilog/dbg_uart.v
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../../../rtl/verilog/watchdog.v
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../../../rtl/verilog/periph/gpio.v
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../../../rtl/verilog/periph/timerA.v
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../../../rtl/verilog/periph/template_periph_8b.v
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../../../rtl/verilog/periph/template_periph_16b.v
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//=============================================================================
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// Testbench related
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//=============================================================================
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+incdir+../../../bench/verilog/
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../../../bench/verilog/tb_openMSP430.v
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../../../bench/verilog/ram.v
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../../../bench/verilog/msp_debug.v
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