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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [tA_compare.v] - Blame information for rev 180

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1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                                  TIMER A                                  */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the timer A:                                                         */
27 
/*                        - Check the timer compare features.                */
28 18 olivier.gi 
/*                                                                           */
29 
/* Author(s):                                                                */
30 
/*             - Olivier Girard,    olgirard@gmail.com                       */
31 
/*                                                                           */
32 
/*---------------------------------------------------------------------------*/
33 19 olivier.gi 
/* $Rev: 180 $                                                                */
34 
/* $LastChangedBy: olivier.girard $                                          */
35 
/* $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $          */
36 2 olivier.gi 
/*===========================================================================*/
37 
 
38 
integer my_counter;
39 
always @ (posedge mclk)
40 
  my_counter <=  my_counter+1;
41 
 
42 
 
43 
initial
44 
   begin
45 
      $display(" ===============================================");
46 
      $display("|                 START SIMULATION              |");
47 
      $display(" ===============================================");
48 
      repeat(5) @(posedge mclk);
49 
      stimulus_done = 0;
50 
 
51 180 olivier.gi 
`ifdef ASIC_CLOCKING
52 134 olivier.gi 
      $display(" ===============================================");
53 
      $display("|               SIMULATION SKIPPED              |");
54 
      $display("|   (this test is not supported in ASIC mode)   |");
55 
      $display(" ===============================================");
56 
      $finish;
57 
`else
58 
 
59 2 olivier.gi 
      // TIMER A TEST:  UP MODE
60 
      //--------------------------------------------------------
61 
 
62 
      @(mem200 === 16'h0001);  // Check Comparator 0
63 
      @(posedge ta_out0);
64 
      @(negedge mclk);
65 
      my_counter = 0;
66 
      @(posedge irq_ta1);
67 
      if (my_counter !== 32'h2) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
68 
 
69 
      @(negedge ta_out0);
70 
      @(negedge mclk);
71 
      my_counter = 0;
72 
      @(posedge irq_ta1);
73 
      if (my_counter !== 32'h2) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
74 
      @(posedge ta_out0);
75 
      if (my_counter !== 32'h2C) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
76 
 
77 
      @(posedge irq_ta0);
78 
      @(negedge mclk);
79 
      my_counter = 0;
80 
      @(posedge irq_ta1);
81 
      if (my_counter !== 32'h2) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
82 
 
83 
 
84 
      @(mem200 === 16'h0002);  // Check Comparator 1
85 
      @(posedge ta_out1);
86 
      @(negedge mclk);
87 
      my_counter = 0;
88 
      @(posedge ta_out0);
89 
      if (my_counter !== 32'h20) tb_error("====== TIMER_A COMPARE 1: UP MODE =====");
90 
 
91 
      @(negedge ta_out1);
92 
      @(negedge mclk);
93 
      my_counter = 0;
94 
      @(negedge ta_out0);
95 
      if (my_counter !== 32'h20) tb_error("====== TIMER_A COMPARE 1: UP MODE =====");
96 
 
97 
      @(posedge irq_ta1);
98 
      @(negedge mclk);
99 
      my_counter = 0;
100 
      @(posedge ta_out0);
101 
      if (my_counter !== 32'h20) tb_error("====== TIMER_A COMPARE 1: UP MODE =====");
102 
 
103 
 
104 
      @(mem200 === 16'h0003);  // Check Comparator 2
105 
      @(posedge ta_out2);
106 
      @(negedge mclk);
107 
      my_counter = 0;
108 
      @(posedge ta_out0);
109 
      if (my_counter !== 32'h12) tb_error("====== TIMER_A COMPARE 2: UP MODE =====");
110 
 
111 
      @(negedge ta_out2);
112 
      @(negedge mclk);
113 
      my_counter = 0;
114 
      @(negedge ta_out0);
115 
      if (my_counter !== 32'h12) tb_error("====== TIMER_A COMPARE 2: UP MODE =====");
116 
 
117 
      @(posedge irq_ta1);
118 
      @(negedge mclk);
119 
      my_counter = 0;
120 
      @(posedge ta_out0);
121 
      if (my_counter !== 32'h12) tb_error("====== TIMER_A COMPARE 2: UP MODE =====");
122 
 
123 
 
124 
      // TIMER A TEST:  CONTINUOUS MODE
125 
      //--------------------------------------------------------
126 
 
127 
      @(mem200 === 16'h0001);
128 
      @(posedge irq_ta1);
129 
      @(negedge mclk);
130 
      my_counter = 0;
131 
      @(negedge irq_ta1);
132 
      repeat(10) @(negedge mclk);
133 
      if (mem206 !== 16'h000A) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 1 =====");
134 
 
135 
      @(posedge ta_out0);
136 
      if (my_counter !== 32'h60) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 1 =====");
137 
 
138 
      @(posedge ta_out1);
139 
      if (my_counter !== 32'hC0) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 1 =====");
140 
      @(negedge irq_ta1);
141 
      repeat(10) @(negedge mclk);
142 
      if (mem206 !== 16'h0002) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 1 =====");
143 
 
144 
      @(posedge ta_out2);
145 
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 1 =====");
146 
      @(negedge irq_ta1);
147 
      repeat(10) @(negedge mclk);
148 
      if (mem206 !== 16'h0004) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 1 =====");
149 
 
150 
 
151 
      @(mem200 === 16'h0002);
152 
      @(posedge irq_ta1);
153 
      @(negedge mclk);
154 
      my_counter = 0;
155 
      @(negedge irq_ta1);
156 
      repeat(10) @(negedge mclk);
157 
      if (mem206 !== 16'h000A) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 2 =====");
158 
 
159 
      @(posedge irq_ta0);
160 
      if (my_counter !== 32'h60) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 2 =====");
161 
 
162 
      @(posedge irq_ta1);
163 
      if (my_counter !== 32'hC0) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 2 =====");
164 
      @(negedge irq_ta1);
165 
      repeat(10) @(negedge mclk);
166 
      if (mem206 !== 16'h0002) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 2 =====");
167 
 
168 
      @(posedge irq_ta1);
169 
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 2 =====");
170 
      @(negedge irq_ta1);
171 
      repeat(10) @(negedge mclk);
172 
      if (mem206 !== 16'h0004) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 2 =====");
173 
 
174 
 
175 
 
176 
      // TIMER A TEST:  UP-DOWN MODE
177 
      //--------------------------------------------------------
178 
 
179 
      @(mem200 === 16'h0001);
180 
      @(posedge irq_ta1);
181 
      @(negedge mclk);
182 
      my_counter = 0;
183 
      @(posedge ta_out2);
184 
      if (my_counter !== 32'h60)  tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 1 =====");
185 
      @(posedge ta_out1);
186 
      if (my_counter !== 32'hC0)  tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 1 =====");
187 
      @(posedge ta_out0);
188 
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 1 =====");
189 
 
190 
      @(negedge ta_out1);
191 
      if (my_counter !== 32'h180) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 2 =====");
192 
      @(negedge ta_out2);
193 
      if (my_counter !== 32'h1E0) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 2 =====");
194 
      @(negedge ta_out0);
195 
      if (my_counter !== 32'h360) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 2 =====");
196 
 
197 
 
198 
      @(mem200 === 16'h0002);
199 
      @(posedge irq_ta1);
200 
      @(negedge mclk);
201 
      my_counter = 0;
202 
      @(negedge irq_ta1);
203 
      repeat(10) @(negedge mclk);
204 
      if (mem206 !== 16'h000A)    tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 3 =====");
205 
      @(posedge irq_ta1);
206 
      if (my_counter !== 32'h60)  tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 3 =====");
207 
      @(negedge irq_ta1);
208 
      repeat(10) @(negedge mclk);
209 
      if (mem206 !== 16'h0004)    tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 3 =====");
210 
      @(posedge irq_ta1);
211 
      if (my_counter !== 32'hC0)  tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 3 =====");
212 
      @(negedge irq_ta1);
213 
      repeat(10) @(negedge mclk);
214 
      if (mem206 !== 16'h0002)    tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 3 =====");
215 
      @(posedge irq_ta0);
216 
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 3 =====");
217 
 
218 
      @(posedge irq_ta1);
219 
      if (my_counter !== 32'h180) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 4 =====");
220 
      @(negedge irq_ta1);
221 
      repeat(10) @(negedge mclk);
222 
      if (mem206 !== 16'h0002)    tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 4 =====");
223 
      @(posedge irq_ta1);
224 
      if (my_counter !== 32'h1E0) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 4 =====");
225 
      @(negedge irq_ta1);
226 
      repeat(10) @(negedge mclk);
227 
      if (mem206 !== 16'h0004)    tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 4 =====");
228 
      @(posedge irq_ta1);
229 
      if (my_counter !== 32'h240) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 4 =====");
230 
      @(negedge irq_ta1);
231 
      repeat(10) @(negedge mclk);
232 
      if (mem206 !== 16'h000A)    tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 4 =====");
233 
      @(posedge irq_ta0);
234 
      if (my_counter !== 32'h360) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 4 =====");
235 
 
236 
 
237 
      // TIMER A TEST:  CCI INPUT LATCHING (SCCI)
238 
      //--------------------------------------------------------
239 
 
240 
      @(r15 === 16'h4000);
241 
      if (mem202 !== 16'h3088) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
242 
      if (mem204 !== 16'h3489) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
243 
      if (mem206 !== 16'h2480) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
244 
      if (mem208 !== 16'h2081) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
245 
 
246 
      if (mem212 !== 16'h3088) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
247 
      if (mem214 !== 16'h3489) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
248 
      if (mem216 !== 16'h2480) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
249 
      if (mem218 !== 16'h2081) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
250 
 
251 
      if (mem222 !== 16'h3088) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
252 
      if (mem224 !== 16'h3489) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
253 
      if (mem226 !== 16'h2480) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
254 
      if (mem228 !== 16'h2081) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
255 
 
256 134 olivier.gi 
`endif
257 
 
258 2 olivier.gi 
      stimulus_done = 1;
259 
   end
260 
 

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