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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [tA_compare.v] - Blame information for rev 2

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1 2 olivier.gi 
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                                  TIMER A                                  */
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/*---------------------------------------------------------------------------*/
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/* Test the timer A:                                                         */
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/*                        - Check the timer compare features.                */
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/*===========================================================================*/
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integer my_counter;
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always @ (posedge mclk)
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  my_counter <=  my_counter+1;
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
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      // TIMER A TEST:  UP MODE
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      //--------------------------------------------------------
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      @(mem200 === 16'h0001);  // Check Comparator 0
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      @(posedge ta_out0);
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      @(negedge mclk);
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      my_counter = 0;
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      @(posedge irq_ta1);
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      if (my_counter !== 32'h2) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
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      @(negedge ta_out0);
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      @(negedge mclk);
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      my_counter = 0;
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      @(posedge irq_ta1);
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      if (my_counter !== 32'h2) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
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      @(posedge ta_out0);
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      if (my_counter !== 32'h2C) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
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      @(posedge irq_ta0);
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      @(negedge mclk);
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      my_counter = 0;
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      @(posedge irq_ta1);
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      if (my_counter !== 32'h2) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
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67 
 
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      @(mem200 === 16'h0002);  // Check Comparator 1
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      @(posedge ta_out1);
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      @(negedge mclk);
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      my_counter = 0;
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      @(posedge ta_out0);
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      if (my_counter !== 32'h20) tb_error("====== TIMER_A COMPARE 1: UP MODE =====");
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      @(negedge ta_out1);
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      @(negedge mclk);
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      my_counter = 0;
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      @(negedge ta_out0);
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      if (my_counter !== 32'h20) tb_error("====== TIMER_A COMPARE 1: UP MODE =====");
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81 
      @(posedge irq_ta1);
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      @(negedge mclk);
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      my_counter = 0;
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      @(posedge ta_out0);
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      if (my_counter !== 32'h20) tb_error("====== TIMER_A COMPARE 1: UP MODE =====");
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87 
 
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      @(mem200 === 16'h0003);  // Check Comparator 2
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      @(posedge ta_out2);
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      @(negedge mclk);
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      my_counter = 0;
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      @(posedge ta_out0);
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      if (my_counter !== 32'h12) tb_error("====== TIMER_A COMPARE 2: UP MODE =====");
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95 
      @(negedge ta_out2);
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      @(negedge mclk);
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      my_counter = 0;
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      @(negedge ta_out0);
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      if (my_counter !== 32'h12) tb_error("====== TIMER_A COMPARE 2: UP MODE =====");
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101 
      @(posedge irq_ta1);
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      @(negedge mclk);
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      my_counter = 0;
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      @(posedge ta_out0);
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      if (my_counter !== 32'h12) tb_error("====== TIMER_A COMPARE 2: UP MODE =====");
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107 
 
108 
      // TIMER A TEST:  CONTINUOUS MODE
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      //--------------------------------------------------------
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      @(mem200 === 16'h0001);
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      @(posedge irq_ta1);
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      @(negedge mclk);
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      my_counter = 0;
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      @(negedge irq_ta1);
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      repeat(10) @(negedge mclk);
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      if (mem206 !== 16'h000A) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 1 =====");
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119 
      @(posedge ta_out0);
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      if (my_counter !== 32'h60) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 1 =====");
121 
 
122 
      @(posedge ta_out1);
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      if (my_counter !== 32'hC0) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 1 =====");
124 
      @(negedge irq_ta1);
125 
      repeat(10) @(negedge mclk);
126 
      if (mem206 !== 16'h0002) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 1 =====");
127 
 
128 
      @(posedge ta_out2);
129 
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 1 =====");
130 
      @(negedge irq_ta1);
131 
      repeat(10) @(negedge mclk);
132 
      if (mem206 !== 16'h0004) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 1 =====");
133 
 
134 
 
135 
      @(mem200 === 16'h0002);
136 
      @(posedge irq_ta1);
137 
      @(negedge mclk);
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      my_counter = 0;
139 
      @(negedge irq_ta1);
140 
      repeat(10) @(negedge mclk);
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      if (mem206 !== 16'h000A) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 2 =====");
142 
 
143 
      @(posedge irq_ta0);
144 
      if (my_counter !== 32'h60) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 2 =====");
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146 
      @(posedge irq_ta1);
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      if (my_counter !== 32'hC0) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 2 =====");
148 
      @(negedge irq_ta1);
149 
      repeat(10) @(negedge mclk);
150 
      if (mem206 !== 16'h0002) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 2 =====");
151 
 
152 
      @(posedge irq_ta1);
153 
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 2 =====");
154 
      @(negedge irq_ta1);
155 
      repeat(10) @(negedge mclk);
156 
      if (mem206 !== 16'h0004) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 2 =====");
157 
 
158 
 
159 
 
160 
      // TIMER A TEST:  UP-DOWN MODE
161 
      //--------------------------------------------------------
162 
 
163 
      @(mem200 === 16'h0001);
164 
      @(posedge irq_ta1);
165 
      @(negedge mclk);
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      my_counter = 0;
167 
      @(posedge ta_out2);
168 
      if (my_counter !== 32'h60)  tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 1 =====");
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      @(posedge ta_out1);
170 
      if (my_counter !== 32'hC0)  tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 1 =====");
171 
      @(posedge ta_out0);
172 
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 1 =====");
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174 
      @(negedge ta_out1);
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      if (my_counter !== 32'h180) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 2 =====");
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      @(negedge ta_out2);
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      if (my_counter !== 32'h1E0) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 2 =====");
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      @(negedge ta_out0);
179 
      if (my_counter !== 32'h360) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 2 =====");
180 
 
181 
 
182 
      @(mem200 === 16'h0002);
183 
      @(posedge irq_ta1);
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      @(negedge mclk);
185 
      my_counter = 0;
186 
      @(negedge irq_ta1);
187 
      repeat(10) @(negedge mclk);
188 
      if (mem206 !== 16'h000A)    tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 3 =====");
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      @(posedge irq_ta1);
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      if (my_counter !== 32'h60)  tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 3 =====");
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      @(negedge irq_ta1);
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      repeat(10) @(negedge mclk);
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      if (mem206 !== 16'h0004)    tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 3 =====");
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      @(posedge irq_ta1);
195 
      if (my_counter !== 32'hC0)  tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 3 =====");
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      @(negedge irq_ta1);
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      repeat(10) @(negedge mclk);
198 
      if (mem206 !== 16'h0002)    tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 3 =====");
199 
      @(posedge irq_ta0);
200 
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 3 =====");
201 
 
202 
      @(posedge irq_ta1);
203 
      if (my_counter !== 32'h180) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 4 =====");
204 
      @(negedge irq_ta1);
205 
      repeat(10) @(negedge mclk);
206 
      if (mem206 !== 16'h0002)    tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 4 =====");
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      @(posedge irq_ta1);
208 
      if (my_counter !== 32'h1E0) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 4 =====");
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      @(negedge irq_ta1);
210 
      repeat(10) @(negedge mclk);
211 
      if (mem206 !== 16'h0004)    tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 4 =====");
212 
      @(posedge irq_ta1);
213 
      if (my_counter !== 32'h240) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 4 =====");
214 
      @(negedge irq_ta1);
215 
      repeat(10) @(negedge mclk);
216 
      if (mem206 !== 16'h000A)    tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 4 =====");
217 
      @(posedge irq_ta0);
218 
      if (my_counter !== 32'h360) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 4 =====");
219 
 
220 
 
221 
      // TIMER A TEST:  CCI INPUT LATCHING (SCCI)
222 
      //--------------------------------------------------------
223 
 
224 
      @(r15 === 16'h4000);
225 
      if (mem202 !== 16'h3088) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
226 
      if (mem204 !== 16'h3489) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
227 
      if (mem206 !== 16'h2480) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
228 
      if (mem208 !== 16'h2081) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
229 
 
230 
      if (mem212 !== 16'h3088) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
231 
      if (mem214 !== 16'h3489) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
232 
      if (mem216 !== 16'h2480) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
233 
      if (mem218 !== 16'h2081) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
234 
 
235 
      if (mem222 !== 16'h3088) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
236 
      if (mem224 !== 16'h3489) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
237 
      if (mem226 !== 16'h2480) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
238 
      if (mem228 !== 16'h2081) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
239 
 
240 
      stimulus_done = 1;
241 
   end
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