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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [tA_modes.v] - Blame information for rev 180

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Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                                  TIMER A                                  */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the timer A:                                                         */
27 
/*                        - Check RD/WR register access.                     */
28 
/*                        - Check the clock divider.                         */
29 
/*                        - Check the timer modes.                           */
30 18 olivier.gi 
/*                                                                           */
31 
/* Author(s):                                                                */
32 
/*             - Olivier Girard,    olgirard@gmail.com                       */
33 
/*                                                                           */
34 
/*---------------------------------------------------------------------------*/
35 19 olivier.gi 
/* $Rev: 180 $                                                                */
36 
/* $LastChangedBy: olivier.girard $                                          */
37 
/* $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $          */
38 2 olivier.gi 
/*===========================================================================*/
39 
 
40 111 olivier.gi 
 
41 
integer test_step;
42 2 olivier.gi 
integer my_counter;
43 
always @ (posedge mclk)
44 
  my_counter <=  my_counter+1;
45 
 
46 
initial
47 
   begin
48 
      $display(" ===============================================");
49 
      $display("|                 START SIMULATION              |");
50 
      $display(" ===============================================");
51 
      repeat(5) @(posedge mclk);
52 
      stimulus_done = 0;
53 111 olivier.gi 
      test_step     = 0;
54 
 
55 180 olivier.gi 
`ifdef ASIC_CLOCKING
56 134 olivier.gi 
      $display(" ===============================================");
57 
      $display("|               SIMULATION SKIPPED              |");
58 
      $display("|   (this test is not supported in ASIC mode)   |");
59 
      $display(" ===============================================");
60 
      $finish;
61 
`else
62 
 
63 2 olivier.gi 
      // TIMER A TEST:  RD/WR ACCESS
64 
      //--------------------------------------------------------
65 
 
66 
      @(r15===16'h1000);
67 
      if (mem200 !== 16'h02a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
68 
      if (mem202 !== 16'h0151) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
69 
      if (mem204 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
70 
      if (mem206 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
71 
 
72 
      if (mem208 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TAR     ERROR =====");
73 
      if (mem20A !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TAR     ERROR =====");
74 
      if (mem20C !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAR     ERROR =====");
75 
 
76 
      if (mem210 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
77 
      if (mem212 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
78 
      if (mem214 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
79 
 
80 
      if (mem216 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0  ERROR =====");
81 
      if (mem218 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0  ERROR =====");
82 
      if (mem21A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0  ERROR =====");
83 
 
84 
      if (mem220 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
85 
      if (mem222 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
86 
      if (mem224 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
87 
 
88 
      if (mem226 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1  ERROR =====");
89 
      if (mem228 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1  ERROR =====");
90 
      if (mem22A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1  ERROR =====");
91 
 
92 
      if (mem230 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
93 
      if (mem232 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
94 
      if (mem234 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
95 
 
96 
      if (mem236 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
97 
      if (mem238 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
98 
      if (mem23A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
99 
 
100 
      if (mem240 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
101 
      if (mem242 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
102 
      if (mem244 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
103 111 olivier.gi 
      test_step = 1;
104 2 olivier.gi 
 
105 
      // TIMER A TEST:  INPUT DIVIDER
106 
      //--------------------------------------------------------
107 
 
108 
      @(mem200 === 16'h0001);  // Check /1 divider
109 
      @(posedge irq_ta1)
110 
      @(negedge mclk)
111 
        my_counter = 0;
112 
      @(posedge irq_ta1)
113 
        if (my_counter !== 32'h21) tb_error("====== TIMER_A INPUT DIVIDER: /1 ERROR =====");
114 111 olivier.gi 
      test_step = 2;
115 2 olivier.gi 
 
116 
      @(mem200 === 16'h0002);  // Check /2 divider
117 
      @(posedge irq_ta1)
118 
      @(negedge mclk)
119 
        my_counter = 0;
120 
      @(posedge irq_ta1)
121 
        if (my_counter !== 32'h22) tb_error("====== TIMER_A INPUT DIVIDER: /2 ERROR =====");
122 111 olivier.gi 
      test_step = 3;
123 2 olivier.gi 
 
124 
      @(mem200 === 16'h0003);  // Check /4 divider
125 
      @(posedge irq_ta1)
126 
      @(negedge mclk)
127 
        my_counter = 0;
128 
      @(posedge irq_ta1)
129 
        if (my_counter !== 32'h24) tb_error("====== TIMER_A INPUT DIVIDER: /4 ERROR =====");
130 111 olivier.gi 
      test_step = 4;
131 2 olivier.gi 
 
132 
      @(mem200 === 16'h0004);  // Check /8 divider
133 
      @(posedge irq_ta1)
134 
      @(negedge mclk)
135 
        my_counter = 0;
136 
      @(posedge irq_ta1)
137 
        if (my_counter !== 32'h28) tb_error("====== TIMER_A INPUT DIVIDER: /8 ERROR =====");
138 111 olivier.gi 
      test_step = 5;
139 2 olivier.gi 
 
140 
      @(r15===16'h2000);
141 111 olivier.gi 
      test_step = 6;
142 2 olivier.gi 
 
143 
 
144 
      // TIMER A TEST:  UP MODE
145 
      //--------------------------------------------------------
146 
 
147 
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
148 
      @(posedge irq_ta1)
149 
      @(negedge mclk)
150 
        my_counter = 0;
151 
      @(posedge irq_ta1)
152 
        if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TAIFG interrupt =====");
153 111 olivier.gi 
      test_step = 7;
154 2 olivier.gi 
 
155 
      @(mem200 === 16'h0002);  // Check timing 2 - TAIFG interrupt
156 
      @(posedge irq_ta1)
157 
      @(negedge mclk)
158 
        my_counter = 0;
159 
      @(posedge irq_ta1)
160 
        if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TAIFG interrupt =====");
161 111 olivier.gi 
      test_step = 8;
162 
 
163 2 olivier.gi 
      @(mem200 === 16'h0003);  // Check timing 1 - TACCR0 interrupt
164 
      @(posedge irq_ta0)
165 
      @(negedge mclk)
166 
        my_counter = 0;
167 
      @(posedge irq_ta0)
168 
        if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TACCR0 interrupt =====");
169 111 olivier.gi 
      test_step = 8;
170 2 olivier.gi 
 
171 
      @(mem200 === 16'h0004);  // Check timing 2 - TACCR0 interrupt
172 
      @(posedge irq_ta0)
173 
      @(negedge mclk)
174 
        my_counter = 0;
175 
      @(posedge irq_ta0)
176 
        if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TACCR0 interrupt =====");
177 111 olivier.gi 
      test_step = 9;
178 2 olivier.gi 
 
179 
      @(r15===16'h3000);
180 
      if (mem202 !== 16'h0004) tb_error("====== TIMER_A UP MODE: TAIFG LATENCY ERROR =====");
181 
      if (mem204 !== 16'h0003) tb_error("====== TIMER_A UP MODE: TACCR0 LATENCY ERROR =====");
182 111 olivier.gi 
      test_step = 10;
183 2 olivier.gi 
 
184 
 
185 
      // TIMER A TEST:  CONTINUOUS MODE
186 
      //--------------------------------------------------------
187 
 
188 
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
189 
      @(negedge mclk)
190 
      my_counter = 0;
191 
      @(posedge irq_ta1)
192 
        if (my_counter !== 32'h1C) tb_error("====== TIMER_A CONTINUOUS MODE: TIMING 1 - TAIFG interrupt =====");
193 111 olivier.gi 
      test_step = 11;
194 2 olivier.gi 
 
195 
 
196 
      // TIMER A TEST:  UP-DOWN MODE
197 
      //--------------------------------------------------------
198 
 
199 
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
200 
      @(posedge irq_ta0)
201 
      @(negedge mclk)
202 
      my_counter = 0;
203 
      @(posedge irq_ta0)
204 
        if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG interrupt =====");
205 111 olivier.gi 
      test_step = 12;
206 2 olivier.gi 
 
207 
      @(posedge irq_ta1)       // Check timing 1 - TACCR0 interrupt
208 
      @(negedge mclk)
209 
      my_counter = 0;
210 
      @(posedge irq_ta1)
211 
        if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TACCR0 interrupt =====");
212 111 olivier.gi 
      test_step = 13;
213 2 olivier.gi 
 
214 
      @(posedge irq_ta0)       // Check timing 1 - TAIFG->TACCR0 interrupt
215 
      @(negedge mclk)
216 
      my_counter = 0;
217 
      @(posedge irq_ta1)
218 
        if (my_counter !== 32'h31) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG->TACCR0 interrupt =====");
219 111 olivier.gi 
      test_step = 14;
220 2 olivier.gi 
 
221 
      @(mem200===16'h0002);
222 
      if (mem202 !== 16'h0008) tb_error("====== TIMER_A UP-DOWN MODE: TAIFG LATENCY ERROR =====");
223 
      if (mem204 !== 16'h0028) tb_error("====== TIMER_A UP-DOWN MODE: TACCR0 LATENCY ERROR =====");
224 111 olivier.gi 
      test_step = 15;
225 2 olivier.gi 
 
226 134 olivier.gi 
`endif
227 2 olivier.gi 
 
228 
      stimulus_done = 1;
229 
   end
230 
 

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