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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                 TWO-OPERAND ARITHMETIC: ADDC[.B] INSTRUCTION              */
/*---------------------------------------------------------------------------*/
/* Test the ADDC[.B] instruction.                                            */
/*===========================================================================*/
 
 
.global main
 
main:
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
 
        # Test standard ADD without Carry bit set
        mov     #0x0000, r2
        mov     #0x4444, r4
        mov     #0x5555, r5
        add          r4, r5        ;# Add r4+r5 (0x4444+0x5555=0x9999)
 
        # Test standard ADD withCarry bit set
        mov     #0x0001, r2
        mov     #0x6666, r4
        mov     #0x7777, r6
        add          r4, r6        ;# Add r4+r6 (0x6666+0x7777=0xdddd)
 
 
        # Test standard ADDC without Carry bit set
        mov     #0x0000, r2
        mov     #0x8888, r4
        mov     #0x9999, r7
        addc         r4, r7        ;# Add r4+r7+c (0x8888+0x9999=0x2221)
 
        # Test standard ADDC with Carry bit set
        mov     #0x0001, r2
        mov     #0xaaaa, r4
        mov     #0xbbbb, r8
        addc         r4, r8        ;# Add r4+r8+C (0xaaaa+0xbbbb=0x6666)
 
 
        mov     #0x1000, r15
 
 
        /* -------------- TEST INSTRUCTION IN BYTE MODE ------------------- */
 
        # Test standard ADD with and without Carry bit set
        mov     #0x0000, r2
        mov     #0x4444, r4
        mov     #0x5555, r5
        add.b        r4, r5        ;# Add r4+r5 (0x0044+0x0055=0x0099)
 
        # Test standard ADD with and with Carry bit set
        mov     #0x0001, r2
        mov     #0x6666, r4
        mov     #0x6677, r6
        add.b        r4, r6        ;# Add r4+r6 (0x0066+0x0077=0x00dd)
 
 
        # Test standard ADDC with and without Carry bit set
        mov     #0x0000, r2
        mov     #0x8888, r4
        mov     #0x9999, r7
        addc.b       r4, r7        ;# Add r4+r5+c (0x0088+0x0099=0x0021)
 
        # Test standard ADDC with and with Carry bit set
        mov     #0x0001, r2
        mov     #0xaaaa, r4
        mov     #0xbbbb, r8
        addc.b       r4, r8        ;# Add r4+r6+C (0x00aa+0x00bb=0x0066)
 
 
        mov     #0x2000, r15
 
 
        /* ------------------ TEST FLAGS IN WORD MODE ---------------------- */
 
        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=0
        mov     #0x0444, r4        ;#
        mov     #0x0555, r5        ;#
        addc         r4, r5        ;# Add r4+r5 (0x0444+0x0555=0x0999)
        mov     #0x3000, r15
 
        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=1
        mov     #0x0011, r4        ;#
        mov     #0xfff0, r5        ;#
        addc         r4, r5        ;# Add r4+r5 (0xfff0+0x0011=0x0001)
        mov     #0x3001, r15
 
        mov     #0x0000, r2        ;# V=0, N=0, Z=1, C=0
        mov     #0x0000, r4        ;#
        mov     #0x0000, r5        ;#
        addc         r4, r5        ;# Add r4+r5 (0x0000+0x0000=0x0000)
        mov     #0x3002, r15
 
        mov     #0x0000, r2        ;# V=0, N=1, Z=0, C=0
        mov     #0xff00, r4        ;#
        mov     #0x0010, r5        ;#
        addc         r4, r5        ;# Add r4+r5 (0xff00+0x0010=0xff10)
        mov     #0x3003, r15
 
        mov     #0x0000, r2        ;# V=1, N=1, Z=0, C=0
        mov     #0x7fff, r4        ;#
        mov     #0x0010, r5        ;#
        addc         r4, r5        ;# Add r4+r5 (0x7fff+0x0010=0x800f)
        mov     #0x3004, r15
 
        mov     #0x0000, r2        ;# V=1, N=0, Z=0, C=1
        mov     #0xff00, r4        ;#
        mov     #0x8000, r5        ;#
        addc         r4, r5        ;# Add r4+r5 (0xff00+0x8000=0x7f00)
        mov     #0x3005, r15
 
 
        /* ------------------ TEST FLAGS IN BYTE MODE --------------------- */
 
        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=0
        mov     #0xaa04, r4        ;#
        mov     #0x6605, r5        ;#
        addc.b       r4, r5        ;# Add r4+r5 (0xaa04+0x6605=0x0009)
        mov     #0x4000, r15
 
        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=1
        mov     #0xaa11, r4        ;#
        mov     #0x66f0, r5        ;#
        addc.b       r4, r5        ;# Add r4+r5 (0x0011+0x00f0=0x0001)
        mov     #0x4001, r15
 
        mov     #0x0000, r2        ;# V=0, N=0, Z=1, C=0
        mov     #0xaa00, r4        ;#
        mov     #0x6600, r5        ;#
        addc.b       r4, r5        ;# Add r4+r5 (0x0000+0x0000=0x0000)
        mov     #0x4002, r15
 
        mov     #0x0000, r2        ;# V=0, N=1, Z=0, C=0
        mov     #0xaaf0, r4        ;#
        mov     #0x6603, r5        ;#
        addc.b       r4, r5        ;# Add r4+r5 (0x00f0+0x0003=0x00f3)
        mov     #0x4003, r15
 
        mov     #0x0000, r2        ;# V=1, N=1, Z=0, C=0
        mov     #0x007f, r4        ;#
        mov     #0x0010, r5        ;#
        addc.b       r4, r5        ;# Add r4+r5 (0x007f+0x0010=0x008f)
        mov     #0x4004, r15
 
        mov     #0x0000, r2        ;# V=1, N=0, Z=0, C=1
        mov     #0x00ff, r4        ;#
        mov     #0x0080, r5        ;#
        addc.b       r4, r5        ;# Add r4+r5 (0x00ff+0x0080=0x007f)
        mov     #0x4005, r15
 
 
        /* ----------------------         END OF TEST        --------------- */
        mov     #0x5000, r15
end_of_test:
        nop
        br #0xffff
 
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* TWO-OPERAND ARITHMETIC: ADDC[.B] INSTRUCTION */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the ADDC[.B] instruction. */`
27			`/===========================================================================/`
28
29
30			`.global main`
31
32			`main:`
33			`/* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */`
34
35			`# Test standard ADD without Carry bit set`
36			`mov #0x0000, r2`
37			`mov #0x4444, r4`
38			`mov #0x5555, r5`
39			`add r4, r5 ;# Add r4+r5 (0x4444+0x5555=0x9999)`
40
41			`# Test standard ADD withCarry bit set`
42			`mov #0x0001, r2`
43			`mov #0x6666, r4`
44			`mov #0x7777, r6`
45			`add r4, r6 ;# Add r4+r6 (0x6666+0x7777=0xdddd)`
46
47
48			`# Test standard ADDC without Carry bit set`
49			`mov #0x0000, r2`
50			`mov #0x8888, r4`
51			`mov #0x9999, r7`
52			`addc r4, r7 ;# Add r4+r7+c (0x8888+0x9999=0x2221)`
53
54			`# Test standard ADDC with Carry bit set`
55			`mov #0x0001, r2`
56			`mov #0xaaaa, r4`
57			`mov #0xbbbb, r8`
58			`addc r4, r8 ;# Add r4+r8+C (0xaaaa+0xbbbb=0x6666)`
59
60
61			`mov #0x1000, r15`
62
63
64			`/* -------------- TEST INSTRUCTION IN BYTE MODE ------------------- */`
65
66			`# Test standard ADD with and without Carry bit set`
67			`mov #0x0000, r2`
68			`mov #0x4444, r4`
69			`mov #0x5555, r5`
70			`add.b r4, r5 ;# Add r4+r5 (0x0044+0x0055=0x0099)`
71
72			`# Test standard ADD with and with Carry bit set`
73			`mov #0x0001, r2`
74			`mov #0x6666, r4`
75			`mov #0x6677, r6`
76			`add.b r4, r6 ;# Add r4+r6 (0x0066+0x0077=0x00dd)`
77
78
79			`# Test standard ADDC with and without Carry bit set`
80			`mov #0x0000, r2`
81			`mov #0x8888, r4`
82			`mov #0x9999, r7`
83			`addc.b r4, r7 ;# Add r4+r5+c (0x0088+0x0099=0x0021)`
84
85			`# Test standard ADDC with and with Carry bit set`
86			`mov #0x0001, r2`
87			`mov #0xaaaa, r4`
88			`mov #0xbbbb, r8`
89			`addc.b r4, r8 ;# Add r4+r6+C (0x00aa+0x00bb=0x0066)`
90
91
92			`mov #0x2000, r15`
93
94
95			`/* ------------------ TEST FLAGS IN WORD MODE ---------------------- */`
96
97			`mov #0x0000, r2 ;# V=0, N=0, Z=0, C=0`
98			`mov #0x0444, r4 ;#`
99			`mov #0x0555, r5 ;#`
100			`addc r4, r5 ;# Add r4+r5 (0x0444+0x0555=0x0999)`
101			`mov #0x3000, r15`
102
103			`mov #0x0000, r2 ;# V=0, N=0, Z=0, C=1`
104			`mov #0x0011, r4 ;#`
105			`mov #0xfff0, r5 ;#`
106			`addc r4, r5 ;# Add r4+r5 (0xfff0+0x0011=0x0001)`
107			`mov #0x3001, r15`
108
109			`mov #0x0000, r2 ;# V=0, N=0, Z=1, C=0`
110			`mov #0x0000, r4 ;#`
111			`mov #0x0000, r5 ;#`
112			`addc r4, r5 ;# Add r4+r5 (0x0000+0x0000=0x0000)`
113			`mov #0x3002, r15`
114
115			`mov #0x0000, r2 ;# V=0, N=1, Z=0, C=0`
116			`mov #0xff00, r4 ;#`
117			`mov #0x0010, r5 ;#`
118			`addc r4, r5 ;# Add r4+r5 (0xff00+0x0010=0xff10)`
119			`mov #0x3003, r15`
120
121			`mov #0x0000, r2 ;# V=1, N=1, Z=0, C=0`
122			`mov #0x7fff, r4 ;#`
123			`mov #0x0010, r5 ;#`
124			`addc r4, r5 ;# Add r4+r5 (0x7fff+0x0010=0x800f)`
125			`mov #0x3004, r15`
126
127			`mov #0x0000, r2 ;# V=1, N=0, Z=0, C=1`
128			`mov #0xff00, r4 ;#`
129			`mov #0x8000, r5 ;#`
130			`addc r4, r5 ;# Add r4+r5 (0xff00+0x8000=0x7f00)`
131			`mov #0x3005, r15`
132
133
134			`/* ------------------ TEST FLAGS IN BYTE MODE --------------------- */`
135
136			`mov #0x0000, r2 ;# V=0, N=0, Z=0, C=0`
137			`mov #0xaa04, r4 ;#`
138			`mov #0x6605, r5 ;#`
139			`addc.b r4, r5 ;# Add r4+r5 (0xaa04+0x6605=0x0009)`
140			`mov #0x4000, r15`
141
142			`mov #0x0000, r2 ;# V=0, N=0, Z=0, C=1`
143			`mov #0xaa11, r4 ;#`
144			`mov #0x66f0, r5 ;#`
145			`addc.b r4, r5 ;# Add r4+r5 (0x0011+0x00f0=0x0001)`
146			`mov #0x4001, r15`
147
148			`mov #0x0000, r2 ;# V=0, N=0, Z=1, C=0`
149			`mov #0xaa00, r4 ;#`
150			`mov #0x6600, r5 ;#`
151			`addc.b r4, r5 ;# Add r4+r5 (0x0000+0x0000=0x0000)`
152			`mov #0x4002, r15`
153
154			`mov #0x0000, r2 ;# V=0, N=1, Z=0, C=0`
155			`mov #0xaaf0, r4 ;#`
156			`mov #0x6603, r5 ;#`
157			`addc.b r4, r5 ;# Add r4+r5 (0x00f0+0x0003=0x00f3)`
158			`mov #0x4003, r15`
159
160			`mov #0x0000, r2 ;# V=1, N=1, Z=0, C=0`
161			`mov #0x007f, r4 ;#`
162			`mov #0x0010, r5 ;#`
163			`addc.b r4, r5 ;# Add r4+r5 (0x007f+0x0010=0x008f)`
164			`mov #0x4004, r15`
165
166			`mov #0x0000, r2 ;# V=1, N=0, Z=0, C=1`
167			`mov #0x00ff, r4 ;#`
168			`mov #0x0080, r5 ;#`
169			`addc.b r4, r5 ;# Add r4+r5 (0x00ff+0x0080=0x007f)`
170			`mov #0x4005, r15`
171
172
173			`/* ---------------------- END OF TEST --------------- */`
174			`mov #0x5000, r15`
175			`end_of_test:`
176			`nop`
177			`br #0xffff`
178
179
180
181			`/* ---------------------- INTERRUPT VECTORS --------------- */`
182
183			`.section .vectors, "a"`
184			`.word end_of_test ; Interrupt 0 (lowest priority)`
185			`.word end_of_test ; Interrupt 1`
186			`.word end_of_test ; Interrupt 2`
187			`.word end_of_test ; Interrupt 3`
188			`.word end_of_test ; Interrupt 4`
189			`.word end_of_test ; Interrupt 5`
190			`.word end_of_test ; Interrupt 6`
191			`.word end_of_test ; Interrupt 7`
192			`.word end_of_test ; Interrupt 8`
193			`.word end_of_test ; Interrupt 9`
194			`.word end_of_test ; Interrupt 10 Watchdog timer`
195			`.word end_of_test ; Interrupt 11`
196			`.word end_of_test ; Interrupt 12`
197			`.word end_of_test ; Interrupt 13`
198			`.word end_of_test ; Interrupt 14 NMI`
199			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_addc.s43] - Blame information for rev 2