OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_addc.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                 TWO-OPERAND ARITHMETIC: ADDC[.B] INSTRUCTION              */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the ADDC[.B] instruction.                                            */
27 
/*===========================================================================*/
28 
 
29 
initial
30 
   begin
31 
      $display(" ===============================================");
32 
      $display("|                 START SIMULATION              |");
33 
      $display(" ===============================================");
34 
      repeat(5) @(posedge mclk);
35 
      stimulus_done = 0;
36 
 
37 
      // ADDC (WORD MODE)
38 
      //--------------------------------------------------------
39 
      @(r15==16'h1000);
40 
 
41 
      if (r5    !==16'h9999) tb_error("====== ADD without Carry =====");
42 
      if (r6    !==16'hdddd) tb_error("====== ADD with Carry =====");
43 
      if (r7    !==16'h2221) tb_error("====== ADDC without Carry =====");
44 
      if (r8    !==16'h6666) tb_error("====== ADDC with Carry =====");
45 
 
46 
 
47 
      // ADDC.B (BYTE MODE)
48 
      //--------------------------------------------------------
49 
      @(r15==16'h2000);
50 
 
51 
      if (r5    !==16'h0099) tb_error("====== ADD.B  without Carry =====");
52 
      if (r6    !==16'h00dd) tb_error("====== ADD.B  with Carry =====");
53 
      if (r7    !==16'h0021) tb_error("====== ADDC.B without Carry =====");
54 
      if (r8    !==16'h0066) tb_error("====== ADDC.B with Carry =====");
55 
 
56 
 
57 
      // ADDC (WORD MODE): Check Flags
58 
      //--------------------------------------------------------
59 
 
60 
      @(r15==16'h3000);
61 
      if (r2    !==16'h0000) tb_error("====== ADDC FLAG: Flag   check error: V=0, N=0, Z=0, C=0 =====");
62 
      if (r5    !==16'h0999) tb_error("====== ADDC FLAG: Result check error: V=0, N=0, Z=0, C=0 =====");
63 
 
64 
      @(r15==16'h3001);
65 
      if (r2    !==16'h0001) tb_error("====== ADDC FLAG: Flag   check error: V=0, N=0, Z=0, C=1 =====");
66 
      if (r5    !==16'h0001) tb_error("====== ADDC FLAG: Result check error: V=0, N=0, Z=0, C=1 =====");
67 
 
68 
      @(r15==16'h3002);
69 
      if (r2    !==16'h0002) tb_error("====== ADDC FLAG: Flag   check error: V=0, N=0, Z=1, C=0 =====");
70 
      if (r5    !==16'h0000) tb_error("====== ADDC FLAG: Result check error: V=0, N=0, Z=1, C=0 =====");
71 
 
72 
      @(r15==16'h3003);
73 
      if (r2    !==16'h0004) tb_error("====== ADDC FLAG: Flag   check error: V=0, N=1, Z=0, C=0 =====");
74 
      if (r5    !==16'hff10) tb_error("====== ADDC FLAG: Result check error: V=0, N=1, Z=0, C=0 =====");
75 
 
76 
      @(r15==16'h3004);
77 
      if (r2    !==16'h0104) tb_error("====== ADDC FLAG: Flag   check error: V=1, N=1, Z=0, C=0 =====");
78 
      if (r5    !==16'h800f) tb_error("====== ADDC FLAG: Result check error: V=1, N=1, Z=0, C=0 =====");
79 
 
80 
      @(r15==16'h3005);
81 
      if (r2    !==16'h0101) tb_error("====== ADDC FLAG: Flag   check error: V=1, N=0, Z=0, C=1 =====");
82 
      if (r5    !==16'h7f00) tb_error("====== ADDC FLAG: Result check error: V=1, N=0, Z=0, C=1 =====");
83 
 
84 
 
85 
      // ADDC.B (BYTE MODE): Check Flags
86 
      //--------------------------------------------------------
87 
 
88 
      @(r15==16'h4000);
89 
      if (r2    !==16'h0000) tb_error("====== ADDC.B FLAG: Flag   check error: V=0, N=0, Z=0, C=0 =====");
90 
      if (r5    !==16'h0009) tb_error("====== ADDC.B FLAG: Result check error: V=0, N=0, Z=0, C=0 =====");
91 
 
92 
      @(r15==16'h4001);
93 
      if (r2    !==16'h0001) tb_error("====== ADDC.B FLAG: Flag   check error: V=0, N=0, Z=0, C=1 =====");
94 
      if (r5    !==16'h0001) tb_error("====== ADDC.B FLAG: Result check error: V=0, N=0, Z=0, C=1 =====");
95 
 
96 
      @(r15==16'h4002);
97 
      if (r2    !==16'h0002) tb_error("====== ADDC.B FLAG: Flag   check error: V=0, N=0, Z=1, C=0 =====");
98 
      if (r5    !==16'h0000) tb_error("====== ADDC.B FLAG: Result check error: V=0, N=0, Z=1, C=0 =====");
99 
 
100 
      @(r15==16'h4003);
101 
      if (r2    !==16'h0004) tb_error("====== ADDC.B FLAG: Flag   check error: V=0, N=1, Z=0, C=0 =====");
102 
      if (r5    !==16'h00f3) tb_error("====== ADDC.B FLAG: Result check error: V=0, N=1, Z=0, C=0 =====");
103 
 
104 
      @(r15==16'h4004);
105 
      if (r2    !==16'h0104) tb_error("====== ADDC.B FLAG: Flag   check error: V=1, N=1, Z=0, C=0 =====");
106 
      if (r5    !==16'h008f) tb_error("====== ADDC.B FLAG: Result check error: V=1, N=1, Z=0, C=0 =====");
107 
 
108 
      @(r15==16'h4005);
109 
      if (r2    !==16'h0101) tb_error("====== ADDC.B FLAG: Flag   check error: V=1, N=0, Z=0, C=1 =====");
110 
      if (r5    !==16'h007f) tb_error("====== ADDC.B FLAG: Result check error: V=1, N=0, Z=0, C=1 =====");
111 
 
112 
 
113 
      stimulus_done = 1;
114 
   end
115 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.