OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_bic.s43] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                 TWO-OPERAND ARITHMETIC: BIC[.B] INSTRUCTION               */
25
/*---------------------------------------------------------------------------*/
26
/* Test the BIC[.B] instruction.                                             */
27
/*===========================================================================*/
28
 
29
 
30
.global main
31
 
32
main:
33
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
34
 
35
        mov     #0x0000, r2
36
        mov     #0xaaaa, r4
37
        mov     #0xffff, r5
38
        bic          r4, r5        ;# Clear bits ~r4 & r5 (~0xaaaa & 0xffff=0x5555)
39
 
40
        mov     #0x0001, r2
41
        mov     #0x5555, r4
42
        mov     #0xffff, r6
43
        bic          r4, r6        ;# Clear bits ~r4 & r6 (~0x5555 & 0xffff=0xaaaa)
44
 
45
 
46
        mov     #0x1000, r15
47
 
48
 
49
        /* -------------- TEST INSTRUCTION IN BYTE MODE ------------------- */
50
 
51
        mov     #0x0000, r2
52
        mov     #0x3333, r4
53
        mov     #0x9999, r5
54
        bic.b        r4, r5        ;# Clear bits ~r4 & r5 (~0x3333 & 0x9999=0x0088)
55
 
56
        mov     #0x0001, r2
57
        mov     #0x5555, r4
58
        mov     #0x6666, r6
59
        bic.b        r4, r6        ;# Clear bits ~r4 & r6 (~0x5555 & 0xcccc=0x0022)
60
 
61
 
62
        mov     #0x2000, r15
63
 
64
 
65
        /* ------------------ TEST FLAGS IN WORD MODE ---------------------- */
66
        #
67
        # Make sure Flags are unaffected by instruction
68
        #
69
 
70
        mov     #0x0005, r2        ;# V=0, N=1, Z=0, C=1
71
        mov     #0x0aaa, r4        ;#
72
        mov     #0x0666, r5        ;#
73
        bic          r4, r5        ;# Clear bits ~r4 & r5 (~0x0aaa & 0x0666=0x0444)
74
        mov     #0x3000, r15
75
 
76
        mov     #0x0102, r2        ;# V=1, N=0, Z=1, C=0
77
        mov     #0x0aaa, r4        ;#
78
        mov     #0x0666, r5        ;#
79
        bic          r4, r5        ;# Clear bits ~r4 & r5 (~0x0aaa & 0x0666=0x0444)
80
        mov     #0x3001, r15
81
 
82
 
83
        /* ------------------ TEST FLAGS IN BYTE MODE --------------------- */
84
        #
85
        # Make sure Flags are unaffected by instruction
86
        #
87
 
88
        mov     #0x0005, r2        ;# V=0, N=1, Z=0, C=1
89
        mov     #0x550a, r4        ;#
90
        mov     #0x6606, r5        ;#
91
        bic.b        r4, r5        ;# Clear bits ~r4 & r5 (~0x000a & 0x0006=0x0004)
92
        mov     #0x4000, r15
93
 
94
        mov     #0x0102, r2        ;# V=1, N=0, Z=1, C=0
95
        mov     #0x330a, r4        ;#
96
        mov     #0x9906, r5        ;#
97
        bic.b        r4, r5        ;# Clear bits ~r4 & r5 (~0x000a & 0x0006=0x0004)
98
        mov     #0x4001, r15
99
 
100
 
101
 
102
        /* ----------------------         END OF TEST        --------------- */
103
        mov      #0x5000, r15
104
end_of_test:
105
        nop
106
        br #0xffff
107
 
108
 
109
 
110
        /* ----------------------         INTERRUPT VECTORS  --------------- */
111
 
112
.section .vectors, "a"
113
.word end_of_test  ; Interrupt  0 (lowest priority)    
114
.word end_of_test  ; Interrupt  1                      
115
.word end_of_test  ; Interrupt  2                      
116
.word end_of_test  ; Interrupt  3                      
117
.word end_of_test  ; Interrupt  4                      
118
.word end_of_test  ; Interrupt  5                      
119
.word end_of_test  ; Interrupt  6                      
120
.word end_of_test  ; Interrupt  7                      
121
.word end_of_test  ; Interrupt  8                      
122
.word end_of_test  ; Interrupt  9                      
123
.word end_of_test  ; Interrupt 10                      Watchdog timer
124
.word end_of_test  ; Interrupt 11                      
125
.word end_of_test  ; Interrupt 12                      
126
.word end_of_test  ; Interrupt 13                      
127
.word end_of_test  ; Interrupt 14                      NMI
128
.word main         ; Interrupt 15 (highest priority)   RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.