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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_bis.s43] - Blame information for rev 2

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1 2 olivier.gi 
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                 TWO-OPERAND ARITHMETIC: BIS[.B] INSTRUCTION               */
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/*---------------------------------------------------------------------------*/
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/* Test the BIS[.B] instruction.                                             */
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/*===========================================================================*/
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.global main
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main:
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        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
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        mov     #0x0000, r2
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        mov     #0xaaaa, r4
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        mov     #0x3333, r5
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        bis          r4, r5        ;# Set bits r4 | r5 (0xaaaa | 0x3333=0xbbbb)
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        mov     #0x0001, r2
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        mov     #0x5555, r4
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        mov     #0xcccc, r6
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        bis          r4, r6        ;# Set bits r4 | r6 (0x5555 | 0xcccc=0xdddd)
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        mov     #0x1000, r15
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        /* -------------- TEST INSTRUCTION IN BYTE MODE ------------------- */
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        mov     #0x0000, r2
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        mov     #0x4444, r4
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        mov     #0x1111, r5
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        bis.b        r4, r5        ;# Set bits r4 | r5 (0x4444 | 0x1111=0x0055)
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        mov     #0x0001, r2
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        mov     #0x8888, r4
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        mov     #0x2222, r6
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        bis.b        r4, r6        ;# Set bits r4 | r6 (0x8888 | 0x2222=0x00aa)
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        mov     #0x2000, r15
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        /* ------------------ TEST FLAGS IN WORD MODE ---------------------- */
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        #
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        # Make sure Flags are unaffected by instruction
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        #
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        mov     #0x0005, r2        ;# V=0, N=1, Z=0, C=1
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        mov     #0x0aaa, r4        ;#
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        mov     #0x0666, r5        ;#
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        bis          r4, r5        ;# Set bits r4 | r5 (0x0aaa | 0x0666=0x0eee)
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        mov     #0x3000, r15
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        mov     #0x0102, r2        ;# V=1, N=0, Z=1, C=0
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        mov     #0x0aaa, r4        ;#
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        mov     #0x0666, r5        ;#
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        bis          r4, r5        ;# Set bits r4 | r5 (0x0aaa | 0x0666=0x0eee)
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        mov     #0x3001, r15
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        /* ------------------ TEST FLAGS IN BYTE MODE --------------------- */
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        #
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        # Make sure Flags are unaffected by instruction
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        #
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        mov     #0x0005, r2        ;# V=0, N=1, Z=0, C=1
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        mov     #0x550a, r4        ;#
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        mov     #0x6606, r5        ;#
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        bis.b        r4, r5        ;# Set bits r4 | r5 (0x000a | 0x0006=0x000e)
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        mov     #0x4000, r15
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        mov     #0x0102, r2        ;# V=1, N=0, Z=1, C=0
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        mov     #0x330a, r4        ;#
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        mov     #0x9906, r5        ;#
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        bis.b        r4, r5        ;# Set bits r4 | r5 (0x000a | 0x0006=0x000e)
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        mov     #0x4001, r15
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        /* ----------------------         END OF TEST        --------------- */
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        mov      #0x5000, r15
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end_of_test:
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        nop
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        br #0xffff
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        /* ----------------------         INTERRUPT VECTORS  --------------- */
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.section .vectors, "a"
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.word end_of_test  ; Interrupt  0 (lowest priority)
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.word end_of_test  ; Interrupt  1
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.word end_of_test  ; Interrupt  2
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.word end_of_test  ; Interrupt  3
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.word end_of_test  ; Interrupt  4
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.word end_of_test  ; Interrupt  5
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.word end_of_test  ; Interrupt  6
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.word end_of_test  ; Interrupt  7
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.word end_of_test  ; Interrupt  8
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.word end_of_test  ; Interrupt  9
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.word end_of_test  ; Interrupt 10                      Watchdog timer
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.word end_of_test  ; Interrupt 11
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.word end_of_test  ; Interrupt 12
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.word end_of_test  ; Interrupt 13
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.word end_of_test  ; Interrupt 14                      NMI
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.word main         ; Interrupt 15 (highest priority)   RESET

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