OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_bis.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                 TWO-OPERAND ARITHMETIC: BIS[.B] INSTRUCTION               */
25
/*---------------------------------------------------------------------------*/
26
/* Test the BIS[.B] instruction.                                             */
27
/*===========================================================================*/
28
 
29
initial
30
   begin
31
      $display(" ===============================================");
32
      $display("|                 START SIMULATION              |");
33
      $display(" ===============================================");
34
      repeat(5) @(posedge mclk);
35
      stimulus_done = 0;
36
 
37
 
38
      // BIS (WORD MODE)
39
      //--------------------------------------------------------
40
      @(r15==16'h1000);
41
 
42
      if (r5    !==16'hbbbb) tb_error("====== BIS Test =====");
43
      if (r6    !==16'hdddd) tb_error("====== BIS Test =====");
44
 
45
 
46
      // BIS.B (BYTE MODE)
47
      //--------------------------------------------------------
48
      @(r15==16'h2000);
49
 
50
      if (r5    !==16'h0055) tb_error("====== BIS.B Test =====");
51
      if (r6    !==16'h00aa) tb_error("====== BIS.B Test =====");
52
 
53
 
54
      // BIS (WORD MODE): Check Flags
55
      //--------------------------------------------------------
56
 
57
      @(r15==16'h3000);
58
      if (r2    !==16'h0005) tb_error("====== BIS FLAG: Flag   check error =====");
59
      if (r5    !==16'h0eee) tb_error("====== BIS FLAG: Result check error =====");
60
 
61
      @(r15==16'h3001);
62
      if (r2    !==16'h0102) tb_error("====== BIS FLAG: Flag   check error =====");
63
      if (r5    !==16'h0eee) tb_error("====== BIS FLAG: Result check error =====");
64
 
65
 
66
      // BIS.B (BYTE MODE): Check Flags
67
      //--------------------------------------------------------
68
 
69
      @(r15==16'h4000);
70
      if (r2    !==16'h0005) tb_error("====== BIS.B FLAG: Flag   check error =====");
71
      if (r5    !==16'h000e) tb_error("====== BIS.B FLAG: Result check error =====");
72
 
73
      @(r15==16'h4001);
74
      if (r2    !==16'h0102) tb_error("====== BIS.B FLAG: Flag   check error =====");
75
      if (r5    !==16'h000e) tb_error("====== BIS.B FLAG: Result check error =====");
76
 
77
 
78
      stimulus_done = 1;
79
   end
80
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.