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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_clkmux.s43] - Blame information for rev 2

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1 2 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                            WATCHDOG TIMER                                 */
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/*---------------------------------------------------------------------------*/
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/* Test the Watdog timer:                                                    */
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/*                        - Clock source selection.                          */
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/*===========================================================================*/
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.global main
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.set   BCSCTL1, 0x0057
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.set   BCSCTL2, 0x0058
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.set   IE1,    0x0000
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.set   IFG1,   0x0002
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.set   WDTCTL, 0x0120
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WAIT_FUNC:
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        dec r14
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        jnz WAIT_FUNC
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        ret
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main:
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        /* -------   WATCHDOG TEST INTERVAL MODE /64 - SMCLK /2      ------ */
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        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
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        eint
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        bis.b   #0x01,   &IE1
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        mov.b   #0x02, &BCSCTL2	  ;# SMCLK = MCLK/2
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        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
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        mov   #0x0001, r15
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        mov   #0x0170, r14
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        call  #WAIT_FUNC
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        mov   #0x1000, r15
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        /* -------   WATCHDOG TEST INTERVAL MODE /64 - ACLK        ------ */
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        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
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        eint
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        bis.b   #0x01,   &IE1
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        mov.b   #0x00, &BCSCTL1	  ;# ACLK = LFXTCLK/1
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        mov   #0x5a1f, &WDTCTL	  ;# Enable interval mode /64 & clear counter
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        mov   #0x1001, r15
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        mov   #0x1000, r14
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        call  #WAIT_FUNC
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        mov   #0x2000, r15
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        /* ----------------------         END OF TEST        --------------- */
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end_of_test:
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        nop
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        br #0xffff
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        /* ----------------------      INTERRUPT ROUTINES    --------------- */
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WDOG_VECTOR:
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        xor  #0x0001, r5        ; # Toggle r5[0] for testbench stimulus check
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        reti
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        /* ----------------------         INTERRUPT VECTORS  --------------- */
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.section .vectors, "a"
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.word end_of_test  ; Interrupt  0 (lowest priority)    
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.word end_of_test  ; Interrupt  1                      
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.word end_of_test  ; Interrupt  2                      
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.word end_of_test  ; Interrupt  3                      
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.word end_of_test  ; Interrupt  4                      
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.word end_of_test  ; Interrupt  5                      
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.word end_of_test  ; Interrupt  6                      
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.word end_of_test  ; Interrupt  7                      
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.word end_of_test  ; Interrupt  8                      
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.word end_of_test  ; Interrupt  9                      
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.word WDOG_VECTOR  ; Interrupt 10                      Watchdog timer
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.word end_of_test  ; Interrupt 11                      
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.word end_of_test  ; Interrupt 12                      
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.word end_of_test  ; Interrupt 13                      
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.word end_of_test  ; Interrupt 14                      NMI
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.word main         ; Interrupt 15 (highest priority)   RESET

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