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olivier.gi |
/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/*===========================================================================*/
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/* WATCHDOG TIMER */
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/*---------------------------------------------------------------------------*/
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/* Test the Watdog timer: */
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/* - Clock source selection. */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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integer mclk_counter;
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always @ (posedge mclk)
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mclk_counter <= mclk_counter+1;
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integer r5_counter;
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always @ (posedge r5[0] or negedge r5[0])
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r5_counter <= r5_counter+1;
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initial
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begin
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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// WATCHDOG TEST INTERVAL MODE /64 - SMCLK == MCLK/2
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//--------------------------------------------------------
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@(r15 === 16'h0001);
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@(posedge r5[0]);
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@(negedge mclk);
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mclk_counter = 0;
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r5_counter = 0;
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repeat(1024) @(negedge mclk);
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if (mclk_counter !== 1024) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK =====");
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if (r5_counter !== 8) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK =====");
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// WATCHDOG TEST INTERVAL MODE /64 - ACLK == LFXTCLK/1
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//--------------------------------------------------------
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@(r15 === 16'h1001);
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@(negedge r5[0]);
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@(negedge mclk);
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mclk_counter = 0;
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r5_counter = 0;
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repeat(7813) @(negedge mclk);
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if (mclk_counter !== 7813) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK =====");
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if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK =====");
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stimulus_done = 1;
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end
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