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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_interval.s43] - Blame information for rev 2

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            WATCHDOG TIMER                                 */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer:                                                    */
/*                        - Interval timer mode.                             */
/*===========================================================================*/
 
.global main
 
.set   IE1,    0x0000
.set   IFG1,   0x0002
.set   WDTCTL, 0x0120
 
 
main:
 
        /* --------------   WATCHDOG TEST:  RD/WR ACCESS    --------------- */
 
        mov  &WDTCTL, r4
        mov  #0x5aff, &WDTCTL
        mov  &WDTCTL, r5
        mov  #0x5a55, &WDTCTL
        mov  &WDTCTL, r6
        mov  #0x5aaa, &WDTCTL
        mov  &WDTCTL, r7
        mov  #0x5a00, &WDTCTL
        mov  &WDTCTL, r8
 
        mov  #0x1000, r15
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /64  ------------ */
 
        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0001, r5
wait_loop_64:
        inc   r4
        cmp   #0x3401, r5
        jne   wait_loop_64
 
        mov   #0x2000, r15
 
 
 
        bic.b #0x01,   &IE1	  ;# Disable watchdog interrupt
 
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
 
        mov   #0x0010, r4
        mov   #0x0002, r5
wait_loop_64_no_irq:
        dec   r4
        cmp   #0x0000, r4
        jne   wait_loop_64_no_irq
 
        mov    &IFG1, r6
        mov       r4, r7
        bic.b #0x01,   &IFG1	  ;# Clear flag
        mov    &IFG1, r8
 
        mov   #0x2001, r15
 
 
 
        mov   #0x5a9b, &WDTCTL	  ;# Enable interval mode /64 & clear counter & enable hold
 
        mov   #0x0020, r4
        mov   #0x0022, r5
wait_loop_64_no_irq_hold:
        dec   r4
        cmp   #0x0000, r4
        jne   wait_loop_64_no_irq_hold
 
        mov    &IFG1, r6
        mov       r4, r7
 
        mov   #0x2002, r15
 
 
 
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter / Check counter clear
        mov   #0x0033, r4
 
        mov   #0x000C, r5
wait_loop_64_no_irq_clear1:
        dec   r5
        cmp   #0x0000, r5
        jne   wait_loop_64_no_irq_clear1
 
        mov   #0x5a1b, &WDTCTL	  ;# Clear counter
        mov    &IFG1, r6
 
        mov   #0x000C, r5
wait_loop_64_no_irq_clear2:
        dec   r5
        cmp   #0x0000, r5
        jne   wait_loop_64_no_irq_clear2
 
        mov    &IFG1, r7	  ;# Don't Clear counter
 
        mov   #0x000C, r5
wait_loop_64_no_irq_clear3:
        dec   r5
        cmp   #0x0000, r5
        jne   wait_loop_64_no_irq_clear3
 
        mov    &IFG1,   r8
        bic.b  #0x01,   &IFG1	  ;# Clear flag
 
 
        mov   #0x2003, r15
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /512  ------------ */
 
        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a1a, &WDTCTL	  ;# Enable interval mode /512 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0003, r5
wait_loop_512:
        inc   r4
        cmp   #0x3403, r5
        jne   wait_loop_512
 
        mov   #0x3000, r15
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /8192  ------------ */
 
        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a19, &WDTCTL	  ;# Enable interval mode /8192 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0004, r5
wait_loop_8192:
        inc   r4
        cmp   #0x3404, r5
        jne   wait_loop_8192
 
        mov   #0x4000, r15
 
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /32768  ------------ */
 
        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a18, &WDTCTL	  ;# Enable interval mode /32768 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0005, r5
wait_loop_32768:
        inc   r4
        cmp   #0x3405, r5
        jne   wait_loop_32768
 
        mov   #0x5000, r15
 
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
 
WDOG_VECTOR:
        bis  #0x3400, r5
        mov    &IFG1, r6
        mov       r4, r7
        reti
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word WDOG_VECTOR  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_interval.s43] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* WATCHDOG TIMER */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Watdog timer: */`
27			`/* - Interval timer mode. */`
28			`/===========================================================================/`
29
30			`.global main`
31
32			`.set IE1, 0x0000`
33			`.set IFG1, 0x0002`
34			`.set WDTCTL, 0x0120`
35
36
37			`main:`
38
39			`/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */`
40
41			`mov &WDTCTL, r4`
42			`mov #0x5aff, &WDTCTL`
43			`mov &WDTCTL, r5`
44			`mov #0x5a55, &WDTCTL`
45			`mov &WDTCTL, r6`
46			`mov #0x5aaa, &WDTCTL`
47			`mov &WDTCTL, r7`
48			`mov #0x5a00, &WDTCTL`
49			`mov &WDTCTL, r8`
50
51			`mov #0x1000, r15`
52
53
54			`/* -------------- WATCHDOG TEST: INTERVAL MODE /64 ------------ */`
55
56			`mov #0x0250, r1 ;# Initialize stack & Enable interrupts`
57			`eint`
58			`bis.b #0x01, &IE1`
59
60			`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter`
61
62			`mov #0x0000, r4`
63			`mov #0x0001, r5`
64			`wait_loop_64:`
65			`inc r4`
66			`cmp #0x3401, r5`
67			`jne wait_loop_64`
68
69			`mov #0x2000, r15`
70
71
72
73			`bic.b #0x01, &IE1 ;# Disable watchdog interrupt`
74
75			`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter`
76
77			`mov #0x0010, r4`
78			`mov #0x0002, r5`
79			`wait_loop_64_no_irq:`
80			`dec r4`
81			`cmp #0x0000, r4`
82			`jne wait_loop_64_no_irq`
83
84			`mov &IFG1, r6`
85			`mov r4, r7`
86			`bic.b #0x01, &IFG1 ;# Clear flag`
87			`mov &IFG1, r8`
88
89			`mov #0x2001, r15`
90
91
92
93			`mov #0x5a9b, &WDTCTL ;# Enable interval mode /64 & clear counter & enable hold`
94
95			`mov #0x0020, r4`
96			`mov #0x0022, r5`
97			`wait_loop_64_no_irq_hold:`
98			`dec r4`
99			`cmp #0x0000, r4`
100			`jne wait_loop_64_no_irq_hold`
101
102			`mov &IFG1, r6`
103			`mov r4, r7`
104
105			`mov #0x2002, r15`
106
107
108
109			`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter / Check counter clear`
110			`mov #0x0033, r4`
111
112			`mov #0x000C, r5`
113			`wait_loop_64_no_irq_clear1:`
114			`dec r5`
115			`cmp #0x0000, r5`
116			`jne wait_loop_64_no_irq_clear1`
117
118			`mov #0x5a1b, &WDTCTL ;# Clear counter`
119			`mov &IFG1, r6`
120
121			`mov #0x000C, r5`
122			`wait_loop_64_no_irq_clear2:`
123			`dec r5`
124			`cmp #0x0000, r5`
125			`jne wait_loop_64_no_irq_clear2`
126
127			`mov &IFG1, r7 ;# Don't Clear counter`
128
129			`mov #0x000C, r5`
130			`wait_loop_64_no_irq_clear3:`
131			`dec r5`
132			`cmp #0x0000, r5`
133			`jne wait_loop_64_no_irq_clear3`
134
135			`mov &IFG1, r8`
136			`bic.b #0x01, &IFG1 ;# Clear flag`
137
138
139			`mov #0x2003, r15`
140
141
142			`/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */`
143
144			`mov #0x0250, r1 ;# Initialize stack & Enable interrupts`
145			`eint`
146			`bis.b #0x01, &IE1`
147
148			`mov #0x5a1a, &WDTCTL ;# Enable interval mode /512 & clear counter`
149
150			`mov #0x0000, r4`
151			`mov #0x0003, r5`
152			`wait_loop_512:`
153			`inc r4`
154			`cmp #0x3403, r5`
155			`jne wait_loop_512`
156
157			`mov #0x3000, r15`
158
159
160			`/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */`
161
162			`mov #0x0250, r1 ;# Initialize stack & Enable interrupts`
163			`eint`
164			`bis.b #0x01, &IE1`
165
166			`mov #0x5a19, &WDTCTL ;# Enable interval mode /8192 & clear counter`
167
168			`mov #0x0000, r4`
169			`mov #0x0004, r5`
170			`wait_loop_8192:`
171			`inc r4`
172			`cmp #0x3404, r5`
173			`jne wait_loop_8192`
174
175			`mov #0x4000, r15`
176
177
178
179			`/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */`
180
181			`mov #0x0250, r1 ;# Initialize stack & Enable interrupts`
182			`eint`
183			`bis.b #0x01, &IE1`
184
185			`mov #0x5a18, &WDTCTL ;# Enable interval mode /32768 & clear counter`
186
187			`mov #0x0000, r4`
188			`mov #0x0005, r5`
189			`wait_loop_32768:`
190			`inc r4`
191			`cmp #0x3405, r5`
192			`jne wait_loop_32768`
193
194			`mov #0x5000, r15`
195
196
197
198
199			`/* ---------------------- END OF TEST --------------- */`
200			`end_of_test:`
201			`nop`
202			`br #0xffff`
203
204
205			`/* ---------------------- INTERRUPT ROUTINES --------------- */`
206
207			`WDOG_VECTOR:`
208			`bis #0x3400, r5`
209			`mov &IFG1, r6`
210			`mov r4, r7`
211			`reti`
212
213
214			`/* ---------------------- INTERRUPT VECTORS --------------- */`
215
216			`.section .vectors, "a"`
217			`.word end_of_test ; Interrupt 0 (lowest priority)`
218			`.word end_of_test ; Interrupt 1`
219			`.word end_of_test ; Interrupt 2`
220			`.word end_of_test ; Interrupt 3`
221			`.word end_of_test ; Interrupt 4`
222			`.word end_of_test ; Interrupt 5`
223			`.word end_of_test ; Interrupt 6`
224			`.word end_of_test ; Interrupt 7`
225			`.word end_of_test ; Interrupt 8`
226			`.word end_of_test ; Interrupt 9`
227			`.word WDOG_VECTOR ; Interrupt 10 Watchdog timer`
228			`.word end_of_test ; Interrupt 11`
229			`.word end_of_test ; Interrupt 12`
230			`.word end_of_test ; Interrupt 13`
231			`.word end_of_test ; Interrupt 14 NMI`
232			`.word main ; Interrupt 15 (highest priority) RESET`