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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_watchdog.s43] - Blame information for rev 2

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            WATCHDOG TIMER                                 */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer:                                                    */
/*                        - Watchdog mode.                                   */
/*===========================================================================*/
 
.global main
 
.set   IE1,    0x0000
.set   IFG1,   0x0002
.set   WDTCTL, 0x0120
 
 
main:
 
        /* --------------   WATCHDOG TEST:  STARTUP SEQUENCE  --------------- */
 
        mov   &IFG1, r4       	;# Check if we come out of a watchdog reset
        cmp #0x0000, r4
        jeq   RD_WR_ACCESS
 
        mov &0x0250, r15        ;# If yes, check RAM variable to see where to go next
 
        cmp #0x0000, r15
        jeq   RESET_64
        cmp #0x1000, r15
        jeq   RESET_512
        cmp #0x2000, r15
        jeq   RESET_8192
        cmp #0x3000, r15
        jeq   RESET_32768
        cmp #0x4000, r15
        jeq   CHECK_32768
 
        jmp  end_of_test
 
 
        /* --------------   WATCHDOG TEST:  RD/WR ACCESS    --------------- */
RD_WR_ACCESS:
        mov  #0x0000, &0x0250
 
        mov  &WDTCTL, &0x0200
        mov  #0x5aff, &WDTCTL
        mov  &WDTCTL, &0x0202
        mov  #0x5a55, &WDTCTL
        mov  &WDTCTL, &0x0204
        mov  #0x5aaa, &WDTCTL
        mov  &WDTCTL, &0x0206
        mov  #0x5a00, &WDTCTL
        mov  &WDTCTL, &0x0208
 
        mov  #0xDEAD, &WDTCTL	 ;# Generate reset through wrong password
 
        jmp  end_of_test         ;# Force end of test if watchdog reset don't happen
 
 
 
        /* --------------   WATCHDOG TEST:  WATCHODG MODE /64  ------------ */
RESET_64:
        bic.b #0x01,   &IFG1
        mov   #0x1000, &0x0250
 
        mov   #0x5a0b, &WDTCTL	 ;# Enable watchdog mode /64 & clear counter
 
        mov   #0x0000, &0x0200
wait_loop_64:
        inc   &0x0200
        jmp   wait_loop_64
 
        jmp   end_of_test        ;# Force end of test if watchdog reset don't happen
 
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /512  ------------ */
RESET_512:
        bic.b #0x01,   &IFG1
        mov   #0x2000, &0x0250
 
        mov   #0x5a0a, &WDTCTL	  ;# Enable watchdog mode /512 & clear counter
 
        mov   #0x0000, &0x0202
wait_loop_512:
        inc   &0x0202
        jmp   wait_loop_512
 
        jmp   end_of_test         ;# Force end of test if watchdog reset don't happen
 
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /8192  ------------ */
RESET_8192:
        bic.b #0x01,   &IFG1
        mov   #0x3000, &0x0250
 
        mov   #0x5a09, &WDTCTL	  ;# Enable watchdog mode /8192 & clear counter
 
        mov   #0x0000, &0x0204
wait_loop_8192:
        inc   &0x0204
        jmp   wait_loop_8192
 
        jmp   end_of_test         ;# Force end of test if watchdog reset don't happen
 
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /32768  ------------ */
RESET_32768:
        bic.b #0x01,   &IFG1
        mov   #0x4000, &0x0250
 
        mov   #0x5a08, &WDTCTL	  ;# Enable interval mode /32768 & clear counter
 
        mov   #0x0000, &0x0206
wait_loop_32768:
        inc   &0x0206
        jmp   wait_loop_32768
 
        jmp   end_of_test         ;# Force end of test if watchdog reset don't happen
 
 
CHECK_32768:
        bic.b #0x01,   &IFG1
        mov   #0x5000, &0x0250
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
 
WDOG_VECTOR:
        bis  #0x3400, r5
        mov    &IFG1, r6
        mov       r4, r7
        reti
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word WDOG_VECTOR  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* WATCHDOG TIMER */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Watdog timer: */`
27			`/* - Watchdog mode. */`
28			`/===========================================================================/`
29
30			`.global main`
31
32			`.set IE1, 0x0000`
33			`.set IFG1, 0x0002`
34			`.set WDTCTL, 0x0120`
35
36
37			`main:`
38
39			`/* -------------- WATCHDOG TEST: STARTUP SEQUENCE --------------- */`
40
41			`mov &IFG1, r4 ;# Check if we come out of a watchdog reset`
42			`cmp #0x0000, r4`
43			`jeq RD_WR_ACCESS`
44
45			`mov &0x0250, r15 ;# If yes, check RAM variable to see where to go next`
46
47			`cmp #0x0000, r15`
48			`jeq RESET_64`
49			`cmp #0x1000, r15`
50			`jeq RESET_512`
51			`cmp #0x2000, r15`
52			`jeq RESET_8192`
53			`cmp #0x3000, r15`
54			`jeq RESET_32768`
55			`cmp #0x4000, r15`
56			`jeq CHECK_32768`
57
58			`jmp end_of_test`
59
60
61			`/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */`
62			`RD_WR_ACCESS:`
63			`mov #0x0000, &0x0250`
64
65			`mov &WDTCTL, &0x0200`
66			`mov #0x5aff, &WDTCTL`
67			`mov &WDTCTL, &0x0202`
68			`mov #0x5a55, &WDTCTL`
69			`mov &WDTCTL, &0x0204`
70			`mov #0x5aaa, &WDTCTL`
71			`mov &WDTCTL, &0x0206`
72			`mov #0x5a00, &WDTCTL`
73			`mov &WDTCTL, &0x0208`
74
75			`mov #0xDEAD, &WDTCTL ;# Generate reset through wrong password`
76
77			`jmp end_of_test ;# Force end of test if watchdog reset don't happen`
78
79
80
81			`/* -------------- WATCHDOG TEST: WATCHODG MODE /64 ------------ */`
82			`RESET_64:`
83			`bic.b #0x01, &IFG1`
84			`mov #0x1000, &0x0250`
85
86			`mov #0x5a0b, &WDTCTL ;# Enable watchdog mode /64 & clear counter`
87
88			`mov #0x0000, &0x0200`
89			`wait_loop_64:`
90			`inc &0x0200`
91			`jmp wait_loop_64`
92
93			`jmp end_of_test ;# Force end of test if watchdog reset don't happen`
94
95
96
97			`/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */`
98			`RESET_512:`
99			`bic.b #0x01, &IFG1`
100			`mov #0x2000, &0x0250`
101
102			`mov #0x5a0a, &WDTCTL ;# Enable watchdog mode /512 & clear counter`
103
104			`mov #0x0000, &0x0202`
105			`wait_loop_512:`
106			`inc &0x0202`
107			`jmp wait_loop_512`
108
109			`jmp end_of_test ;# Force end of test if watchdog reset don't happen`
110
111
112
113			`/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */`
114			`RESET_8192:`
115			`bic.b #0x01, &IFG1`
116			`mov #0x3000, &0x0250`
117
118			`mov #0x5a09, &WDTCTL ;# Enable watchdog mode /8192 & clear counter`
119
120			`mov #0x0000, &0x0204`
121			`wait_loop_8192:`
122			`inc &0x0204`
123			`jmp wait_loop_8192`
124
125			`jmp end_of_test ;# Force end of test if watchdog reset don't happen`
126
127
128
129			`/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */`
130			`RESET_32768:`
131			`bic.b #0x01, &IFG1`
132			`mov #0x4000, &0x0250`
133
134			`mov #0x5a08, &WDTCTL ;# Enable interval mode /32768 & clear counter`
135
136			`mov #0x0000, &0x0206`
137			`wait_loop_32768:`
138			`inc &0x0206`
139			`jmp wait_loop_32768`
140
141			`jmp end_of_test ;# Force end of test if watchdog reset don't happen`
142
143
144			`CHECK_32768:`
145			`bic.b #0x01, &IFG1`
146			`mov #0x5000, &0x0250`
147
148
149			`/* ---------------------- END OF TEST --------------- */`
150			`end_of_test:`
151			`nop`
152			`br #0xffff`
153
154
155			`/* ---------------------- INTERRUPT ROUTINES --------------- */`
156
157			`WDOG_VECTOR:`
158			`bis #0x3400, r5`
159			`mov &IFG1, r6`
160			`mov r4, r7`
161			`reti`
162
163
164			`/* ---------------------- INTERRUPT VECTORS --------------- */`
165
166			`.section .vectors, "a"`
167			`.word end_of_test ; Interrupt 0 (lowest priority)`
168			`.word end_of_test ; Interrupt 1`
169			`.word end_of_test ; Interrupt 2`
170			`.word end_of_test ; Interrupt 3`
171			`.word end_of_test ; Interrupt 4`
172			`.word end_of_test ; Interrupt 5`
173			`.word end_of_test ; Interrupt 6`
174			`.word end_of_test ; Interrupt 7`
175			`.word end_of_test ; Interrupt 8`
176			`.word end_of_test ; Interrupt 9`
177			`.word WDOG_VECTOR ; Interrupt 10 Watchdog timer`
178			`.word end_of_test ; Interrupt 11`
179			`.word end_of_test ; Interrupt 12`
180			`.word end_of_test ; Interrupt 13`
181			`.word end_of_test ; Interrupt 14 NMI`
182			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_watchdog.s43] - Blame information for rev 2