OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_watchdog.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                            WATCHDOG TIMER                                 */
25
/*---------------------------------------------------------------------------*/
26
/* Test the Watdog timer:                                                    */
27
/*                        - Watchdog mode.                                   */
28
/*===========================================================================*/
29
 
30
`define LONG_TIMEOUT
31
 
32
initial
33
   begin
34
      $display(" ===============================================");
35
      $display("|                 START SIMULATION              |");
36
      $display(" ===============================================");
37
      repeat(5) @(posedge mclk);
38
      stimulus_done = 0;
39
 
40
 
41
      // WATCHDOG TEST:  RD/WR ACCESS
42
      //--------------------------------------------------------
43
 
44
      @(mem250===16'h1000);
45
      if (mem200 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 =====");
46
      if (mem202 !== 16'h69d7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69d3 =====");
47
      if (mem204 !== 16'h6955) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6951 =====");
48
      if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 =====");
49
      if (mem208 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 =====");
50
 
51
 
52
      // WATCHDOG TEST:  WATCHDOG MODE /64
53
      //--------------------------------------------------------
54
 
55
      @(mem250===16'h2000);
56
      if (mem200 !== 16'h000A) tb_error("====== WATCHDOG MODE /64: @0x200 != 0x000A =====");
57
 
58
      $display("Watchdog mode /64 mode test completed...");
59
 
60
 
61
      // WATCHDOG TEST:  INTERVAL MODE /512
62
      //--------------------------------------------------------
63
 
64
      @(mem250===16'h3000);
65
      if (mem202 !== 16'h0055) tb_error("====== WATCHDOG MODE /512: @0x202 != 0x0055 =====");
66
 
67
      $display("Watchdog mode /512 mode test completed...");
68
 
69
 
70
      // WATCHDOG TEST:  INTERVAL MODE /8192
71
      //--------------------------------------------------------
72
 
73
      @(mem250===16'h4000);
74
      if (mem204 !== 16'h0555) tb_error("====== WATCHDOG MODE /8192: @0x204 != 0x0555 =====");
75
 
76
      $display("Watchdog mode /8192 mode test completed...");
77
 
78
 
79
      // WATCHDOG TEST:  INTERVAL MODE /32768
80
      //--------------------------------------------------------
81
 
82
      @(mem250===16'h5000);
83
      if (mem206 !== 16'h1555) tb_error("====== WATCHDOG MODE /32768: @0x206 != 0x1555 =====");
84
 
85
      $display("Watchdog mode /32768 mode test completed...");
86
 
87
 
88
      stimulus_done = 1;
89
   end
90
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.