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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src-c/] [sandbox/] [sandbox.v] - Blame information for rev 202

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1 76 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                                 SANDBOX                                   */
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/*---------------------------------------------------------------------------*/
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
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/*===========================================================================*/
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
41 202 olivier.gi
      // Disable automatic DMA verification
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      #10;
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      dma_verif_on = 0;
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45 76 olivier.gi
      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
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48 145 olivier.gi
      //---------------------------------------
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      // Check CPU configuration
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      //---------------------------------------
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      if ((`PMEM_SIZE !== 24576) || (`DMEM_SIZE !== 16384))
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        begin
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           $display(" ===============================================");
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           $display("|               SIMULATION ERROR                |");
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           $display("|                                               |");
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           $display("|  Core must be configured for:                 |");
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           $display("|               - 24kB program memory           |");
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           $display("|               - 16kB data memory              |");
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           $display(" ===============================================");
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           $finish;
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        end
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      //---------------------------------------
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      // Generate stimulus
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      //---------------------------------------
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68 76 olivier.gi
      repeat(1000) @(posedge mclk);
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      p1_din = 8'h01;
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      repeat(10) @(posedge mclk);
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      p1_din = 8'h00;
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      repeat(1000) @(posedge mclk);
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      p1_din = 8'h01;
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      repeat(10) @(posedge mclk);
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      p1_din = 8'h00;
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      repeat(1000) @(posedge mclk);
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      stimulus_done = 1;
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      $display(" ===============================================");
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      $display("|               SIMULATION DONE                 |");
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      $display("|       (stopped through verilog stimulus)      |");
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      $display(" ===============================================");
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      $finish;
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   end
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