URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [synthesis/] [actel/] [run_analysis.log] - Blame information for rev 64

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Line No.	Rev	Author	Line
1	64	olivier.gi	`#####################################################################################`
2			`# START SYNTHESIS`
3			`#====================================================================================`
4			`# ProASIC3E (A3PE1500), speedgrade: Std`
5			`#====================================================================================`
6			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
7			`# 12 10 0 0 0 0 0`
8			`#====================================================================================`
9
10
11			`Clock Domain: dco_clk`
12			`Period (ns): 59.496`
13			`Frequency (MHz): 16.808`
14			`Required Period (ns): 40.000`
15			`Required Frequency (MHz): 25.000`
16			`External Setup (ns): 56.596`
17			`External Hold (ns): 0.000`
18			`Min Clock-To-Out (ns): 0.000`
19			`Max Clock-To-Out (ns): 65.840`
20
21			`Input to Output`
22			`Min Delay (ns): 0.000`
23			`Max Delay (ns): 62.940`
24
25
26			`====================================================================================`
27			`Compile report:`
28			`===============`
29
30			`CORE Used: 3585`
31			`Core Information:`
32
33			`Type \| Instances \| Core tiles`
34			`--------\|--------------\|-----------`
35			`COMB \| 3106 \| 3106`
36			`SEQ \| 479 \| 479`
37
38
39			`====================================================================================`
40			`# SYNTHESIS DONE`
41			`#####################################################################################`
42
43			`#####################################################################################`
44			`# START SYNTHESIS`
45			`#====================================================================================`
46			`# ProASIC3E (A3PE1500), speedgrade: -1`
47			`#====================================================================================`
48			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
49			`# 12 10 0 0 0 0 0`
50			`#====================================================================================`
51
52
53			`Clock Domain: dco_clk`
54			`Period (ns): 55.520`
55			`Frequency (MHz): 18.012`
56			`Required Period (ns): 40.000`
57			`Required Frequency (MHz): 25.000`
58			`External Setup (ns): 51.193`
59			`External Hold (ns): 0.486`
60			`Min Clock-To-Out (ns): 3.058`
61			`Max Clock-To-Out (ns): 64.779`
62
63			`Input to Output`
64			`Min Delay (ns): 2.046`
65			`Max Delay (ns): 60.452`
66
67
68			`====================================================================================`
69			`Compile report:`
70			`===============`
71
72			`CORE Used: 3635`
73			`Core Information:`
74
75			`Type \| Instances \| Core tiles`
76			`--------\|--------------\|-----------`
77			`COMB \| 3156 \| 3156`
78			`SEQ \| 479 \| 479`
79
80
81			`====================================================================================`
82			`# SYNTHESIS DONE`
83			`#####################################################################################`
84
85			`#####################################################################################`
86			`# START SYNTHESIS`
87			`#====================================================================================`
88			`# ProASIC3E (A3PE1500), speedgrade: -2`
89			`#====================================================================================`
90			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
91			`# 12 10 0 0 0 0 0`
92			`#====================================================================================`
93
94
95			`Clock Domain: dco_clk`
96			`Period (ns): 44.550`
97			`Frequency (MHz): 22.447`
98			`Required Period (ns): 40.000`
99			`Required Frequency (MHz): 25.000`
100			`External Setup (ns): 41.682`
101			`External Hold (ns): 0.248`
102			`Min Clock-To-Out (ns): 3.318`
103			`Max Clock-To-Out (ns): 51.566`
104
105			`Input to Output`
106			`Min Delay (ns): 2.088`
107			`Max Delay (ns): 48.698`
108
109
110			`====================================================================================`
111			`Compile report:`
112			`===============`
113
114			`CORE Used: 3556`
115			`Core Information:`
116
117			`Type \| Instances \| Core tiles`
118			`--------\|--------------\|-----------`
119			`COMB \| 3077 \| 3077`
120			`SEQ \| 479 \| 479`
121
122
123			`====================================================================================`
124			`# SYNTHESIS DONE`
125			`#####################################################################################`
126
127			`#####################################################################################`
128			`# START SYNTHESIS`
129			`#====================================================================================`
130			`# ProASIC3L (A3P1000L), speedgrade: Std`
131			`#====================================================================================`
132			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
133			`# 12 10 0 0 0 0 0`
134			`#====================================================================================`
135
136
137			`Clock Domain: dco_clk`
138			`Period (ns): 69.886`
139			`Frequency (MHz): 14.309`
140			`Required Period (ns): 40.000`
141			`Required Frequency (MHz): 25.000`
142			`External Setup (ns): 65.083`
143			`External Hold (ns): 0.765`
144			`Min Clock-To-Out (ns): 7.615`
145			`Max Clock-To-Out (ns): 75.891`
146
147			`Input to Output`
148			`Min Delay (ns): 4.971`
149			`Max Delay (ns): 71.088`
150
151
152			`====================================================================================`
153			`Compile report:`
154			`===============`
155
156			`CORE Used: 3549`
157			`Core Information:`
158
159			`Type \| Instances \| Core tiles`
160			`--------\|--------------\|-----------`
161			`COMB \| 3069 \| 3069`
162			`SEQ \| 480 \| 480`
163
164
165			`====================================================================================`
166			`# SYNTHESIS DONE`
167			`#####################################################################################`
168
169			`#####################################################################################`
170			`# START SYNTHESIS`
171			`#====================================================================================`
172			`# ProASIC3L (A3P1000L), speedgrade: -1`
173			`#====================================================================================`
174			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
175			`# 12 10 0 0 0 0 0`
176			`#====================================================================================`
177
178
179			`Clock Domain: dco_clk`
180			`Period (ns): 55.165`
181			`Frequency (MHz): 18.127`
182			`Required Period (ns): 40.000`
183			`Required Frequency (MHz): 25.000`
184			`External Setup (ns): 51.175`
185			`External Hold (ns): 0.935`
186			`Min Clock-To-Out (ns): 6.100`
187			`Max Clock-To-Out (ns): 62.347`
188
189			`Input to Output`
190			`Min Delay (ns): 4.213`
191			`Max Delay (ns): 58.357`
192
193
194			`====================================================================================`
195			`Compile report:`
196			`===============`
197
198			`CORE Used: 3535`
199			`Core Information:`
200
201			`Type \| Instances \| Core tiles`
202			`--------\|--------------\|-----------`
203			`COMB \| 3056 \| 3056`
204			`SEQ \| 479 \| 479`
205
206
207			`====================================================================================`
208			`# SYNTHESIS DONE`
209			`#####################################################################################`
210
211			`#####################################################################################`
212			`# START SYNTHESIS`
213			`#====================================================================================`
214			`# ProASIC3 (A3P1000), speedgrade: Std`
215			`#====================================================================================`
216			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
217			`# 12 10 0 0 0 0 0`
218			`#====================================================================================`
219
220
221			`Clock Domain: dco_clk`
222			`Period (ns): 60.713`
223			`Frequency (MHz): 16.471`
224			`Required Period (ns): 40.000`
225			`Required Frequency (MHz): 25.000`
226			`External Setup (ns): 58.080`
227			`External Hold (ns): 0.000`
228			`Min Clock-To-Out (ns): 0.000`
229			`Max Clock-To-Out (ns): 67.811`
230
231			`Input to Output`
232			`Min Delay (ns): 0.000`
233			`Max Delay (ns): 65.178`
234
235
236			`====================================================================================`
237			`Compile report:`
238			`===============`
239
240			`CORE Used: 3585`
241			`Core Information:`
242
243			`Type \| Instances \| Core tiles`
244			`--------\|--------------\|-----------`
245			`COMB \| 3106 \| 3106`
246			`SEQ \| 479 \| 479`
247
248
249			`====================================================================================`
250			`# SYNTHESIS DONE`
251			`#####################################################################################`
252
253			`#####################################################################################`
254			`# START SYNTHESIS`
255			`#====================================================================================`
256			`# ProASIC3 (A3P1000), speedgrade: -1`
257			`#====================================================================================`
258			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
259			`# 12 10 0 0 0 0 0`
260			`#====================================================================================`
261
262
263			`Clock Domain: dco_clk`
264			`Period (ns): 55.458`
265			`Frequency (MHz): 18.032`
266			`Required Period (ns): 40.000`
267			`Required Frequency (MHz): 25.000`
268			`External Setup (ns): 50.559`
269			`External Hold (ns): 0.424`
270			`Min Clock-To-Out (ns): 2.941`
271			`Max Clock-To-Out (ns): 64.709`
272
273			`Input to Output`
274			`Min Delay (ns): 1.904`
275			`Max Delay (ns): 59.812`
276
277
278			`====================================================================================`
279			`Compile report:`
280			`===============`
281
282			`CORE Used: 3635`
283			`Core Information:`
284
285			`Type \| Instances \| Core tiles`
286			`--------\|--------------\|-----------`
287			`COMB \| 3156 \| 3156`
288			`SEQ \| 479 \| 479`
289
290
291			`====================================================================================`
292			`# SYNTHESIS DONE`
293			`#####################################################################################`
294
295			`#####################################################################################`
296			`# START SYNTHESIS`
297			`#====================================================================================`
298			`# ProASIC3 (A3P1000), speedgrade: -2`
299			`#====================================================================================`
300			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
301			`# 12 10 0 0 0 0 0`
302			`#====================================================================================`
303
304
305			`Clock Domain: dco_clk`
306			`Period (ns): 43.859`
307			`Frequency (MHz): 22.800`
308			`Required Period (ns): 40.000`
309			`Required Frequency (MHz): 25.000`
310			`External Setup (ns): 41.325`
311			`External Hold (ns): 0.349`
312			`Min Clock-To-Out (ns): 3.018`
313			`Max Clock-To-Out (ns): 48.521`
314
315			`Input to Output`
316			`Min Delay (ns): 1.893`
317			`Max Delay (ns): 45.987`
318
319
320			`====================================================================================`
321			`Compile report:`
322			`===============`
323
324			`CORE Used: 3556`
325			`Core Information:`
326
327			`Type \| Instances \| Core tiles`
328			`--------\|--------------\|-----------`
329			`COMB \| 3077 \| 3077`
330			`SEQ \| 479 \| 479`
331
332
333			`====================================================================================`
334			`# SYNTHESIS DONE`
335			`#####################################################################################`
336
337			`#####################################################################################`
338			`# START SYNTHESIS`
339			`#====================================================================================`
340			`# Fusion (AFS1500), speedgrade: Std`
341			`#====================================================================================`
342			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
343			`# 12 10 0 0 0 0 0`
344			`#====================================================================================`
345
346
347			`Clock Domain: dco_clk`
348			`Period (ns): 60.059`
349			`Frequency (MHz): 16.650`
350			`Required Period (ns): 40.000`
351			`Required Frequency (MHz): 25.000`
352			`External Setup (ns): 57.164`
353			`External Hold (ns): 0.000`
354			`Min Clock-To-Out (ns): 0.000`
355			`Max Clock-To-Out (ns): 68.807`
356
357			`Input to Output`
358			`Min Delay (ns): 0.000`
359			`Max Delay (ns): 65.912`
360
361
362			`====================================================================================`
363			`Compile report:`
364			`===============`
365
366			`CORE Used: 3585`
367			`Core Information:`
368
369			`Type \| Instances \| Core tiles`
370			`--------\|--------------\|-----------`
371			`COMB \| 3106 \| 3106`
372			`SEQ \| 479 \| 479`
373
374
375			`====================================================================================`
376			`# SYNTHESIS DONE`
377			`#####################################################################################`
378
379			`#####################################################################################`
380			`# START SYNTHESIS`
381			`#====================================================================================`
382			`# Fusion (AFS1500), speedgrade: -1`
383			`#====================================================================================`
384			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
385			`# 12 10 0 0 0 0 0`
386			`#====================================================================================`
387
388
389			`Clock Domain: dco_clk`
390			`Period (ns): 55.859`
391			`Frequency (MHz): 17.902`
392			`Required Period (ns): 40.000`
393			`Required Frequency (MHz): 25.000`
394			`External Setup (ns): 49.060`
395			`External Hold (ns): 0.991`
396			`Min Clock-To-Out (ns): 3.083`
397			`Max Clock-To-Out (ns): 62.333`
398
399			`Input to Output`
400			`Min Delay (ns): 2.212`
401			`Max Delay (ns): 55.534`
402
403
404			`====================================================================================`
405			`Compile report:`
406			`===============`
407
408			`CORE Used: 3635`
409			`Core Information:`
410
411			`Type \| Instances \| Core tiles`
412			`--------\|--------------\|-----------`
413			`COMB \| 3156 \| 3156`
414			`SEQ \| 479 \| 479`
415
416
417			`====================================================================================`
418			`# SYNTHESIS DONE`
419			`#####################################################################################`
420
421			`#####################################################################################`
422			`# START SYNTHESIS`
423			`#====================================================================================`
424			`# Fusion (AFS1500), speedgrade: -2`
425			`#====================================================================================`
426			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
427			`# 12 10 0 0 0 0 0`
428			`#====================================================================================`
429
430
431			`Clock Domain: dco_clk`
432			`Period (ns): 44.843`
433			`Frequency (MHz): 22.300`
434			`Required Period (ns): 40.000`
435			`Required Frequency (MHz): 25.000`
436			`External Setup (ns): 40.185`
437			`External Hold (ns): 1.018`
438			`Min Clock-To-Out (ns): 2.963`
439			`Max Clock-To-Out (ns): 51.927`
440
441			`Input to Output`
442			`Min Delay (ns): 2.260`
443			`Max Delay (ns): 47.269`
444
445
446			`====================================================================================`
447			`Compile report:`
448			`===============`
449
450			`CORE Used: 3556`
451			`Core Information:`
452
453			`Type \| Instances \| Core tiles`
454			`--------\|--------------\|-----------`
455			`COMB \| 3077 \| 3077`
456			`SEQ \| 479 \| 479`
457
458
459			`====================================================================================`
460			`# SYNTHESIS DONE`
461			`#####################################################################################`
462
463			`#####################################################################################`
464			`# START SYNTHESIS`
465			`#====================================================================================`
466			`# IGLOOE (AGLE600V5), speedgrade: Std`
467			`#====================================================================================`
468			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
469			`# 12 10 0 0 0 0 0`
470			`#====================================================================================`
471
472
473			`Clock Domain: dco_clk`
474			`Period (ns): 71.404`
475			`Frequency (MHz): 14.005`
476			`Required Period (ns): 40.000`
477			`Required Frequency (MHz): 25.000`
478			`External Setup (ns): 65.180`
479			`External Hold (ns): 0.000`
480			`Min Clock-To-Out (ns): 0.000`
481			`Max Clock-To-Out (ns): 79.196`
482
483			`Input to Output`
484			`Min Delay (ns): 0.000`
485			`Max Delay (ns): 72.972`
486
487
488			`====================================================================================`
489			`Compile report:`
490			`===============`
491
492			`CORE Used: 3646`
493			`Core Information:`
494
495			`Type \| Instances \| Core tiles`
496			`--------\|--------------\|-----------`
497			`COMB \| 3167 \| 3167`
498			`SEQ \| 479 \| 479`
499
500
501			`====================================================================================`
502			`# SYNTHESIS DONE`
503			`#####################################################################################`
504
505			`#####################################################################################`
506			`# START SYNTHESIS`
507			`#====================================================================================`
508			`# ProASIC3E (A3PE1500), speedgrade: Std`
509			`#====================================================================================`
510			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
511			`# 12 10 1 0 0 0 0`
512			`#====================================================================================`
513
514
515			`Clock Domain: dco_clk`
516			`Period (ns): 71.522`
517			`Frequency (MHz): 13.982`
518			`Required Period (ns): 40.000`
519			`Required Frequency (MHz): 25.000`
520			`External Setup (ns): 62.333`
521			`External Hold (ns): 0.000`
522			`Min Clock-To-Out (ns): 0.000`
523			`Max Clock-To-Out (ns): 71.649`
524
525			`Input to Output`
526			`Min Delay (ns): 0.000`
527			`Max Delay (ns): 70.065`
528
529
530			`====================================================================================`
531			`Compile report:`
532			`===============`
533
534			`CORE Used: 4884`
535			`Core Information:`
536
537			`Type \| Instances \| Core tiles`
538			`--------\|--------------\|-----------`
539			`COMB \| 4261 \| 4261`
540			`SEQ \| 623 \| 623`
541
542
543			`====================================================================================`
544			`# SYNTHESIS DONE`
545			`#####################################################################################`
546
547			`#####################################################################################`
548			`# START SYNTHESIS`
549			`#====================================================================================`
550			`# ProASIC3E (A3PE1500), speedgrade: -1`
551			`#====================================================================================`
552			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
553			`# 12 10 1 0 0 0 0`
554			`#====================================================================================`
555
556
557			`Clock Domain: dco_clk`
558			`Period (ns): 55.799`
559			`Frequency (MHz): 17.921`
560			`Required Period (ns): 40.000`
561			`Required Frequency (MHz): 25.000`
562			`External Setup (ns): 55.847`
563			`External Hold (ns): 0.430`
564			`Min Clock-To-Out (ns): 3.127`
565			`Max Clock-To-Out (ns): 62.868`
566
567			`Input to Output`
568			`Min Delay (ns): 2.070`
569			`Max Delay (ns): 62.916`
570
571
572			`====================================================================================`
573			`Compile report:`
574			`===============`
575
576			`CORE Used: 4742`
577			`Core Information:`
578
579			`Type \| Instances \| Core tiles`
580			`--------\|--------------\|-----------`
581			`COMB \| 4118 \| 4118`
582			`SEQ \| 624 \| 624`
583
584
585			`====================================================================================`
586			`# SYNTHESIS DONE`
587			`#####################################################################################`
588
589			`#####################################################################################`
590			`# START SYNTHESIS`
591			`#====================================================================================`
592			`# ProASIC3E (A3PE1500), speedgrade: -2`
593			`#====================================================================================`
594			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
595			`# 12 10 1 0 0 0 0`
596			`#====================================================================================`
597
598
599			`Clock Domain: dco_clk`
600			`Period (ns): 46.678`
601			`Frequency (MHz): 21.423`
602			`Required Period (ns): 40.000`
603			`Required Frequency (MHz): 25.000`
604			`External Setup (ns): 45.726`
605			`External Hold (ns): 0.184`
606			`Min Clock-To-Out (ns): 3.121`
607			`Max Clock-To-Out (ns): 52.569`
608
609			`Input to Output`
610			`Min Delay (ns): 2.125`
611			`Max Delay (ns): 51.617`
612
613
614			`====================================================================================`
615			`Compile report:`
616			`===============`
617
618			`CORE Used: 4811`
619			`Core Information:`
620
621			`Type \| Instances \| Core tiles`
622			`--------\|--------------\|-----------`
623			`COMB \| 4188 \| 4188`
624			`SEQ \| 623 \| 623`
625
626
627			`====================================================================================`
628			`# SYNTHESIS DONE`
629			`#####################################################################################`
630
631			`#####################################################################################`
632			`# START SYNTHESIS`
633			`#====================================================================================`
634			`# ProASIC3L (A3P1000L), speedgrade: Std`
635			`#====================================================================================`
636			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
637			`# 12 10 1 0 0 0 0`
638			`#====================================================================================`
639
640
641			`Clock Domain: dco_clk`
642			`Period (ns): 66.074`
643			`Frequency (MHz): 15.135`
644			`Required Period (ns): 40.000`
645			`Required Frequency (MHz): 25.000`
646			`External Setup (ns): 65.604`
647			`External Hold (ns): 0.636`
648			`Min Clock-To-Out (ns): 6.321`
649			`Max Clock-To-Out (ns): 74.907`
650
651			`Input to Output`
652			`Min Delay (ns): 4.750`
653			`Max Delay (ns): 75.465`
654
655
656			`====================================================================================`
657			`Compile report:`
658			`===============`
659
660			`CORE Used: 4774`
661			`Core Information:`
662
663			`Type \| Instances \| Core tiles`
664			`--------\|--------------\|-----------`
665			`COMB \| 4151 \| 4151`
666			`SEQ \| 623 \| 623`
667
668
669			`====================================================================================`
670			`# SYNTHESIS DONE`
671			`#####################################################################################`
672
673			`#####################################################################################`
674			`# START SYNTHESIS`
675			`#====================================================================================`
676			`# ProASIC3L (A3P1000L), speedgrade: -1`
677			`#====================================================================================`
678			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
679			`# 12 10 1 0 0 0 0`
680			`#====================================================================================`
681
682
683			`Clock Domain: dco_clk`
684			`Period (ns): 62.880`
685			`Frequency (MHz): 15.903`
686			`Required Period (ns): 40.000`
687			`Required Frequency (MHz): 25.000`
688			`External Setup (ns): 58.918`
689			`External Hold (ns): 0.501`
690			`Min Clock-To-Out (ns): 5.767`
691			`Max Clock-To-Out (ns): 68.704`
692
693			`Input to Output`
694			`Min Delay (ns): 4.032`
695			`Max Delay (ns): 66.092`
696
697
698			`====================================================================================`
699			`Compile report:`
700			`===============`
701
702			`CORE Used: 4776`
703			`Core Information:`
704
705			`Type \| Instances \| Core tiles`
706			`--------\|--------------\|-----------`
707			`COMB \| 4153 \| 4153`
708			`SEQ \| 623 \| 623`
709
710
711			`====================================================================================`
712			`# SYNTHESIS DONE`
713			`#####################################################################################`
714
715			`#####################################################################################`
716			`# START SYNTHESIS`
717			`#====================================================================================`
718			`# ProASIC3 (A3P1000), speedgrade: Std`
719			`#====================================================================================`
720			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
721			`# 12 10 1 0 0 0 0`
722			`#====================================================================================`
723
724
725			`Clock Domain: dco_clk`
726			`Period (ns): 66.554`
727			`Frequency (MHz): 15.025`
728			`Required Period (ns): 40.000`
729			`Required Frequency (MHz): 25.000`
730			`External Setup (ns): 61.743`
731			`External Hold (ns): 0.000`
732			`Min Clock-To-Out (ns): 0.000`
733			`Max Clock-To-Out (ns): 72.194`
734
735			`Input to Output`
736			`Min Delay (ns): 0.000`
737			`Max Delay (ns): 70.797`
738
739
740			`====================================================================================`
741			`Compile report:`
742			`===============`
743
744			`CORE Used: 4884`
745			`Core Information:`
746
747			`Type \| Instances \| Core tiles`
748			`--------\|--------------\|-----------`
749			`COMB \| 4261 \| 4261`
750			`SEQ \| 623 \| 623`
751
752
753			`====================================================================================`
754			`# SYNTHESIS DONE`
755			`#####################################################################################`
756
757			`#####################################################################################`
758			`# START SYNTHESIS`
759			`#====================================================================================`
760			`# ProASIC3 (A3P1000), speedgrade: -1`
761			`#====================================================================================`
762			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
763			`# 12 10 1 0 0 0 0`
764			`#====================================================================================`
765
766
767			`Clock Domain: dco_clk`
768			`Period (ns): 54.375`
769			`Frequency (MHz): 18.391`
770			`Required Period (ns): 40.000`
771			`Required Frequency (MHz): 25.000`
772			`External Setup (ns): 54.649`
773			`External Hold (ns): 0.420`
774			`Min Clock-To-Out (ns): 2.827`
775			`Max Clock-To-Out (ns): 59.461`
776
777			`Input to Output`
778			`Min Delay (ns): 1.902`
779			`Max Delay (ns): 59.735`
780
781
782			`====================================================================================`
783			`Compile report:`
784			`===============`
785
786			`CORE Used: 4742`
787			`Core Information:`
788
789			`Type \| Instances \| Core tiles`
790			`--------\|--------------\|-----------`
791			`COMB \| 4118 \| 4118`
792			`SEQ \| 624 \| 624`
793
794
795			`====================================================================================`
796			`# SYNTHESIS DONE`
797			`#####################################################################################`
798
799			`#####################################################################################`
800			`# START SYNTHESIS`
801			`#====================================================================================`
802			`# ProASIC3 (A3P1000), speedgrade: -2`
803			`#====================================================================================`
804			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
805			`# 12 10 1 0 0 0 0`
806			`#====================================================================================`
807
808
809			`Clock Domain: dco_clk`
810			`Period (ns): 46.154`
811			`Frequency (MHz): 21.667`
812			`Required Period (ns): 40.000`
813			`Required Frequency (MHz): 25.000`
814			`External Setup (ns): 46.484`
815			`External Hold (ns): 0.353`
816			`Min Clock-To-Out (ns): 3.003`
817			`Max Clock-To-Out (ns): 51.186`
818
819			`Input to Output`
820			`Min Delay (ns): 1.940`
821			`Max Delay (ns): 51.965`
822
823
824			`====================================================================================`
825			`Compile report:`
826			`===============`
827
828			`CORE Used: 4811`
829			`Core Information:`
830
831			`Type \| Instances \| Core tiles`
832			`--------\|--------------\|-----------`
833			`COMB \| 4188 \| 4188`
834			`SEQ \| 623 \| 623`
835
836
837			`====================================================================================`
838			`# SYNTHESIS DONE`
839			`#####################################################################################`
840
841			`#####################################################################################`
842			`# START SYNTHESIS`
843			`#====================================================================================`
844			`# Fusion (AFS1500), speedgrade: Std`
845			`#====================================================================================`
846			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
847			`# 12 10 1 0 0 0 0`
848			`#====================================================================================`
849
850
851			`Clock Domain: dco_clk`
852			`Period (ns): 70.208`
853			`Frequency (MHz): 14.243`
854			`Required Period (ns): 40.000`
855			`Required Frequency (MHz): 25.000`
856			`External Setup (ns): 60.252`
857			`External Hold (ns): 0.000`
858			`Min Clock-To-Out (ns): 0.000`
859			`Max Clock-To-Out (ns): 69.971`
860
861			`Input to Output`
862			`Min Delay (ns): 0.000`
863			`Max Delay (ns): 68.565`
864
865
866			`====================================================================================`
867			`Compile report:`
868			`===============`
869
870			`CORE Used: 4884`
871			`Core Information:`
872
873			`Type \| Instances \| Core tiles`
874			`--------\|--------------\|-----------`
875			`COMB \| 4261 \| 4261`
876			`SEQ \| 623 \| 623`
877
878
879			`====================================================================================`
880			`# SYNTHESIS DONE`
881			`#####################################################################################`
882
883			`#####################################################################################`
884			`# START SYNTHESIS`
885			`#====================================================================================`
886			`# Fusion (AFS1500), speedgrade: -1`
887			`#====================================================================================`
888			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
889			`# 12 10 1 0 0 0 0`
890			`#====================================================================================`
891
892
893			`Clock Domain: dco_clk`
894			`Period (ns): 56.209`
895			`Frequency (MHz): 17.791`
896			`Required Period (ns): 40.000`
897			`Required Frequency (MHz): 25.000`
898			`External Setup (ns): 54.735`
899			`External Hold (ns): 0.685`
900			`Min Clock-To-Out (ns): 2.951`
901			`Max Clock-To-Out (ns): 61.627`
902
903			`Input to Output`
904			`Min Delay (ns): 2.212`
905			`Max Delay (ns): 60.153`
906
907
908			`====================================================================================`
909			`Compile report:`
910			`===============`
911
912			`CORE Used: 4742`
913			`Core Information:`
914
915			`Type \| Instances \| Core tiles`
916			`--------\|--------------\|-----------`
917			`COMB \| 4118 \| 4118`
918			`SEQ \| 624 \| 624`
919
920
921			`====================================================================================`
922			`# SYNTHESIS DONE`
923			`#####################################################################################`
924
925			`#####################################################################################`
926			`# START SYNTHESIS`
927			`#====================================================================================`
928			`# Fusion (AFS1500), speedgrade: -2`
929			`#====================================================================================`
930			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
931			`# 12 10 1 0 0 0 0`
932			`#====================================================================================`
933
934
935			`Clock Domain: dco_clk`
936			`Period (ns): 48.594`
937			`Frequency (MHz): 20.579`
938			`Required Period (ns): 40.000`
939			`Required Frequency (MHz): 25.000`
940			`External Setup (ns): 49.120`
941			`External Hold (ns): 1.041`
942			`Min Clock-To-Out (ns): 2.988`
943			`Max Clock-To-Out (ns): 53.864`
944
945			`Input to Output`
946			`Min Delay (ns): 2.262`
947			`Max Delay (ns): 54.390`
948
949
950			`====================================================================================`
951			`Compile report:`
952			`===============`
953
954			`CORE Used: 4811`
955			`Core Information:`
956
957			`Type \| Instances \| Core tiles`
958			`--------\|--------------\|-----------`
959			`COMB \| 4188 \| 4188`
960			`SEQ \| 623 \| 623`
961
962
963			`====================================================================================`
964			`# SYNTHESIS DONE`
965			`#####################################################################################`
966
967			`#####################################################################################`
968			`# START SYNTHESIS`
969			`#====================================================================================`
970			`# IGLOOE (AGLE600V5), speedgrade: Std`
971			`#====================================================================================`
972			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
973			`# 12 10 1 0 0 0 0`
974			`#====================================================================================`
975
976
977			`Clock Domain: dco_clk`
978			`Period (ns): 73.462`
979			`Frequency (MHz): 13.612`
980			`Required Period (ns): 40.000`
981			`Required Frequency (MHz): 25.000`
982			`External Setup (ns): 64.585`
983			`External Hold (ns): 0.000`
984			`Min Clock-To-Out (ns): 0.000`
985			`Max Clock-To-Out (ns): 73.620`
986
987			`Input to Output`
988			`Min Delay (ns): 0.000`
989			`Max Delay (ns): 70.771`
990
991
992			`====================================================================================`
993			`Compile report:`
994			`===============`
995
996			`CORE Used: 4857`
997			`Core Information:`
998
999			`Type \| Instances \| Core tiles`
1000			`--------\|--------------\|-----------`
1001			`COMB \| 4234 \| 4234`
1002			`SEQ \| 623 \| 623`
1003
1004
1005			`====================================================================================`
1006			`# SYNTHESIS DONE`
1007			`#####################################################################################`
1008
1009			`#####################################################################################`
1010			`# START SYNTHESIS`
1011			`#====================================================================================`
1012			`# ProASIC3E (A3PE1500), speedgrade: Std`
1013			`#====================================================================================`
1014			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1015			`# 12 10 1 1 0 0 0`
1016			`#====================================================================================`
1017
1018
1019			`Clock Domain: dco_clk`
1020			`Period (ns): 61.636`
1021			`Frequency (MHz): 16.224`
1022			`Required Period (ns): 40.000`
1023			`Required Frequency (MHz): 25.000`
1024			`External Setup (ns): 57.137`
1025			`External Hold (ns): 0.000`
1026			`Min Clock-To-Out (ns): 0.000`
1027			`Max Clock-To-Out (ns): 67.618`
1028
1029			`Input to Output`
1030			`Min Delay (ns): 0.000`
1031			`Max Delay (ns): 63.463`
1032
1033
1034			`====================================================================================`
1035			`Compile report:`
1036			`===============`
1037
1038			`CORE Used: 5014`
1039			`Core Information:`
1040
1041			`Type \| Instances \| Core tiles`
1042			`--------\|--------------\|-----------`
1043			`COMB \| 4348 \| 4348`
1044			`SEQ \| 666 \| 666`
1045
1046
1047			`====================================================================================`
1048			`# SYNTHESIS DONE`
1049			`#####################################################################################`
1050
1051			`#####################################################################################`
1052			`# START SYNTHESIS`
1053			`#====================================================================================`
1054			`# ProASIC3E (A3PE1500), speedgrade: -1`
1055			`#====================================================================================`
1056			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1057			`# 12 10 1 1 0 0 0`
1058			`#====================================================================================`
1059
1060
1061			`Clock Domain: dco_clk`
1062			`Period (ns): 62.374`
1063			`Frequency (MHz): 16.032`
1064			`Required Period (ns): 40.000`
1065			`Required Frequency (MHz): 25.000`
1066			`External Setup (ns): 52.661`
1067			`External Hold (ns): 0.369`
1068			`Min Clock-To-Out (ns): 3.057`
1069			`Max Clock-To-Out (ns): 60.319`
1070
1071			`Input to Output`
1072			`Min Delay (ns): 2.079`
1073			`Max Delay (ns): 57.466`
1074
1075
1076			`====================================================================================`
1077			`Compile report:`
1078			`===============`
1079
1080			`CORE Used: 5004`
1081			`Core Information:`
1082
1083			`Type \| Instances \| Core tiles`
1084			`--------\|--------------\|-----------`
1085			`COMB \| 4337 \| 4337`
1086			`SEQ \| 667 \| 667`
1087
1088
1089			`====================================================================================`
1090			`# SYNTHESIS DONE`
1091			`#####################################################################################`
1092
1093			`#####################################################################################`
1094			`# START SYNTHESIS`
1095			`#====================================================================================`
1096			`# ProASIC3E (A3PE1500), speedgrade: -2`
1097			`#====================================================================================`
1098			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1099			`# 12 10 1 1 0 0 0`
1100			`#====================================================================================`
1101
1102
1103			`Clock Domain: dco_clk`
1104			`Period (ns): 47.073`
1105			`Frequency (MHz): 21.244`
1106			`Required Period (ns): 40.000`
1107			`Required Frequency (MHz): 25.000`
1108			`External Setup (ns): 46.714`
1109			`External Hold (ns): 0.437`
1110			`Min Clock-To-Out (ns): 3.315`
1111			`Max Clock-To-Out (ns): 52.799`
1112
1113			`Input to Output`
1114			`Min Delay (ns): 2.109`
1115			`Max Delay (ns): 52.440`
1116
1117
1118			`====================================================================================`
1119			`Compile report:`
1120			`===============`
1121
1122			`CORE Used: 5002`
1123			`Core Information:`
1124
1125			`Type \| Instances \| Core tiles`
1126			`--------\|--------------\|-----------`
1127			`COMB \| 4336 \| 4336`
1128			`SEQ \| 666 \| 666`
1129
1130
1131			`====================================================================================`
1132			`# SYNTHESIS DONE`
1133			`#####################################################################################`
1134
1135			`#####################################################################################`
1136			`# START SYNTHESIS`
1137			`#====================================================================================`
1138			`# ProASIC3L (A3P1000L), speedgrade: Std`
1139			`#====================================================================================`
1140			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1141			`# 12 10 1 1 0 0 0`
1142			`#====================================================================================`
1143
1144
1145			`Clock Domain: dco_clk`
1146			`Period (ns): 69.350`
1147			`Frequency (MHz): 14.420`
1148			`Required Period (ns): 40.000`
1149			`Required Frequency (MHz): 25.000`
1150			`External Setup (ns): 66.678`
1151			`External Hold (ns): 1.139`
1152			`Min Clock-To-Out (ns): 6.759`
1153			`Max Clock-To-Out (ns): 73.782`
1154
1155			`Input to Output`
1156			`Min Delay (ns): 4.757`
1157			`Max Delay (ns): 72.203`
1158
1159
1160			`====================================================================================`
1161			`Compile report:`
1162			`===============`
1163
1164			`CORE Used: 5012`
1165			`Core Information:`
1166
1167			`Type \| Instances \| Core tiles`
1168			`--------\|--------------\|-----------`
1169			`COMB \| 4345 \| 4345`
1170			`SEQ \| 667 \| 667`
1171
1172
1173			`====================================================================================`
1174			`# SYNTHESIS DONE`
1175			`#####################################################################################`
1176
1177			`#####################################################################################`
1178			`# START SYNTHESIS`
1179			`#====================================================================================`
1180			`# ProASIC3L (A3P1000L), speedgrade: -1`
1181			`#====================================================================================`
1182			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1183			`# 12 10 1 1 0 0 0`
1184			`#====================================================================================`
1185
1186
1187			`Clock Domain: dco_clk`
1188			`Period (ns): 54.514`
1189			`Frequency (MHz): 18.344`
1190			`Required Period (ns): 40.000`
1191			`Required Frequency (MHz): 25.000`
1192			`External Setup (ns): 52.044`
1193			`External Hold (ns): 0.934`
1194			`Min Clock-To-Out (ns): 5.679`
1195			`Max Clock-To-Out (ns): 62.000`
1196
1197			`Input to Output`
1198			`Min Delay (ns): 4.032`
1199			`Max Delay (ns): 58.639`
1200
1201
1202			`====================================================================================`
1203			`Compile report:`
1204			`===============`
1205
1206			`CORE Used: 5032`
1207			`Core Information:`
1208
1209			`Type \| Instances \| Core tiles`
1210			`--------\|--------------\|-----------`
1211			`COMB \| 4366 \| 4366`
1212			`SEQ \| 666 \| 666`
1213
1214
1215			`====================================================================================`
1216			`# SYNTHESIS DONE`
1217			`#####################################################################################`
1218
1219			`#####################################################################################`
1220			`# START SYNTHESIS`
1221			`#====================================================================================`
1222			`# ProASIC3 (A3P1000), speedgrade: Std`
1223			`#====================================================================================`
1224			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1225			`# 12 10 1 1 0 0 0`
1226			`#====================================================================================`
1227
1228
1229			`Clock Domain: dco_clk`
1230			`Period (ns): 60.421`
1231			`Frequency (MHz): 16.551`
1232			`Required Period (ns): 40.000`
1233			`Required Frequency (MHz): 25.000`
1234			`External Setup (ns): 58.594`
1235			`External Hold (ns): 0.000`
1236			`Min Clock-To-Out (ns): 0.000`
1237			`Max Clock-To-Out (ns): 69.078`
1238
1239			`Input to Output`
1240			`Min Delay (ns): 0.000`
1241			`Max Delay (ns): 67.251`
1242
1243
1244			`====================================================================================`
1245			`Compile report:`
1246			`===============`
1247
1248			`CORE Used: 5014`
1249			`Core Information:`
1250
1251			`Type \| Instances \| Core tiles`
1252			`--------\|--------------\|-----------`
1253			`COMB \| 4348 \| 4348`
1254			`SEQ \| 666 \| 666`
1255
1256
1257			`====================================================================================`
1258			`# SYNTHESIS DONE`
1259			`#####################################################################################`
1260
1261			`#####################################################################################`
1262			`# START SYNTHESIS`
1263			`#====================================================================================`
1264			`# ProASIC3 (A3P1000), speedgrade: -1`
1265			`#====================================================================================`
1266			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1267			`# 12 10 1 1 0 0 0`
1268			`#====================================================================================`
1269
1270
1271			`Clock Domain: dco_clk`
1272			`Period (ns): 54.338`
1273			`Frequency (MHz): 18.403`
1274			`Required Period (ns): 40.000`
1275			`Required Frequency (MHz): 25.000`
1276			`External Setup (ns): 51.572`
1277			`External Hold (ns): 0.643`
1278			`Min Clock-To-Out (ns): 2.515`
1279			`Max Clock-To-Out (ns): 58.728`
1280
1281			`Input to Output`
1282			`Min Delay (ns): 1.854`
1283			`Max Delay (ns): 55.962`
1284
1285
1286			`====================================================================================`
1287			`Compile report:`
1288			`===============`
1289
1290			`CORE Used: 5004`
1291			`Core Information:`
1292
1293			`Type \| Instances \| Core tiles`
1294			`--------\|--------------\|-----------`
1295			`COMB \| 4337 \| 4337`
1296			`SEQ \| 667 \| 667`
1297
1298
1299			`====================================================================================`
1300			`# SYNTHESIS DONE`
1301			`#####################################################################################`
1302
1303			`#####################################################################################`
1304			`# START SYNTHESIS`
1305			`#====================================================================================`
1306			`# ProASIC3 (A3P1000), speedgrade: -2`
1307			`#====================================================================================`
1308			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1309			`# 12 10 1 1 0 0 0`
1310			`#====================================================================================`
1311
1312
1313			`Clock Domain: dco_clk`
1314			`Period (ns): 47.071`
1315			`Frequency (MHz): 21.245`
1316			`Required Period (ns): 40.000`
1317			`Required Frequency (MHz): 25.000`
1318			`External Setup (ns): 47.553`
1319			`External Hold (ns): 0.528`
1320			`Min Clock-To-Out (ns): 2.730`
1321			`Max Clock-To-Out (ns): 50.373`
1322
1323			`Input to Output`
1324			`Min Delay (ns): 1.940`
1325			`Max Delay (ns): 50.855`
1326
1327
1328			`====================================================================================`
1329			`Compile report:`
1330			`===============`
1331
1332			`CORE Used: 5002`
1333			`Core Information:`
1334
1335			`Type \| Instances \| Core tiles`
1336			`--------\|--------------\|-----------`
1337			`COMB \| 4336 \| 4336`
1338			`SEQ \| 666 \| 666`
1339
1340
1341			`====================================================================================`
1342			`# SYNTHESIS DONE`
1343			`#####################################################################################`
1344
1345			`#####################################################################################`
1346			`# START SYNTHESIS`
1347			`#====================================================================================`
1348			`# Fusion (AFS1500), speedgrade: Std`
1349			`#====================================================================================`
1350			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1351			`# 12 10 1 1 0 0 0`
1352			`#====================================================================================`
1353
1354
1355			`Clock Domain: dco_clk`
1356			`Period (ns): 64.110`
1357			`Frequency (MHz): 15.598`
1358			`Required Period (ns): 40.000`
1359			`Required Frequency (MHz): 25.000`
1360			`External Setup (ns): 62.268`
1361			`External Hold (ns): 0.000`
1362			`Min Clock-To-Out (ns): 0.000`
1363			`Max Clock-To-Out (ns): 75.575`
1364
1365			`Input to Output`
1366			`Min Delay (ns): 0.000`
1367			`Max Delay (ns): 73.733`
1368
1369
1370			`====================================================================================`
1371			`Compile report:`
1372			`===============`
1373
1374			`CORE Used: 5014`
1375			`Core Information:`
1376
1377			`Type \| Instances \| Core tiles`
1378			`--------\|--------------\|-----------`
1379			`COMB \| 4348 \| 4348`
1380			`SEQ \| 666 \| 666`
1381
1382
1383			`====================================================================================`
1384			`# SYNTHESIS DONE`
1385			`#####################################################################################`
1386
1387			`#####################################################################################`
1388			`# START SYNTHESIS`
1389			`#====================================================================================`
1390			`# Fusion (AFS1500), speedgrade: -1`
1391			`#====================================================================================`
1392			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1393			`# 12 10 1 1 0 0 0`
1394			`#====================================================================================`
1395
1396
1397			`Clock Domain: dco_clk`
1398			`Period (ns): 55.995`
1399			`Frequency (MHz): 17.859`
1400			`Required Period (ns): 40.000`
1401			`Required Frequency (MHz): 25.000`
1402			`External Setup (ns): 53.992`
1403			`External Hold (ns): 0.998`
1404			`Min Clock-To-Out (ns): 2.999`
1405			`Max Clock-To-Out (ns): 62.056`
1406
1407			`Input to Output`
1408			`Min Delay (ns): 2.211`
1409			`Max Delay (ns): 60.053`
1410
1411
1412			`====================================================================================`
1413			`Compile report:`
1414			`===============`
1415
1416			`CORE Used: 5004`
1417			`Core Information:`
1418
1419			`Type \| Instances \| Core tiles`
1420			`--------\|--------------\|-----------`
1421			`COMB \| 4337 \| 4337`
1422			`SEQ \| 667 \| 667`
1423
1424
1425			`====================================================================================`
1426			`# SYNTHESIS DONE`
1427			`#####################################################################################`
1428
1429			`#####################################################################################`
1430			`# START SYNTHESIS`
1431			`#====================================================================================`
1432			`# Fusion (AFS1500), speedgrade: -2`
1433			`#====================================================================================`
1434			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1435			`# 12 10 1 1 0 0 0`
1436			`#====================================================================================`
1437
1438
1439			`Clock Domain: dco_clk`
1440			`Period (ns): 49.346`
1441			`Frequency (MHz): 20.265`
1442			`Required Period (ns): 40.000`
1443			`Required Frequency (MHz): 25.000`
1444			`External Setup (ns): 46.472`
1445			`External Hold (ns): 1.023`
1446			`Min Clock-To-Out (ns): 2.997`
1447			`Max Clock-To-Out (ns): 52.969`
1448
1449			`Input to Output`
1450			`Min Delay (ns): 2.297`
1451			`Max Delay (ns): 53.522`
1452
1453
1454			`====================================================================================`
1455			`Compile report:`
1456			`===============`
1457
1458			`CORE Used: 5002`
1459			`Core Information:`
1460
1461			`Type \| Instances \| Core tiles`
1462			`--------\|--------------\|-----------`
1463			`COMB \| 4336 \| 4336`
1464			`SEQ \| 666 \| 666`
1465
1466
1467			`====================================================================================`
1468			`# SYNTHESIS DONE`
1469			`#####################################################################################`
1470
1471			`#####################################################################################`
1472			`# START SYNTHESIS`
1473			`#====================================================================================`
1474			`# IGLOOE (AGLE600V5), speedgrade: Std`
1475			`#====================================================================================`
1476			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1477			`# 12 10 1 1 0 0 0`
1478			`#====================================================================================`
1479
1480
1481			`Clock Domain: dco_clk`
1482			`Period (ns): 72.222`
1483			`Frequency (MHz): 13.846`
1484			`Required Period (ns): 40.000`
1485			`Required Frequency (MHz): 25.000`
1486			`External Setup (ns): 66.967`
1487			`External Hold (ns): 0.000`
1488			`Min Clock-To-Out (ns): 0.000`
1489			`Max Clock-To-Out (ns): 79.167`
1490
1491			`Input to Output`
1492			`Min Delay (ns): 0.000`
1493			`Max Delay (ns): 73.912`
1494
1495
1496			`====================================================================================`
1497			`Compile report:`
1498			`===============`
1499
1500			`CORE Used: 5016`
1501			`Core Information:`
1502
1503			`Type \| Instances \| Core tiles`
1504			`--------\|--------------\|-----------`
1505			`COMB \| 4350 \| 4350`
1506			`SEQ \| 666 \| 666`
1507
1508
1509			`====================================================================================`
1510			`# SYNTHESIS DONE`
1511			`#####################################################################################`
1512
1513			`#####################################################################################`
1514			`# START SYNTHESIS`
1515			`#====================================================================================`
1516			`# ProASIC3E (A3PE1500), speedgrade: Std`
1517			`#====================================================================================`
1518			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1519			`# 12 10 1 1 1 0 0`
1520			`#====================================================================================`
1521
1522
1523			`Clock Domain: dco_clk`
1524			`Period (ns): 60.040`
1525			`Frequency (MHz): 16.656`
1526			`Required Period (ns): 40.000`
1527			`Required Frequency (MHz): 25.000`
1528			`External Setup (ns): 56.383`
1529			`External Hold (ns): 0.000`
1530			`Min Clock-To-Out (ns): 0.000`
1531			`Max Clock-To-Out (ns): 67.070`
1532
1533			`Input to Output`
1534			`Min Delay (ns): 0.000`
1535			`Max Delay (ns): 63.561`
1536
1537
1538			`====================================================================================`
1539			`Compile report:`
1540			`===============`
1541
1542			`CORE Used: 5263`
1543			`Core Information:`
1544
1545			`Type \| Instances \| Core tiles`
1546			`--------\|--------------\|-----------`
1547			`COMB \| 4554 \| 4554`
1548			`SEQ \| 709 \| 709`
1549
1550
1551			`====================================================================================`
1552			`# SYNTHESIS DONE`
1553			`#####################################################################################`
1554
1555			`#####################################################################################`
1556			`# START SYNTHESIS`
1557			`#====================================================================================`
1558			`# ProASIC3E (A3PE1500), speedgrade: -1`
1559			`#====================================================================================`
1560			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1561			`# 12 10 1 1 1 0 0`
1562			`#====================================================================================`
1563
1564
1565			`Clock Domain: dco_clk`
1566			`Period (ns): 52.542`
1567			`Frequency (MHz): 19.032`
1568			`Required Period (ns): 40.000`
1569			`Required Frequency (MHz): 25.000`
1570			`External Setup (ns): 51.724`
1571			`External Hold (ns): 0.390`
1572			`Min Clock-To-Out (ns): 3.241`
1573			`Max Clock-To-Out (ns): 60.476`
1574
1575			`Input to Output`
1576			`Min Delay (ns): 2.048`
1577			`Max Delay (ns): 59.658`
1578
1579
1580			`====================================================================================`
1581			`Compile report:`
1582			`===============`
1583
1584			`CORE Used: 5246`
1585			`Core Information:`
1586
1587			`Type \| Instances \| Core tiles`
1588			`--------\|--------------\|-----------`
1589			`COMB \| 4538 \| 4538`
1590			`SEQ \| 708 \| 708`
1591
1592
1593			`====================================================================================`
1594			`# SYNTHESIS DONE`
1595			`#####################################################################################`
1596
1597			`#####################################################################################`
1598			`# START SYNTHESIS`
1599			`#====================================================================================`
1600			`# ProASIC3E (A3PE1500), speedgrade: -2`
1601			`#====================================================================================`
1602			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1603			`# 12 10 1 1 1 0 0`
1604			`#====================================================================================`
1605
1606
1607			`Clock Domain: dco_clk`
1608			`Period (ns): 41.647`
1609			`Frequency (MHz): 24.011`
1610			`Required Period (ns): 40.000`
1611			`Required Frequency (MHz): 25.000`
1612			`External Setup (ns): 40.940`
1613			`External Hold (ns): 0.393`
1614			`Min Clock-To-Out (ns): 3.373`
1615			`Max Clock-To-Out (ns): 49.023`
1616
1617			`Input to Output`
1618			`Min Delay (ns): 2.162`
1619			`Max Delay (ns): 48.316`
1620
1621
1622			`====================================================================================`
1623			`Compile report:`
1624			`===============`
1625
1626			`CORE Used: 5210`
1627			`Core Information:`
1628
1629			`Type \| Instances \| Core tiles`
1630			`--------\|--------------\|-----------`
1631			`COMB \| 4503 \| 4503`
1632			`SEQ \| 707 \| 707`
1633
1634
1635			`====================================================================================`
1636			`# SYNTHESIS DONE`
1637			`#####################################################################################`
1638
1639			`#####################################################################################`
1640			`# START SYNTHESIS`
1641			`#====================================================================================`
1642			`# ProASIC3L (A3P1000L), speedgrade: Std`
1643			`#====================================================================================`
1644			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1645			`# 12 10 1 1 1 0 0`
1646			`#====================================================================================`
1647
1648
1649			`Clock Domain: dco_clk`
1650			`Period (ns): 67.866`
1651			`Frequency (MHz): 14.735`
1652			`Required Period (ns): 40.000`
1653			`Required Frequency (MHz): 25.000`
1654			`External Setup (ns): 67.341`
1655			`External Hold (ns): 0.633`
1656			`Min Clock-To-Out (ns): 6.638`
1657			`Max Clock-To-Out (ns): 77.183`
1658
1659			`Input to Output`
1660			`Min Delay (ns): 4.759`
1661			`Max Delay (ns): 76.658`
1662
1663
1664			`====================================================================================`
1665			`Compile report:`
1666			`===============`
1667
1668			`CORE Used: 5183`
1669			`Core Information:`
1670
1671			`Type \| Instances \| Core tiles`
1672			`--------\|--------------\|-----------`
1673			`COMB \| 4474 \| 4474`
1674			`SEQ \| 709 \| 709`
1675
1676
1677			`====================================================================================`
1678			`# SYNTHESIS DONE`
1679			`#####################################################################################`
1680
1681			`#####################################################################################`
1682			`# START SYNTHESIS`
1683			`#====================================================================================`
1684			`# ProASIC3L (A3P1000L), speedgrade: -1`
1685			`#====================================================================================`
1686			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1687			`# 12 10 1 1 1 0 0`
1688			`#====================================================================================`
1689
1690
1691			`Clock Domain: dco_clk`
1692			`Period (ns): 58.347`
1693			`Frequency (MHz): 17.139`
1694			`Required Period (ns): 40.000`
1695			`Required Frequency (MHz): 25.000`
1696			`External Setup (ns): 53.616`
1697			`External Hold (ns): 0.484`
1698			`Min Clock-To-Out (ns): 6.148`
1699			`Max Clock-To-Out (ns): 67.071`
1700
1701			`Input to Output`
1702			`Min Delay (ns): 4.038`
1703			`Max Delay (ns): 62.340`
1704
1705
1706			`====================================================================================`
1707			`Compile report:`
1708			`===============`
1709
1710			`CORE Used: 5174`
1711			`Core Information:`
1712
1713			`Type \| Instances \| Core tiles`
1714			`--------\|--------------\|-----------`
1715			`COMB \| 4466 \| 4466`
1716			`SEQ \| 708 \| 708`
1717
1718
1719			`====================================================================================`
1720			`# SYNTHESIS DONE`
1721			`#####################################################################################`
1722
1723			`#####################################################################################`
1724			`# START SYNTHESIS`
1725			`#====================================================================================`
1726			`# ProASIC3 (A3P1000), speedgrade: Std`
1727			`#====================================================================================`
1728			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1729			`# 12 10 1 1 1 0 0`
1730			`#====================================================================================`
1731
1732
1733			`Clock Domain: dco_clk`
1734			`Period (ns): 62.489`
1735			`Frequency (MHz): 16.003`
1736			`Required Period (ns): 40.000`
1737			`Required Frequency (MHz): 25.000`
1738			`External Setup (ns): 59.682`
1739			`External Hold (ns): 0.000`
1740			`Min Clock-To-Out (ns): 0.000`
1741			`Max Clock-To-Out (ns): 71.122`
1742
1743			`Input to Output`
1744			`Min Delay (ns): 0.000`
1745			`Max Delay (ns): 68.508`
1746
1747
1748			`====================================================================================`
1749			`Compile report:`
1750			`===============`
1751
1752			`CORE Used: 5263`
1753			`Core Information:`
1754
1755			`Type \| Instances \| Core tiles`
1756			`--------\|--------------\|-----------`
1757			`COMB \| 4554 \| 4554`
1758			`SEQ \| 709 \| 709`
1759
1760
1761			`====================================================================================`
1762			`# SYNTHESIS DONE`
1763			`#####################################################################################`
1764
1765			`#####################################################################################`
1766			`# START SYNTHESIS`
1767			`#====================================================================================`
1768			`# ProASIC3 (A3P1000), speedgrade: -1`
1769			`#====================================================================================`
1770			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1771			`# 12 10 1 1 1 0 0`
1772			`#====================================================================================`
1773
1774
1775			`Clock Domain: dco_clk`
1776			`Period (ns): 52.780`
1777			`Frequency (MHz): 18.947`
1778			`Required Period (ns): 40.000`
1779			`Required Frequency (MHz): 25.000`
1780			`External Setup (ns): 51.636`
1781			`External Hold (ns): 0.644`
1782			`Min Clock-To-Out (ns): 2.870`
1783			`Max Clock-To-Out (ns): 60.087`
1784
1785			`Input to Output`
1786			`Min Delay (ns): 1.901`
1787			`Max Delay (ns): 58.974`
1788
1789
1790			`====================================================================================`
1791			`Compile report:`
1792			`===============`
1793
1794			`CORE Used: 5246`
1795			`Core Information:`
1796
1797			`Type \| Instances \| Core tiles`
1798			`--------\|--------------\|-----------`
1799			`COMB \| 4538 \| 4538`
1800			`SEQ \| 708 \| 708`
1801
1802
1803			`====================================================================================`
1804			`# SYNTHESIS DONE`
1805			`#####################################################################################`
1806
1807			`#####################################################################################`
1808			`# START SYNTHESIS`
1809			`#====================================================================================`
1810			`# ProASIC3 (A3P1000), speedgrade: -2`
1811			`#====================================================================================`
1812			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1813			`# 12 10 1 1 1 0 0`
1814			`#====================================================================================`
1815
1816
1817			`Clock Domain: dco_clk`
1818			`Period (ns): 44.316`
1819			`Frequency (MHz): 22.565`
1820			`Required Period (ns): 40.000`
1821			`Required Frequency (MHz): 25.000`
1822			`External Setup (ns): 42.479`
1823			`External Hold (ns): 0.407`
1824			`Min Clock-To-Out (ns): 2.509`
1825			`Max Clock-To-Out (ns): 49.750`
1826
1827			`Input to Output`
1828			`Min Delay (ns): 1.888`
1829			`Max Delay (ns): 47.909`
1830
1831
1832			`====================================================================================`
1833			`Compile report:`
1834			`===============`
1835
1836			`CORE Used: 5210`
1837			`Core Information:`
1838
1839			`Type \| Instances \| Core tiles`
1840			`--------\|--------------\|-----------`
1841			`COMB \| 4503 \| 4503`
1842			`SEQ \| 707 \| 707`
1843
1844
1845			`====================================================================================`
1846			`# SYNTHESIS DONE`
1847			`#####################################################################################`
1848
1849			`#####################################################################################`
1850			`# START SYNTHESIS`
1851			`#====================================================================================`
1852			`# Fusion (AFS1500), speedgrade: Std`
1853			`#====================================================================================`
1854			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1855			`# 12 10 1 1 1 0 0`
1856			`#====================================================================================`
1857
1858
1859			`Clock Domain: dco_clk`
1860			`Period (ns): 64.038`
1861			`Frequency (MHz): 15.616`
1862			`Required Period (ns): 40.000`
1863			`Required Frequency (MHz): 25.000`
1864			`External Setup (ns): 64.165`
1865			`External Hold (ns): 0.000`
1866			`Min Clock-To-Out (ns): 0.000`
1867			`Max Clock-To-Out (ns): 68.333`
1868
1869			`Input to Output`
1870			`Min Delay (ns): 0.000`
1871			`Max Delay (ns): 69.112`
1872
1873
1874			`====================================================================================`
1875			`Compile report:`
1876			`===============`
1877
1878			`CORE Used: 5263`
1879			`Core Information:`
1880
1881			`Type \| Instances \| Core tiles`
1882			`--------\|--------------\|-----------`
1883			`COMB \| 4554 \| 4554`
1884			`SEQ \| 709 \| 709`
1885
1886
1887			`====================================================================================`
1888			`# SYNTHESIS DONE`
1889			`#####################################################################################`
1890
1891			`#####################################################################################`
1892			`# START SYNTHESIS`
1893			`#====================================================================================`
1894			`# Fusion (AFS1500), speedgrade: -1`
1895			`#====================================================================================`
1896			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1897			`# 12 10 1 1 1 0 0`
1898			`#====================================================================================`
1899
1900
1901			`Clock Domain: dco_clk`
1902			`Period (ns): 56.151`
1903			`Frequency (MHz): 17.809`
1904			`Required Period (ns): 40.000`
1905			`Required Frequency (MHz): 25.000`
1906			`External Setup (ns): 54.045`
1907			`External Hold (ns): 0.671`
1908			`Min Clock-To-Out (ns): 2.988`
1909			`Max Clock-To-Out (ns): 65.864`
1910
1911			`Input to Output`
1912			`Min Delay (ns): 2.209`
1913			`Max Delay (ns): 63.758`
1914
1915
1916			`====================================================================================`
1917			`Compile report:`
1918			`===============`
1919
1920			`CORE Used: 5246`
1921			`Core Information:`
1922
1923			`Type \| Instances \| Core tiles`
1924			`--------\|--------------\|-----------`
1925			`COMB \| 4538 \| 4538`
1926			`SEQ \| 708 \| 708`
1927
1928
1929			`====================================================================================`
1930			`# SYNTHESIS DONE`
1931			`#####################################################################################`
1932
1933			`#####################################################################################`
1934			`# START SYNTHESIS`
1935			`#====================================================================================`
1936			`# Fusion (AFS1500), speedgrade: -2`
1937			`#====================================================================================`
1938			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1939			`# 12 10 1 1 1 0 0`
1940			`#====================================================================================`
1941
1942
1943			`Clock Domain: dco_clk`
1944			`Period (ns): 46.560`
1945			`Frequency (MHz): 21.478`
1946			`Required Period (ns): 40.000`
1947			`Required Frequency (MHz): 25.000`
1948			`External Setup (ns): 48.940`
1949			`External Hold (ns): 0.720`
1950			`Min Clock-To-Out (ns): 2.906`
1951			`Max Clock-To-Out (ns): 56.528`
1952
1953			`Input to Output`
1954			`Min Delay (ns): 2.260`
1955			`Max Delay (ns): 58.908`
1956
1957
1958			`====================================================================================`
1959			`Compile report:`
1960			`===============`
1961
1962			`CORE Used: 5210`
1963			`Core Information:`
1964
1965			`Type \| Instances \| Core tiles`
1966			`--------\|--------------\|-----------`
1967			`COMB \| 4503 \| 4503`
1968			`SEQ \| 707 \| 707`
1969
1970
1971			`====================================================================================`
1972			`# SYNTHESIS DONE`
1973			`#####################################################################################`
1974
1975			`#####################################################################################`
1976			`# START SYNTHESIS`
1977			`#====================================================================================`
1978			`# IGLOOE (AGLE600V5), speedgrade: Std`
1979			`#====================================================================================`
1980			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
1981			`# 12 10 1 1 1 0 0`
1982			`#====================================================================================`
1983
1984
1985			`Clock Domain: dco_clk`
1986			`Period (ns): 70.004`
1987			`Frequency (MHz): 14.285`
1988			`Required Period (ns): 40.000`
1989			`Required Frequency (MHz): 25.000`
1990			`External Setup (ns): 67.782`
1991			`External Hold (ns): 0.000`
1992			`Min Clock-To-Out (ns): 0.000`
1993			`Max Clock-To-Out (ns): 76.206`
1994
1995			`Input to Output`
1996			`Min Delay (ns): 0.000`
1997			`Max Delay (ns): 73.984`
1998
1999
2000			`====================================================================================`
2001			`Compile report:`
2002			`===============`
2003
2004			`CORE Used: 5214`
2005			`Core Information:`
2006
2007			`Type \| Instances \| Core tiles`
2008			`--------\|--------------\|-----------`
2009			`COMB \| 4505 \| 4505`
2010			`SEQ \| 709 \| 709`
2011
2012
2013			`====================================================================================`
2014			`# SYNTHESIS DONE`
2015			`#####################################################################################`
2016
2017			`#####################################################################################`
2018			`# START SYNTHESIS`
2019			`#====================================================================================`
2020			`# ProASIC3E (A3PE1500), speedgrade: Std`
2021			`#====================================================================================`
2022			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2023			`# 12 10 1 1 1 1 0`
2024			`#====================================================================================`
2025
2026
2027			`Clock Domain: dco_clk`
2028			`Period (ns): 67.175`
2029			`Frequency (MHz): 14.886`
2030			`Required Period (ns): 40.000`
2031			`Required Frequency (MHz): 25.000`
2032			`External Setup (ns): 66.999`
2033			`External Hold (ns): 0.000`
2034			`Min Clock-To-Out (ns): 0.000`
2035			`Max Clock-To-Out (ns): 74.967`
2036
2037			`Input to Output`
2038			`Min Delay (ns): 0.000`
2039			`Max Delay (ns): 74.791`
2040
2041
2042			`====================================================================================`
2043			`Compile report:`
2044			`===============`
2045
2046			`CORE Used: 5571`
2047			`Core Information:`
2048
2049			`Type \| Instances \| Core tiles`
2050			`--------\|--------------\|-----------`
2051			`COMB \| 4821 \| 4821`
2052			`SEQ \| 750 \| 750`
2053
2054
2055			`====================================================================================`
2056			`# SYNTHESIS DONE`
2057			`#####################################################################################`
2058
2059			`#####################################################################################`
2060			`# START SYNTHESIS`
2061			`#====================================================================================`
2062			`# ProASIC3E (A3PE1500), speedgrade: -1`
2063			`#====================================================================================`
2064			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2065			`# 12 10 1 1 1 1 0`
2066			`#====================================================================================`
2067
2068
2069			`Clock Domain: dco_clk`
2070			`Period (ns): 52.406`
2071			`Frequency (MHz): 19.082`
2072			`Required Period (ns): 40.000`
2073			`Required Frequency (MHz): 25.000`
2074			`External Setup (ns): 49.356`
2075			`External Hold (ns): 0.399`
2076			`Min Clock-To-Out (ns): 3.024`
2077			`Max Clock-To-Out (ns): 58.778`
2078
2079			`Input to Output`
2080			`Min Delay (ns): 2.043`
2081			`Max Delay (ns): 57.661`
2082
2083
2084			`====================================================================================`
2085			`Compile report:`
2086			`===============`
2087
2088			`CORE Used: 5345`
2089			`Core Information:`
2090
2091			`Type \| Instances \| Core tiles`
2092			`--------\|--------------\|-----------`
2093			`COMB \| 4595 \| 4595`
2094			`SEQ \| 750 \| 750`
2095
2096
2097			`====================================================================================`
2098			`# SYNTHESIS DONE`
2099			`#####################################################################################`
2100
2101			`#####################################################################################`
2102			`# START SYNTHESIS`
2103			`#====================================================================================`
2104			`# ProASIC3E (A3PE1500), speedgrade: -2`
2105			`#====================================================================================`
2106			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2107			`# 12 10 1 1 1 1 0`
2108			`#====================================================================================`
2109
2110
2111			`Clock Domain: dco_clk`
2112			`Period (ns): 43.762`
2113			`Frequency (MHz): 22.851`
2114			`Required Period (ns): 40.000`
2115			`Required Frequency (MHz): 25.000`
2116			`External Setup (ns): 42.914`
2117			`External Hold (ns): 0.453`
2118			`Min Clock-To-Out (ns): 2.938`
2119			`Max Clock-To-Out (ns): 52.039`
2120
2121			`Input to Output`
2122			`Min Delay (ns): 2.117`
2123			`Max Delay (ns): 50.921`
2124
2125
2126			`====================================================================================`
2127			`Compile report:`
2128			`===============`
2129
2130			`CORE Used: 5446`
2131			`Core Information:`
2132
2133			`Type \| Instances \| Core tiles`
2134			`--------\|--------------\|-----------`
2135			`COMB \| 4696 \| 4696`
2136			`SEQ \| 750 \| 750`
2137
2138
2139			`====================================================================================`
2140			`# SYNTHESIS DONE`
2141			`#####################################################################################`
2142
2143			`#####################################################################################`
2144			`# START SYNTHESIS`
2145			`#====================================================================================`
2146			`# ProASIC3L (A3P1000L), speedgrade: Std`
2147			`#====================================================================================`
2148			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2149			`# 12 10 1 1 1 1 0`
2150			`#====================================================================================`
2151
2152
2153			`Clock Domain: dco_clk`
2154			`Period (ns): 70.659`
2155			`Frequency (MHz): 14.152`
2156			`Required Period (ns): 40.000`
2157			`Required Frequency (MHz): 25.000`
2158			`External Setup (ns): 69.361`
2159			`External Hold (ns): 1.104`
2160			`Min Clock-To-Out (ns): 6.284`
2161			`Max Clock-To-Out (ns): 79.935`
2162
2163			`Input to Output`
2164			`Min Delay (ns): 4.970`
2165			`Max Delay (ns): 78.637`
2166
2167
2168			`====================================================================================`
2169			`Compile report:`
2170			`===============`
2171
2172			`CORE Used: 5453`
2173			`Core Information:`
2174
2175			`Type \| Instances \| Core tiles`
2176			`--------\|--------------\|-----------`
2177			`COMB \| 4703 \| 4703`
2178			`SEQ \| 750 \| 750`
2179
2180
2181			`====================================================================================`
2182			`# SYNTHESIS DONE`
2183			`#####################################################################################`
2184
2185			`#####################################################################################`
2186			`# START SYNTHESIS`
2187			`#====================================================================================`
2188			`# ProASIC3L (A3P1000L), speedgrade: -1`
2189			`#====================================================================================`
2190			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2191			`# 12 10 1 1 1 1 0`
2192			`#====================================================================================`
2193
2194
2195			`Clock Domain: dco_clk`
2196			`Period (ns): 56.521`
2197			`Frequency (MHz): 17.693`
2198			`Required Period (ns): 40.000`
2199			`Required Frequency (MHz): 25.000`
2200			`External Setup (ns): 53.598`
2201			`External Hold (ns): 0.935`
2202			`Min Clock-To-Out (ns): 5.720`
2203			`Max Clock-To-Out (ns): 64.497`
2204
2205			`Input to Output`
2206			`Min Delay (ns): 4.213`
2207			`Max Delay (ns): 61.316`
2208
2209
2210			`====================================================================================`
2211			`Compile report:`
2212			`===============`
2213
2214			`CORE Used: 5418`
2215			`Core Information:`
2216
2217			`Type \| Instances \| Core tiles`
2218			`--------\|--------------\|-----------`
2219			`COMB \| 4668 \| 4668`
2220			`SEQ \| 750 \| 750`
2221
2222
2223			`====================================================================================`
2224			`# SYNTHESIS DONE`
2225			`#####################################################################################`
2226
2227			`#####################################################################################`
2228			`# START SYNTHESIS`
2229			`#====================================================================================`
2230			`# ProASIC3 (A3P1000), speedgrade: Std`
2231			`#====================================================================================`
2232			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2233			`# 12 10 1 1 1 1 0`
2234			`#====================================================================================`
2235
2236
2237			`Clock Domain: dco_clk`
2238			`Period (ns): 68.371`
2239			`Frequency (MHz): 14.626`
2240			`Required Period (ns): 40.000`
2241			`Required Frequency (MHz): 25.000`
2242			`External Setup (ns): 65.231`
2243			`External Hold (ns): 0.000`
2244			`Min Clock-To-Out (ns): 0.000`
2245			`Max Clock-To-Out (ns): 75.295`
2246
2247			`Input to Output`
2248			`Min Delay (ns): 0.000`
2249			`Max Delay (ns): 72.138`
2250
2251
2252			`====================================================================================`
2253			`Compile report:`
2254			`===============`
2255
2256			`CORE Used: 5571`
2257			`Core Information:`
2258
2259			`Type \| Instances \| Core tiles`
2260			`--------\|--------------\|-----------`
2261			`COMB \| 4821 \| 4821`
2262			`SEQ \| 750 \| 750`
2263
2264
2265			`====================================================================================`
2266			`# SYNTHESIS DONE`
2267			`#####################################################################################`
2268
2269			`#####################################################################################`
2270			`# START SYNTHESIS`
2271			`#====================================================================================`
2272			`# ProASIC3 (A3P1000), speedgrade: -1`
2273			`#====================================================================================`
2274			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2275			`# 12 10 1 1 1 1 0`
2276			`#====================================================================================`
2277
2278
2279			`Clock Domain: dco_clk`
2280			`Period (ns): 58.370`
2281			`Frequency (MHz): 17.132`
2282			`Required Period (ns): 40.000`
2283			`Required Frequency (MHz): 25.000`
2284			`External Setup (ns): 51.910`
2285			`External Hold (ns): 0.260`
2286			`Min Clock-To-Out (ns): 2.311`
2287			`Max Clock-To-Out (ns): 60.896`
2288
2289			`Input to Output`
2290			`Min Delay (ns): 1.902`
2291			`Max Delay (ns): 59.108`
2292
2293
2294			`====================================================================================`
2295			`Compile report:`
2296			`===============`
2297
2298			`CORE Used: 5345`
2299			`Core Information:`
2300
2301			`Type \| Instances \| Core tiles`
2302			`--------\|--------------\|-----------`
2303			`COMB \| 4595 \| 4595`
2304			`SEQ \| 750 \| 750`
2305
2306
2307			`====================================================================================`
2308			`# SYNTHESIS DONE`
2309			`#####################################################################################`
2310
2311			`#####################################################################################`
2312			`# START SYNTHESIS`
2313			`#====================================================================================`
2314			`# ProASIC3 (A3P1000), speedgrade: -2`
2315			`#====================================================================================`
2316			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2317			`# 12 10 1 1 1 1 0`
2318			`#====================================================================================`
2319
2320
2321			`Clock Domain: dco_clk`
2322			`Period (ns): 42.983`
2323			`Frequency (MHz): 23.265`
2324			`Required Period (ns): 40.000`
2325			`Required Frequency (MHz): 25.000`
2326			`External Setup (ns): 41.687`
2327			`External Hold (ns): 0.668`
2328			`Min Clock-To-Out (ns): 2.665`
2329			`Max Clock-To-Out (ns): 50.200`
2330
2331			`Input to Output`
2332			`Min Delay (ns): 1.890`
2333			`Max Delay (ns): 48.904`
2334
2335
2336			`====================================================================================`
2337			`Compile report:`
2338			`===============`
2339
2340			`CORE Used: 5446`
2341			`Core Information:`
2342
2343			`Type \| Instances \| Core tiles`
2344			`--------\|--------------\|-----------`
2345			`COMB \| 4696 \| 4696`
2346			`SEQ \| 750 \| 750`
2347
2348
2349			`====================================================================================`
2350			`# SYNTHESIS DONE`
2351			`#####################################################################################`
2352
2353			`#####################################################################################`
2354			`# START SYNTHESIS`
2355			`#====================================================================================`
2356			`# Fusion (AFS1500), speedgrade: Std`
2357			`#====================================================================================`
2358			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2359			`# 12 10 1 1 1 1 0`
2360			`#====================================================================================`
2361
2362
2363			`Clock Domain: dco_clk`
2364			`Period (ns): 65.791`
2365			`Frequency (MHz): 15.200`
2366			`Required Period (ns): 40.000`
2367			`Required Frequency (MHz): 25.000`
2368			`External Setup (ns): 65.369`
2369			`External Hold (ns): 0.000`
2370			`Min Clock-To-Out (ns): 0.000`
2371			`Max Clock-To-Out (ns): 77.776`
2372
2373			`Input to Output`
2374			`Min Delay (ns): 0.000`
2375			`Max Delay (ns): 77.354`
2376
2377
2378			`====================================================================================`
2379			`Compile report:`
2380			`===============`
2381
2382			`CORE Used: 5571`
2383			`Core Information:`
2384
2385			`Type \| Instances \| Core tiles`
2386			`--------\|--------------\|-----------`
2387			`COMB \| 4821 \| 4821`
2388			`SEQ \| 750 \| 750`
2389
2390
2391			`====================================================================================`
2392			`# SYNTHESIS DONE`
2393			`#####################################################################################`
2394
2395			`#####################################################################################`
2396			`# START SYNTHESIS`
2397			`#====================================================================================`
2398			`# Fusion (AFS1500), speedgrade: -1`
2399			`#====================================================================================`
2400			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2401			`# 12 10 1 1 1 1 0`
2402			`#====================================================================================`
2403
2404
2405			`Clock Domain: dco_clk`
2406			`Period (ns): 53.504`
2407			`Frequency (MHz): 18.690`
2408			`Required Period (ns): 40.000`
2409			`Required Frequency (MHz): 25.000`
2410			`External Setup (ns): 51.043`
2411			`External Hold (ns): 1.020`
2412			`Min Clock-To-Out (ns): 2.932`
2413			`Max Clock-To-Out (ns): 63.905`
2414
2415			`Input to Output`
2416			`Min Delay (ns): 2.211`
2417			`Max Delay (ns): 61.444`
2418
2419
2420			`====================================================================================`
2421			`Compile report:`
2422			`===============`
2423
2424			`CORE Used: 5345`
2425			`Core Information:`
2426
2427			`Type \| Instances \| Core tiles`
2428			`--------\|--------------\|-----------`
2429			`COMB \| 4595 \| 4595`
2430			`SEQ \| 750 \| 750`
2431
2432
2433			`====================================================================================`
2434			`# SYNTHESIS DONE`
2435			`#####################################################################################`
2436
2437			`#####################################################################################`
2438			`# START SYNTHESIS`
2439			`#====================================================================================`
2440			`# Fusion (AFS1500), speedgrade: -2`
2441			`#====================================================================================`
2442			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2443			`# 12 10 1 1 1 1 0`
2444			`#====================================================================================`
2445
2446
2447			`Clock Domain: dco_clk`
2448			`Period (ns): 46.762`
2449			`Frequency (MHz): 21.385`
2450			`Required Period (ns): 40.000`
2451			`Required Frequency (MHz): 25.000`
2452			`External Setup (ns): 45.886`
2453			`External Hold (ns): 1.039`
2454			`Min Clock-To-Out (ns): 2.882`
2455			`Max Clock-To-Out (ns): 54.605`
2456
2457			`Input to Output`
2458			`Min Delay (ns): 2.258`
2459			`Max Delay (ns): 53.727`
2460
2461
2462			`====================================================================================`
2463			`Compile report:`
2464			`===============`
2465
2466			`CORE Used: 5446`
2467			`Core Information:`
2468
2469			`Type \| Instances \| Core tiles`
2470			`--------\|--------------\|-----------`
2471			`COMB \| 4696 \| 4696`
2472			`SEQ \| 750 \| 750`
2473
2474
2475			`====================================================================================`
2476			`# SYNTHESIS DONE`
2477			`#####################################################################################`
2478
2479			`#####################################################################################`
2480			`# START SYNTHESIS`
2481			`#====================================================================================`
2482			`# IGLOOE (AGLE600V5), speedgrade: Std`
2483			`#====================================================================================`
2484			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2485			`# 12 10 1 1 1 1 0`
2486			`#====================================================================================`
2487
2488
2489			`Clock Domain: dco_clk`
2490			`Period (ns): 69.277`
2491			`Frequency (MHz): 14.435`
2492			`Required Period (ns): 40.000`
2493			`Required Frequency (MHz): 25.000`
2494			`External Setup (ns): 65.839`
2495			`External Hold (ns): 0.000`
2496			`Min Clock-To-Out (ns): 0.000`
2497			`Max Clock-To-Out (ns): 77.535`
2498
2499			`Input to Output`
2500			`Min Delay (ns): 0.000`
2501			`Max Delay (ns): 73.236`
2502
2503
2504			`====================================================================================`
2505			`Compile report:`
2506			`===============`
2507
2508			`CORE Used: 5467`
2509			`Core Information:`
2510
2511			`Type \| Instances \| Core tiles`
2512			`--------\|--------------\|-----------`
2513			`COMB \| 4716 \| 4716`
2514			`SEQ \| 751 \| 751`
2515
2516
2517			`====================================================================================`
2518			`# SYNTHESIS DONE`
2519			`#####################################################################################`
2520
2521			`#####################################################################################`
2522			`# START SYNTHESIS`
2523			`#====================================================================================`
2524			`# ProASIC3E (A3PE1500), speedgrade: Std`
2525			`#====================================================================================`
2526			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2527			`# 12 10 1 1 1 1 1`
2528			`#====================================================================================`
2529
2530
2531			`Clock Domain: dco_clk`
2532			`Period (ns): 65.626`
2533			`Frequency (MHz): 15.238`
2534			`Required Period (ns): 40.000`
2535			`Required Frequency (MHz): 25.000`
2536			`External Setup (ns): 62.017`
2537			`External Hold (ns): 0.000`
2538			`Min Clock-To-Out (ns): 0.000`
2539			`Max Clock-To-Out (ns): 71.036`
2540
2541			`Input to Output`
2542			`Min Delay (ns): 0.000`
2543			`Max Delay (ns): 68.666`
2544
2545
2546			`====================================================================================`
2547			`Compile report:`
2548			`===============`
2549
2550			`CORE Used: 5747`
2551			`Core Information:`
2552
2553			`Type \| Instances \| Core tiles`
2554			`--------\|--------------\|-----------`
2555			`COMB \| 4954 \| 4954`
2556			`SEQ \| 793 \| 793`
2557
2558
2559			`====================================================================================`
2560			`# SYNTHESIS DONE`
2561			`#####################################################################################`
2562
2563			`#####################################################################################`
2564			`# START SYNTHESIS`
2565			`#====================================================================================`
2566			`# ProASIC3E (A3PE1500), speedgrade: -1`
2567			`#====================================================================================`
2568			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2569			`# 12 10 1 1 1 1 1`
2570			`#====================================================================================`
2571
2572
2573			`Clock Domain: dco_clk`
2574			`Period (ns): 54.672`
2575			`Frequency (MHz): 18.291`
2576			`Required Period (ns): 40.000`
2577			`Required Frequency (MHz): 25.000`
2578			`External Setup (ns): 49.764`
2579			`External Hold (ns): 0.328`
2580			`Min Clock-To-Out (ns): 3.161`
2581			`Max Clock-To-Out (ns): 61.785`
2582
2583			`Input to Output`
2584			`Min Delay (ns): 2.070`
2585			`Max Delay (ns): 56.877`
2586
2587
2588			`====================================================================================`
2589			`Compile report:`
2590			`===============`
2591
2592			`CORE Used: 5713`
2593			`Core Information:`
2594
2595			`Type \| Instances \| Core tiles`
2596			`--------\|--------------\|-----------`
2597			`COMB \| 4920 \| 4920`
2598			`SEQ \| 793 \| 793`
2599
2600
2601			`====================================================================================`
2602			`# SYNTHESIS DONE`
2603			`#####################################################################################`
2604
2605			`#####################################################################################`
2606			`# START SYNTHESIS`
2607			`#====================================================================================`
2608			`# ProASIC3E (A3PE1500), speedgrade: -2`
2609			`#====================================================================================`
2610			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2611			`# 12 10 1 1 1 1 1`
2612			`#====================================================================================`
2613
2614
2615			`Clock Domain: dco_clk`
2616			`Period (ns): 51.406`
2617			`Frequency (MHz): 19.453`
2618			`Required Period (ns): 40.000`
2619			`Required Frequency (MHz): 25.000`
2620			`External Setup (ns): 47.497`
2621			`External Hold (ns): 0.320`
2622			`Min Clock-To-Out (ns): 3.089`
2623			`Max Clock-To-Out (ns): 52.123`
2624
2625			`Input to Output`
2626			`Min Delay (ns): 2.089`
2627			`Max Delay (ns): 51.309`
2628
2629
2630			`====================================================================================`
2631			`Compile report:`
2632			`===============`
2633
2634			`CORE Used: 5625`
2635			`Core Information:`
2636
2637			`Type \| Instances \| Core tiles`
2638			`--------\|--------------\|-----------`
2639			`COMB \| 4833 \| 4833`
2640			`SEQ \| 792 \| 792`
2641
2642
2643			`====================================================================================`
2644			`# SYNTHESIS DONE`
2645			`#####################################################################################`
2646
2647			`#####################################################################################`
2648			`# START SYNTHESIS`
2649			`#====================================================================================`
2650			`# ProASIC3L (A3P1000L), speedgrade: Std`
2651			`#====================================================================================`
2652			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2653			`# 12 10 1 1 1 1 1`
2654			`#====================================================================================`
2655
2656
2657			`Clock Domain: dco_clk`
2658			`Period (ns): 71.166`
2659			`Frequency (MHz): 14.052`
2660			`Required Period (ns): 40.000`
2661			`Required Frequency (MHz): 25.000`
2662			`External Setup (ns): 65.631`
2663			`External Hold (ns): 1.104`
2664			`Min Clock-To-Out (ns): 5.982`
2665			`Max Clock-To-Out (ns): 81.369`
2666
2667			`Input to Output`
2668			`Min Delay (ns): 4.759`
2669			`Max Delay (ns): 75.834`
2670
2671
2672			`====================================================================================`
2673			`Compile report:`
2674			`===============`
2675
2676			`CORE Used: 5638`
2677			`Core Information:`
2678
2679			`Type \| Instances \| Core tiles`
2680			`--------\|--------------\|-----------`
2681			`COMB \| 4846 \| 4846`
2682			`SEQ \| 792 \| 792`
2683
2684
2685			`====================================================================================`
2686			`# SYNTHESIS DONE`
2687			`#####################################################################################`
2688
2689			`#####################################################################################`
2690			`# START SYNTHESIS`
2691			`#====================================================================================`
2692			`# ProASIC3L (A3P1000L), speedgrade: -1`
2693			`#====================================================================================`
2694			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2695			`# 12 10 1 1 1 1 1`
2696			`#====================================================================================`
2697
2698
2699			`Clock Domain: dco_clk`
2700			`Period (ns): 61.462`
2701			`Frequency (MHz): 16.270`
2702			`Required Period (ns): 40.000`
2703			`Required Frequency (MHz): 25.000`
2704			`External Setup (ns): 55.362`
2705			`External Hold (ns): 0.356`
2706			`Min Clock-To-Out (ns): 5.381`
2707			`Max Clock-To-Out (ns): 64.619`
2708
2709			`Input to Output`
2710			`Min Delay (ns): 4.213`
2711			`Max Delay (ns): 62.829`
2712
2713
2714			`====================================================================================`
2715			`Compile report:`
2716			`===============`
2717
2718			`CORE Used: 5706`
2719			`Core Information:`
2720
2721			`Type \| Instances \| Core tiles`
2722			`--------\|--------------\|-----------`
2723			`COMB \| 4913 \| 4913`
2724			`SEQ \| 793 \| 793`
2725
2726
2727			`====================================================================================`
2728			`# SYNTHESIS DONE`
2729			`#####################################################################################`
2730
2731			`#####################################################################################`
2732			`# START SYNTHESIS`
2733			`#====================================================================================`
2734			`# ProASIC3 (A3P1000), speedgrade: Std`
2735			`#====================================================================================`
2736			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2737			`# 12 10 1 1 1 1 1`
2738			`#====================================================================================`
2739
2740
2741			`Clock Domain: dco_clk`
2742			`Period (ns): 65.017`
2743			`Frequency (MHz): 15.381`
2744			`Required Period (ns): 40.000`
2745			`Required Frequency (MHz): 25.000`
2746			`External Setup (ns): 61.568`
2747			`External Hold (ns): 0.000`
2748			`Min Clock-To-Out (ns): 0.000`
2749			`Max Clock-To-Out (ns): 70.734`
2750
2751			`Input to Output`
2752			`Min Delay (ns): 0.000`
2753			`Max Delay (ns): 67.285`
2754
2755
2756			`====================================================================================`
2757			`Compile report:`
2758			`===============`
2759
2760			`CORE Used: 5747`
2761			`Core Information:`
2762
2763			`Type \| Instances \| Core tiles`
2764			`--------\|--------------\|-----------`
2765			`COMB \| 4954 \| 4954`
2766			`SEQ \| 793 \| 793`
2767
2768
2769			`====================================================================================`
2770			`# SYNTHESIS DONE`
2771			`#####################################################################################`
2772
2773			`#####################################################################################`
2774			`# START SYNTHESIS`
2775			`#====================================================================================`
2776			`# ProASIC3 (A3P1000), speedgrade: -1`
2777			`#====================================================================================`
2778			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2779			`# 12 10 1 1 1 1 1`
2780			`#====================================================================================`
2781
2782
2783			`Clock Domain: dco_clk`
2784			`Period (ns): 53.783`
2785			`Frequency (MHz): 18.593`
2786			`Required Period (ns): 40.000`
2787			`Required Frequency (MHz): 25.000`
2788			`External Setup (ns): 50.882`
2789			`External Hold (ns): 0.475`
2790			`Min Clock-To-Out (ns): 2.731`
2791			`Max Clock-To-Out (ns): 59.354`
2792
2793			`Input to Output`
2794			`Min Delay (ns): 1.901`
2795			`Max Delay (ns): 56.114`
2796
2797
2798			`====================================================================================`
2799			`Compile report:`
2800			`===============`
2801
2802			`CORE Used: 5713`
2803			`Core Information:`
2804
2805			`Type \| Instances \| Core tiles`
2806			`--------\|--------------\|-----------`
2807			`COMB \| 4920 \| 4920`
2808			`SEQ \| 793 \| 793`
2809
2810
2811			`====================================================================================`
2812			`# SYNTHESIS DONE`
2813			`#####################################################################################`
2814
2815			`#####################################################################################`
2816			`# START SYNTHESIS`
2817			`#====================================================================================`
2818			`# ProASIC3 (A3P1000), speedgrade: -2`
2819			`#====================================================================================`
2820			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2821			`# 12 10 1 1 1 1 1`
2822			`#====================================================================================`
2823
2824
2825			`Clock Domain: dco_clk`
2826			`Period (ns): 48.202`
2827			`Frequency (MHz): 20.746`
2828			`Required Period (ns): 40.000`
2829			`Required Frequency (MHz): 25.000`
2830			`External Setup (ns): 45.292`
2831			`External Hold (ns): 0.414`
2832			`Min Clock-To-Out (ns): 2.463`
2833			`Max Clock-To-Out (ns): 53.635`
2834
2835			`Input to Output`
2836			`Min Delay (ns): 1.941`
2837			`Max Delay (ns): 51.955`
2838
2839
2840			`====================================================================================`
2841			`Compile report:`
2842			`===============`
2843
2844			`CORE Used: 5625`
2845			`Core Information:`
2846
2847			`Type \| Instances \| Core tiles`
2848			`--------\|--------------\|-----------`
2849			`COMB \| 4833 \| 4833`
2850			`SEQ \| 792 \| 792`
2851
2852
2853			`====================================================================================`
2854			`# SYNTHESIS DONE`
2855			`#####################################################################################`
2856
2857			`#####################################################################################`
2858			`# START SYNTHESIS`
2859			`#====================================================================================`
2860			`# Fusion (AFS1500), speedgrade: Std`
2861			`#====================================================================================`
2862			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2863			`# 12 10 1 1 1 1 1`
2864			`#====================================================================================`
2865
2866
2867			`Clock Domain: dco_clk`
2868			`Period (ns): 64.510`
2869			`Frequency (MHz): 15.501`
2870			`Required Period (ns): 40.000`
2871			`Required Frequency (MHz): 25.000`
2872			`External Setup (ns): 61.904`
2873			`External Hold (ns): 0.000`
2874			`Min Clock-To-Out (ns): 0.000`
2875			`Max Clock-To-Out (ns): 75.008`
2876
2877			`Input to Output`
2878			`Min Delay (ns): 0.000`
2879			`Max Delay (ns): 73.237`
2880
2881
2882			`====================================================================================`
2883			`Compile report:`
2884			`===============`
2885
2886			`CORE Used: 5747`
2887			`Core Information:`
2888
2889			`Type \| Instances \| Core tiles`
2890			`--------\|--------------\|-----------`
2891			`COMB \| 4954 \| 4954`
2892			`SEQ \| 793 \| 793`
2893
2894
2895			`====================================================================================`
2896			`# SYNTHESIS DONE`
2897			`#####################################################################################`
2898
2899			`#####################################################################################`
2900			`# START SYNTHESIS`
2901			`#====================================================================================`
2902			`# Fusion (AFS1500), speedgrade: -1`
2903			`#====================================================================================`
2904			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2905			`# 12 10 1 1 1 1 1`
2906			`#====================================================================================`
2907
2908
2909			`Clock Domain: dco_clk`
2910			`Period (ns): 55.618`
2911			`Frequency (MHz): 17.980`
2912			`Required Period (ns): 40.000`
2913			`Required Frequency (MHz): 25.000`
2914			`External Setup (ns): 49.363`
2915			`External Hold (ns): 1.007`
2916			`Min Clock-To-Out (ns): 3.473`
2917			`Max Clock-To-Out (ns): 63.477`
2918
2919			`Input to Output`
2920			`Min Delay (ns): 2.212`
2921			`Max Delay (ns): 59.116`
2922
2923
2924			`====================================================================================`
2925			`Compile report:`
2926			`===============`
2927
2928			`CORE Used: 5713`
2929			`Core Information:`
2930
2931			`Type \| Instances \| Core tiles`
2932			`--------\|--------------\|-----------`
2933			`COMB \| 4920 \| 4920`
2934			`SEQ \| 793 \| 793`
2935
2936
2937			`====================================================================================`
2938			`# SYNTHESIS DONE`
2939			`#####################################################################################`
2940
2941			`#####################################################################################`
2942			`# START SYNTHESIS`
2943			`#====================================================================================`
2944			`# Fusion (AFS1500), speedgrade: -2`
2945			`#====================================================================================`
2946			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2947			`# 12 10 1 1 1 1 1`
2948			`#====================================================================================`
2949
2950
2951			`Clock Domain: dco_clk`
2952			`Period (ns): 48.568`
2953			`Frequency (MHz): 20.590`
2954			`Required Period (ns): 40.000`
2955			`Required Frequency (MHz): 25.000`
2956			`External Setup (ns): 45.081`
2957			`External Hold (ns): 1.026`
2958			`Min Clock-To-Out (ns): 2.608`
2959			`Max Clock-To-Out (ns): 55.077`
2960
2961			`Input to Output`
2962			`Min Delay (ns): 2.258`
2963			`Max Delay (ns): 51.590`
2964
2965
2966			`====================================================================================`
2967			`Compile report:`
2968			`===============`
2969
2970			`CORE Used: 5625`
2971			`Core Information:`
2972
2973			`Type \| Instances \| Core tiles`
2974			`--------\|--------------\|-----------`
2975			`COMB \| 4833 \| 4833`
2976			`SEQ \| 792 \| 792`
2977
2978
2979			`====================================================================================`
2980			`# SYNTHESIS DONE`
2981			`#####################################################################################`
2982
2983			`#####################################################################################`
2984			`# START SYNTHESIS`
2985			`#====================================================================================`
2986			`# IGLOOE (AGLE600V5), speedgrade: Std`
2987			`#====================================================================================`
2988			`# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3`
2989			`# 12 10 1 1 1 1 1`
2990			`#====================================================================================`
2991
2992
2993			`Clock Domain: dco_clk`
2994			`Period (ns): 70.914`
2995			`Frequency (MHz): 14.102`
2996			`Required Period (ns): 40.000`
2997			`Required Frequency (MHz): 25.000`
2998			`External Setup (ns): 67.728`
2999			`External Hold (ns): 0.000`
3000			`Min Clock-To-Out (ns): 0.000`
3001			`Max Clock-To-Out (ns): 80.521`
3002
3003			`Input to Output`
3004			`Min Delay (ns): 0.000`
3005			`Max Delay (ns): 77.335`
3006
3007
3008			`====================================================================================`
3009			`Compile report:`
3010			`===============`
3011
3012			`CORE Used: 5739`
3013			`Core Information:`
3014
3015			`Type \| Instances \| Core tiles`
3016			`--------\|--------------\|-----------`
3017			`COMB \| 4948 \| 4948`
3018			`SEQ \| 791 \| 791`
3019
3020
3021			`====================================================================================`
3022			`# SYNTHESIS DONE`
3023			`#####################################################################################`
3024
3025
3026			`#####################################################################################`
3027			`# ANALYSIS DONE`
3028			`#####################################################################################`
3029

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