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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [altera/] [src/] [openMSP430_undefines.v] - Blame information for rev 63

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1 63 olivier.gi 
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: openMSP430_undefines.v
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//
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// *Module Description:
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//                      openMSP430 Verilog `undef file
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 23 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// SYSTEM CONFIGURATION
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//----------------------------------------------------------------------------
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// Program Memory Size:
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`ifdef PMEM_AWIDTH
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`undef PMEM_AWIDTH
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`endif
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// Data Memory Size:
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`ifdef DMEM_AWIDTH
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`undef DMEM_AWIDTH
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`endif
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//----------------------------------------------------------------------------
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// REMOTE DEBUGGING INTERFACE CONFIGURATION
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//----------------------------------------------------------------------------
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// Include Debug interface
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`ifdef DBG_EN
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`undef DBG_EN
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`endif
61 
 
62 
// Debug interface selection
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`ifdef DBG_UART
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`undef DBG_UART
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`endif
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`ifdef DBG_JTAG
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`undef DBG_JTAG
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`endif
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// Number of hardware breakpoints
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`ifdef DBG_HWBRK_0
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`undef DBG_HWBRK_0
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`endif
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`ifdef DBG_HWBRK_1
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`undef DBG_HWBRK_1
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`endif
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`ifdef DBG_HWBRK_2
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`undef DBG_HWBRK_2
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`endif
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`ifdef DBG_HWBRK_3
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`undef DBG_HWBRK_3
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`endif
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84 
 
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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//==========================================================================//
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// Program and Data Memory sizes
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`ifdef PMEM_SIZE
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`undef PMEM_SIZE
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`endif
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`ifdef DMEM_SIZE
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`undef DMEM_SIZE
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`endif
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// Data Memory Base Adresses
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`ifdef DMEM_BASE
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`undef DMEM_BASE
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`endif
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// Program & Data Memory most significant address bit (for 16 bit words)
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`ifdef PMEM_MSB
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`undef PMEM_MSB
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`endif
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`ifdef DMEM_MSB
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`undef DMEM_MSB
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`endif
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// Instructions type
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`ifdef INST_SO
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`undef INST_SO
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`endif
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`ifdef INST_JMP
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`undef INST_JMP
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`endif
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`ifdef INST_TO
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`undef INST_TO
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`endif
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// Single-operand arithmetic
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`ifdef RRC
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`undef RRC
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`endif
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`ifdef SWPB
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`undef SWPB
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`endif
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`ifdef RRA
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`undef RRA
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`endif
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`ifdef SXT
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`undef SXT
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`endif
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`ifdef PUSH
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`undef PUSH
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`endif
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`ifdef CALL
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`undef CALL
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`endif
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`ifdef RETI
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`undef RETI
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`endif
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`ifdef IRQ
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`undef IRQ
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`endif
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// Conditional jump
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`ifdef JNE
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`undef JNE
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`endif
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`ifdef JEQ
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`undef JEQ
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`endif
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`ifdef JNC
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`undef JNC
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`endif
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`ifdef JC
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`undef JC
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`endif
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`ifdef JN
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`undef JN
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`endif
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`ifdef JGE
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`undef JGE
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`endif
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`ifdef JL
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`undef JL
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`endif
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`ifdef JMP
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`undef JMP
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`endif
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// Two-operand arithmetic
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`ifdef MOV
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`undef MOV
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`endif
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`ifdef ADD
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`undef ADD
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`endif
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`ifdef ADDC
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`undef ADDC
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`endif
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`ifdef SUBC
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`undef SUBC
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`endif
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`ifdef SUB
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`undef SUB
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`endif
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`ifdef CMP
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`undef CMP
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`endif
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`ifdef DADD
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`undef DADD
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`endif
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`ifdef BIT
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`undef BIT
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`endif
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`ifdef BIC
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`undef BIC
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`endif
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`ifdef BIS
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`undef BIS
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`endif
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`ifdef XOR
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`undef XOR
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`endif
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`ifdef AND
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`undef AND
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`endif
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218 
// Addressing modes
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`ifdef DIR
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`undef DIR
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`endif
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`ifdef IDX
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`undef IDX
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`endif
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`ifdef INDIR
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`undef INDIR
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`endif
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`ifdef INDIR_I
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`undef INDIR_I
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`endif
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`ifdef SYMB
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`undef SYMB
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`endif
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`ifdef IMM
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`undef IMM
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`endif
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`ifdef ABS
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`undef ABS
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`endif
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`ifdef CONST
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`undef CONST
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`endif
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// Execution state machine
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`ifdef E_IRQ_0
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`undef E_IRQ_0
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`endif
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`ifdef E_IRQ_1
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`undef E_IRQ_1
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`endif
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`ifdef E_IRQ_2
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`undef E_IRQ_2
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`endif
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`ifdef E_IRQ_3
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`undef E_IRQ_3
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`endif
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`ifdef E_IRQ_4
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`undef E_IRQ_4
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`endif
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`ifdef E_SRC_AD
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`undef E_SRC_AD
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`endif
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`ifdef E_SRC_RD
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`undef E_SRC_RD
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`endif
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`ifdef E_SRC_WR
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`undef E_SRC_WR
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`endif
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`ifdef E_DST_AD
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`undef E_DST_AD
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`endif
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`ifdef E_DST_RD
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`undef E_DST_RD
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`endif
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`ifdef E_DST_WR
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`undef E_DST_WR
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`endif
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`ifdef E_EXEC
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`undef E_EXEC
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`endif
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`ifdef E_JUMP
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`undef E_JUMP
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`endif
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`ifdef E_IDLE
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`undef E_IDLE
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`endif
287 
 
288 
// ALU control signals
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`ifdef ALU_SRC_INV
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`undef ALU_SRC_INV
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`endif
292 
`ifdef ALU_INC
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`undef ALU_INC
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`endif
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`ifdef ALU_INC_C
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`undef ALU_INC_C
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`endif
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`ifdef ALU_ADD
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`undef ALU_ADD
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`endif
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`ifdef ALU_AND
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`undef ALU_AND
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`endif
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`ifdef ALU_OR
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`undef ALU_OR
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`endif
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`ifdef ALU_XOR
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`undef ALU_XOR
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`endif
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`ifdef ALU_DADD
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`undef ALU_DADD
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`endif
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`ifdef ALU_STAT_7
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`undef ALU_STAT_7
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`endif
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`ifdef ALU_STAT_F
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`undef ALU_STAT_F
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`endif
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`ifdef ALU_SHIFT
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`undef ALU_SHIFT
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`endif
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`ifdef EXEC_NO_WR
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`undef EXEC_NO_WR
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`endif
325 
 
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// Debug interface
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`ifdef DBG_UART_WR
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`undef DBG_UART_WR
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`endif
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`ifdef DBG_UART_BW
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`undef DBG_UART_BW
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`endif
333 
`ifdef DBG_UART_ADDR
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`undef DBG_UART_ADDR
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`endif
336 
 
337 
// Debug interface CPU_CTL register
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`ifdef HALT
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`undef HALT
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`endif
341 
`ifdef RUN
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`undef RUN
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`endif
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`ifdef ISTEP
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`undef ISTEP
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`endif
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`ifdef SW_BRK_EN
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`undef SW_BRK_EN
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`endif
350 
`ifdef FRZ_BRK_EN
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`undef FRZ_BRK_EN
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`endif
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`ifdef RST_BRK_EN
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`undef RST_BRK_EN
355 
`endif
356 
`ifdef CPU_RST
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`undef CPU_RST
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`endif
359 
 
360 
// Debug interface CPU_STAT register
361 
`ifdef HALT_RUN
362 
`undef HALT_RUN
363 
`endif
364 
`ifdef PUC_PND
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`undef PUC_PND
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`endif
367 
`ifdef SWBRK_PND
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`undef SWBRK_PND
369 
`endif
370 
`ifdef HWBRK0_PND
371 
`undef HWBRK0_PND
372 
`endif
373 
`ifdef HWBRK1_PND
374 
`undef HWBRK1_PND
375 
`endif
376 
 
377 
// Debug interface BRKx_CTL register
378 
`ifdef BRK_MODE_RD
379 
`undef BRK_MODE_RD
380 
`endif
381 
`ifdef BRK_MODE_WR
382 
`undef BRK_MODE_WR
383 
`endif
384 
`ifdef BRK_MODE
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`undef BRK_MODE
386 
`endif
387 
`ifdef BRK_EN
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`undef BRK_EN
389 
`endif
390 
`ifdef BRK_I_EN
391 
`undef BRK_I_EN
392 
`endif
393 
`ifdef BRK_RANGE
394 
`undef BRK_RANGE
395 
`endif
396 
 
397 
// Basic clock module: BCSCTL1 Control Register
398 
`ifdef DIVAx
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`undef DIVAx
400 
`endif
401 
 
402 
// Basic clock module: BCSCTL2 Control Register
403 
`ifdef SELS
404 
`undef SELS
405 
`endif
406 
`ifdef DIVSx
407 
`undef DIVSx
408 
`endif
409 
 
410 
// Timer A: TACTL Control Register
411 
`ifdef TASSELx
412 
`undef TASSELx
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`endif
414 
`ifdef TAIDx
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`undef TAIDx
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`endif
417 
`ifdef TAMCx
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`undef TAMCx
419 
`endif
420 
`ifdef TACLR
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`undef TACLR
422 
`endif
423 
`ifdef TAIE
424 
`undef TAIE
425 
`endif
426 
`ifdef TAIFG
427 
`undef TAIFG
428 
`endif
429 
 
430 
// Timer A: TACCTLx Capture/Compare Control Register
431 
`ifdef TACMx
432 
`undef TACMx
433 
`endif
434 
`ifdef TACCISx
435 
`undef TACCISx
436 
`endif
437 
`ifdef TASCS
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`undef TASCS
439 
`endif
440 
`ifdef TASCCI
441 
`undef TASCCI
442 
`endif
443 
`ifdef TACAP
444 
`undef TACAP
445 
`endif
446 
`ifdef TAOUTMODx
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`undef TAOUTMODx
448 
`endif
449 
`ifdef TACCIE
450 
`undef TACCIE
451 
`endif
452 
`ifdef TACCI
453 
`undef TACCI
454 
`endif
455 
`ifdef TAOUT
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`undef TAOUT
457 
`endif
458 
`ifdef TACOV
459 
`undef TACOV
460 
`endif
461 
`ifdef TACCIFG
462 
`undef TACCIFG
463 
`endif
464 
 
465 
//
466 
// DEBUG INTERFACE EXTRA CONFIGURATION
467 
//======================================
468 
 
469 
// Debug interface: Software breakpoint opcode
470 
`ifdef DBG_SWBRK_OP
471 
`undef DBG_SWBRK_OP
472 
`endif
473 
 
474 
// Debug interface ID
475 
`ifdef DBG_ID
476 
`undef DBG_ID
477 
`endif
478 
 
479 
// Debug UART interface auto data synchronization
480 
`ifdef DBG_UART_AUTO_SYNC
481 
`undef DBG_UART_AUTO_SYNC
482 
`endif
483 
 
484 
// Debug UART interface data rate
485 
`ifdef DBG_UART_BAUD
486 
`undef DBG_UART_BAUD
487 
`endif
488 
`ifdef DBG_DCO_FREQ
489 
`undef DBG_DCO_FREQ
490 
`endif
491 
`ifdef DBG_UART_CNT
492 
`undef DBG_UART_CNT
493 
`endif

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