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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [synopsys/] [constraints.tcl] - Blame information for rev 2

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1 2 olivier.gi 
##############################################################################
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#                                                                            #
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#                            CLOCK DEFINITION                                #
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#                                                                            #
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##############################################################################
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#set CLOCK_PERIOD 50.0; #  20 MHz
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#set CLOCK_PERIOD 40.0; #  25 MHz
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#set CLOCK_PERIOD 30.0; #  33 MHz
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#set CLOCK_PERIOD 25.0; #  40 MHz
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set CLOCK_PERIOD 20.0; #  50 MHz
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#set CLOCK_PERIOD 15.0; #  66 MHz
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#set CLOCK_PERIOD 10.0; # 100 MHz
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#set CLOCK_PERIOD  8.0; # 125 MHz
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create_clock -name     "clock"                                \
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             -period   "$CLOCK_PERIOD"                        \
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             -waveform "[expr $CLOCK_PERIOD/2] $CLOCK_PERIOD" \
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            [get_ports clock]
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##############################################################################
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#                                                                            #
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#                          CREATE PATH GROUPS                                #
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#                                                                            #
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##############################################################################
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group_path -name REGOUT      -to   [all_outputs]
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group_path -name REGIN       -from [remove_from_collection [all_inputs] [get_ports clock]]
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group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] [get_ports clock]] -to [all_outputs]
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##############################################################################
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#                                                                            #
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#                          BOUNDARY TIMINGS                                  #
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#                                                                            #
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##############################################################################
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# NOTE: There are some path through between RAM and ROM signals.
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#       If required you might want to relax the constrains a bit.
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#===============#
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# INPUT PORTS   #
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#===============#
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set IRQ_DLY          [expr ($CLOCK_PERIOD/100) * 30]
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set NMI_DLY          [expr ($CLOCK_PERIOD/100) * 10]
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set PER_DOUT_DLY     [expr ($CLOCK_PERIOD/100) * 20]
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set RAM_DOUT_DLY     [expr ($CLOCK_PERIOD/100) * 20]
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set ROM_DOUT_DLY     [expr ($CLOCK_PERIOD/100) * 20]
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set RESET_N_DLY      [expr ($CLOCK_PERIOD/100) * 75]
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set_input_delay $IRQ_DLY       -max -clock "clock"             [get_ports irq]
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set_input_delay 0              -min -clock "clock"             [get_ports irq]
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set_input_delay $NMI_DLY       -max -clock "clock"             [get_ports nmi]
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set_input_delay 0              -min -clock "clock"             [get_ports nmi]
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set_input_delay $PER_DOUT_DLY  -max -clock "clock"             [get_ports per_dout]
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set_input_delay 0              -min -clock "clock"             [get_ports per_dout]
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set_input_delay $RAM_DOUT_DLY  -max -clock "clock"             [get_ports ram_dout]
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set_input_delay 0              -min -clock "clock"             [get_ports ram_dout]
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set_input_delay $ROM_DOUT_DLY  -max -clock "clock"             [get_ports rom_dout]
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set_input_delay 0              -min -clock "clock"             [get_ports rom_dout]
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set_input_delay $RESET_N_DLY   -max -clock "clock" -clock_fall [get_ports reset_n]
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set_input_delay 0              -min -clock "clock" -clock_fall [get_ports reset_n]
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#===============#
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# OUTPUT PORTS  #
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#===============#
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set PER_ADDR_DLY     [expr ($CLOCK_PERIOD/100) * 25]
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set PER_DIN_DLY      [expr ($CLOCK_PERIOD/100) * 25]
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set PER_WEN_DLY      [expr ($CLOCK_PERIOD/100) * 25]
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set PER_8B_CEN_DLY   [expr ($CLOCK_PERIOD/100) * 25]
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set PER_16B_CEN_DLY  [expr ($CLOCK_PERIOD/100) * 25]
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set RAM_ADDR_DLY     [expr ($CLOCK_PERIOD/100) * 20]
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set RAM_CEN_DLY      [expr ($CLOCK_PERIOD/100) * 20]
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set RAM_DIN_DLY      [expr ($CLOCK_PERIOD/100) * 20]
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set RAM_WEN_DLY      [expr ($CLOCK_PERIOD/100) * 20]
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set ROM_ADDR_DLY     [expr ($CLOCK_PERIOD/100) * 20]
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set ROM_CEN_DLY      [expr ($CLOCK_PERIOD/100) * 20]
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set MRST_DLY         [expr ($CLOCK_PERIOD/100) * 75]
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set_output_delay $PER_ADDR_DLY     -add_delay -max -clock "clock"             [get_ports per_addr]
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set_output_delay 0                            -min -clock "clock"             [get_ports per_addr]
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set_output_delay $PER_DIN_DLY      -add_delay -max -clock "clock"             [get_ports per_din]
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set_output_delay 0                            -min -clock "clock"             [get_ports per_din]
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set_output_delay $PER_WEN_DLY      -add_delay -max -clock "clock"             [get_ports per_wen]
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set_output_delay 0                            -min -clock "clock"             [get_ports per_wen]
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set_output_delay $PER_8B_CEN_DLY   -add_delay -max -clock "clock"             [get_ports per_8b_cen]
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set_output_delay 0                            -min -clock "clock"             [get_ports per_8b_cen]
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set_output_delay $PER_16B_CEN_DLY  -add_delay -max -clock "clock"             [get_ports per_16b_cen]
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set_output_delay 0                            -min -clock "clock"             [get_ports per_16b_cen]
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set_output_delay $RAM_ADDR_DLY     -add_delay -max -clock "clock"             [get_ports ram_addr]
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set_output_delay 0                            -min -clock "clock"             [get_ports ram_addr]
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set_output_delay $RAM_CEN_DLY      -add_delay -max -clock "clock"             [get_ports ram_cen]
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set_output_delay 0                            -min -clock "clock"             [get_ports ram_cen]
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set_output_delay $RAM_DIN_DLY      -add_delay -max -clock "clock"             [get_ports ram_din]
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set_output_delay 0                            -min -clock "clock"             [get_ports ram_din]
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set_output_delay $RAM_WEN_DLY      -add_delay -max -clock "clock"             [get_ports ram_wen]
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set_output_delay 0                            -min -clock "clock"             [get_ports ram_wen]
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set_output_delay $ROM_ADDR_DLY     -add_delay -max -clock "clock"             [get_ports rom_addr]
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set_output_delay 0                            -min -clock "clock"             [get_ports rom_addr]
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set_output_delay $ROM_CEN_DLY      -add_delay -max -clock "clock"             [get_ports rom_cen]
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set_output_delay 0                            -min -clock "clock"             [get_ports rom_cen]
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set_output_delay $MRST_DLY         -add_delay -max -clock "clock" -clock_fall [get_ports mrst]
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set_output_delay 0                            -min -clock "clock" -clock_fall [get_ports mrst]
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#========================#
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# FEEDTHROUGH EXCEPTIONS #
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#========================#
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#set_max_delay [expr 2.0 + $RAM_DOUT_DLY + $RAM_ADDR_DLY] \
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#              -from       [get_ports ram_dout]            \
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#              -to         [get_ports ram_addr]            \
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#              -group_path FEEDTHROUGH
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