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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html><head><title>openMSP430 Serial Debug Interface</title>
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4 
 
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<meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body>
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<a name="TOC"></a>
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<h3>Table of content</h3>
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<ul>
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        <li><strong><a href="#1.%20Introduction">                          1. Introduction</a></strong></li>
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        <li><strong><a href="#2.%20Debug%20Unit">                            2. Debug Unit</a></strong>
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        <ul>
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      <li><a href="#2.1%20Register%20Mapping">                  2.1 Register Mapping</a></li>
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      <li><a href="#2.2%20CPU%20Control/Status%20Registers">      2.2 CPU Control/Status Registers</a></li>
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                <ul>
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           <li><a href="#2.2.1%20CPU_ID">                       2.2.1 CPU_ID</a></li>
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        <li><a href="#2.2.2%20CPU_CTL">                      2.2.2 CPU_CTL</a></li>
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        <li><a href="#2.2.3%20CPU_STAT">                     2.2.3 CPU_STAT</a></li>
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        <li><a href="#2.2.4%20CPU_NR">                       2.2.4 CPU_NR</a></li>
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                </ul>
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      <li><a href="#2.3%20Memory%20Access%20Registers">           2.3 Memory Access Registers</a></li>
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                <ul>
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           <li><a href="#2.3.1%20MEM_CTL">                      2.3.1 MEM_CTL</a></li>
23 
        <li><a href="#2.3.2%20MEM_ADDR">                     2.3.2 MEM_ADDR</a></li>
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        <li><a href="#2.3.3%20MEM_DATA">                     2.3.3 MEM_DATA</a></li>
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        <li><a href="#2.3.4%20MEM_CNT">                      2.3.4 MEM_CNT</a></li>
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                </ul>
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      <li><a href="#2.4%20Hardware%20Breakpoint%20Unit%20Registers">2.4 Hardware Breakpoint Unit Registers</a></li>
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                <ul>
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           <li><a href="#2.4.1%20BRKx_CTL">                     2.4.1 BRKx_CTL</a></li>
30 
        <li><a href="#2.4.2%20BRKx_STAT">                    2.4.2 BRKx_STAT</a></li>
31 
        <li><a href="#2.4.3%20BRKx_ADDR0">                   2.4.3 BRKx_ADDR0</a></li>
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        <li><a href="#2.4.4%20BRKx_ADDR1">                   2.4.4 BRKx_ADDR1</a></li>
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                </ul>
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        </ul>
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        </li>
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        <li><strong><a href="#3.%20Debug%20Communication%20Interface:%20UART">   3. Debug Communication Interface: UART</a></strong>
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                <ul>
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           <li><a href="#3.1%20Serial%20communication%20protocol:%208N1">       3.1 Serial communication protocol: 8N1</a></li>
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        <li><a href="#3.2%20Synchronization%20frame">                    3.2 Synchronization frame</a></li>
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        <li><a href="#3.3%20Read/Write%20access%20to%20the%20debug%20registers"> 3.3 Read/Write access to the debug registers</a></li>
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                        <ul>
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                <li><a href="#3.3.1%20Command%20Frame">                       3.3.1 Command Frame</a></li>
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                <li><a href="#3.3.2%20Write%20access">                        3.3.2 Write access</a></li>
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                <li><a href="#3.3.3%20Read%20access">                         3.3.3 Read access</a></li>
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                        </ul>
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        <li><a href="#3.4%20Read/Write%20burst%20implementation%20for%20the%20CPU%20Memory%20access">3.4 Read/Write burst implementation for the CPU Memory access</a></li>
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                        <ul>
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                <li><a href="#3.4.1%20Write%20Burst%20access">                  3.4.1 Write Burst access</a></li>
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                <li><a href="#3.4.2%20Read%20Burst%20access">                   3.4.2 Read Burst access</a></li>
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                        </ul>
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                </ul>
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   </li>
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        <li><strong><a href="#4.%20Debug%20Communication%20Interface:%20I2C">   4. Debug Communication Interface: I2C</a></strong>
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                <ul>
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           <li><a href="#4.1%20I2C%20communication%20protocol">       4.1 I2C communication protocol</a></li>
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        <li><a href="#4.2%20Synchronization%20frame">                    4.2 Synchronization frame</a></li>
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        <li><a href="#4.3%20Read/Write%20access%20to%20the%20debug%20registers"> 4.3 Read/Write access to the debug registers</a></li>
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                        <ul>
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                <li><a href="#4.3.1%20Command%20Frame">                       4.3.1 Command Frame</a></li>
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                <li><a href="#4.3.2%20Write%20access">                        4.3.2 Write access</a></li>
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                <li><a href="#4.3.3%20Read%20access">                         4.3.3 Read access</a></li>
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                        </ul>
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        <li><a href="#4.4%20Read/Write%20burst%20implementation%20for%20the%20CPU%20Memory%20access">4.4 Read/Write burst implementation for the CPU Memory access</a></li>
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                        <ul>
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                <li><a href="#4.4.1%20Write%20Burst%20access">                  4.4.1 Write Burst access</a></li>
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                <li><a href="#4.4.2%20Read%20Burst%20access">                   4.4.2 Read Burst access</a></li>
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                        </ul>
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                </ul>
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   </li>
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</ul>
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72 
<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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The original MSP430 from TI provides a serial debug interface to allow
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in-system software debugging. In that case, the communication
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with the host computer is typically built on a JTAG or Spy-Bi-Wire
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serial protocol. However, the global debug architecture from the MSP430
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is unfortunately poorly documented on the web (and is also probably
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tightly linked with the internal core micro-architecture).
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<br><br>A custom module has therefore been implemented for the
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openMSP430. The communication with the host is done with a simple two-wire cable following either the UART or I<sup>2</sup>C serial protocol (interface is selectable in the <a href="http://opencores.org/project,openmsp430,core#2.1.3.3%20Expert%20System%20Configuration">Expert System Configuraiton</a> section).
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<br><br>The debug unit provides all required features for Nexus Class 3 debugging (beside trace), namely: <br>
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<br>
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<table style="text-align: left; width: 50%; margin-left: auto; margin-right: auto;" border="1" cellpadding="2" cellspacing="2">
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  <tbody>
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    <tr align="center">
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      <td style="vertical-align: top;"><span style="font-weight: bold;"><strong>Debug unit features</strong></span><br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top;">
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      <ul>
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<li>CPU control (run, stop, step, reset).</li><li>Software &amp; hardware breakpoint.</li><li>Hardware watchpoint.<br>
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  </li><li>Memory read/write on-the-fly (no need to halt execution).</li><li>CPU registers read/write on-the-fly (no need to halt execution).</li>
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      </ul>
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      </td>
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    </tr>
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  </tbody>
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</table>
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<br>
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<ul></ul>
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Depending on the selected serial interface, the following features are available:<br>
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<br>
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<table style="text-align: left; width: 50%; margin-left: auto; margin-right: auto;" border="1" cellpadding="2" cellspacing="2">
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  <tbody>
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    <tr align="center">
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      <td colspan="2" rowspan="1" style="vertical-align: top;"><span style="font-weight: bold;"><strong>Debug interface features</strong></span><br>
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      </td>
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    </tr>
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<tr>
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      <td style="vertical-align: top; text-align: center;"><strong>UART</strong><br>
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      </td>
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      <td style="vertical-align: top; text-align: center;"><strong>I<sup>2</sup>C</strong><br>
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      </td>
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    </tr>
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    <tr>
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      <td style="vertical-align: top; text-align: left;">
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      <span style="font-weight: bold;"><br>
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Strengths:</span><br>
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<ul>
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        <li>No extra hardware required for most FPGA boards (almost all come with a UART interface, either <a href="http://www.ftdichip.com/Products/Cables/USBRS232.htm">RS232 or USB</a> based).</li>
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        <li>Possibility to use <a href="http://www.ftdichip.com/Products/Cables/USBTTLSerial.htm">USB to serial TTL</a> cables.</li>
127 
 
128 
      </ul><span style="font-weight: bold;">Weaknesses:</span><br>
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      <ul>
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        <li>Need to reset the debug interface after cable insertion.</li>
131 
        <li>For ASICs, no possibility to change the MCLK frequency during a debug session.<br>
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        </li>
133 
      </ul>
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135 
</td>
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      <td style="vertical-align: top; text-align: left;"><br>
137 
      <span style="font-weight: bold;">Strengths:</span><br>
138 
<ul>
139 
 
140 
        <li>Very stable interface (synchronous protocol, no synchronization frame required).</li>
141 
 
142 
 
143 
        <li>Multi-core chip support with a single I2C
144 
interface (i.e. TWO pins)... in such a system, each openMSP430 instance has its own I2C device address.</li>
145 
        <li>Possibility to combine the openMSP430 debug interface with
146 
an already existing "functional" I2C interface... effectively creating
147 
a ZERO
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wire serial debug interface.</li>
149 
        <li>Affordable <a href="http://www.robot-electronics.co.uk/htm/usb_iss_tech.htm">USB-ISS adapter</a> (~23€).</li>
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</ul><span style="font-weight: bold;">Weaknesses:</span><br>
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      <ul>
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        <li>Extra I2C adapter required (<a href="http://www.robot-electronics.co.uk/htm/usb_iss_tech.htm">USB-ISS</a> currently supported)<br>
153 
</li>
154 
      </ul>
155 
      <br>
156 
 
157 
</td>
158 
    </tr>
159 
  </tbody>
160 
</table>
161 
 
162 
<a name="2. Debug Unit"></a><br>
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<h1>2. Debug Unit</h1>
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167 
<a name="2.1 Register Mapping"></a>
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<h2>2.1 Register Mapping</h2>
169 
 
170 
The following table summarize the complete debug register set accessible through the debug communication interface:
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<br><br>
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<table border="1">
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<tbody><tr align="center">
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<td rowspan="2"><b><small>Register Name</small></b></td>
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<td rowspan="2"><b><small>Address</small></b></td>
176 
<td colspan="16"><b><small>Bit Field</small></b></td>
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</tr>
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<tr align="center">
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<td><small>15</small></td><td><small>14</small></td>
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<td><small>13</small></td><td><small>12</small></td>
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<td><small>11</small></td><td><small>10</small></td>
182 
<td><small> 9</small></td><td><small> 8</small></td>
183 
<td><small> 7</small></td><td><small> 6</small></td>
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<td><small> 5</small></td><td><small> 4</small></td>
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<td><small> 3</small></td><td><small> 2</small></td>
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<td><small> 1</small></td><td><small> 0</small></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.2.1%20CPU_ID">CPU_ID_LO</a></small></td>
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<td><small>0x00</small></td>
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<td colspan="7"><font size="-5">PER_SPACE</font></td>
192 
<td colspan="5"><font size="-5">USER_VERSION</font></td>
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<td colspan="1"><font size="-5">ASIC</font></td>
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<td colspan="3"><font size="-5">CPU_VERSION</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.2.1%20CPU_ID">CPU_ID_HI</a></small></td>
198 
<td><small>0x01</small></td>
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<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
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<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
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<td colspan="1"><font size="-5">MPY</font></td>
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</tr>
203 
<tr align="center">
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<td><small><a href="#2.2.2%20CPU_CTL">CPU_CTL</a></small></td>
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<td><small>0x02</small></td>
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<td colspan="9"><font size="-5">Reserved</font></td>
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<td><font size="-5">CPU_RST</font></td>
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<td><font size="-5">RST_BRK_EN</font></td>
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<td><font size="-5">FRZ_BRK_EN</font></td>
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<td><font size="-5">SW_BRK_EN</font></td>
211 
<td><font size="-5">ISTEP</font></td>
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<td><font size="-5">RUN</font></td>
213 
<td><font size="-5">HALT</font></td>
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</tr>
215 
<tr align="center">
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<td><small><a href="#2.2.3%20CPU_STAT">CPU_STAT</a></small></td>
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<td><small>0x03</small></td>
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<td colspan="8"><font size="-5">Reserved</font></td>
219 
<td><font size="-5">HWBRK3_PND</font></td>
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<td><font size="-5">HWBRK2_PND</font></td>
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<td><font size="-5">HWBRK1_PND</font></td>
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<td><font size="-5">HWBRK0_PND</font></td>
223 
<td><font size="-5">SWBRK_PND</font></td>
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<td><font size="-5">PUC_PND</font></td>
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<td><font size="-5">Res.</font></td>
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<td><font size="-5">HALT_RUN</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.3.1%20MEM_CTL">MEM_CTL</a></small></td>
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<td><small>0x04</small></td>
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<td colspan="12"><font size="-5">Reserved</font></td>
232 
<td><font size="-5">B/W</font></td>
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<td><font size="-5">MEM/REG</font></td>
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<td><font size="-5">RD/WR</font></td>
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<td><font size="-5">START</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.3.2%20MEM_ADDR">MEM_ADDR</a></small></td>
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<td><small>0x05</small></td>
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<td colspan="16"><font size="-5">MEM_ADDR[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.3.3%20MEM_DATA">MEM_DATA</a></small></td>
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<td><small>0x06</small></td>
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<td colspan="16"><font size="-5">MEM_DATA[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.3.4%20MEM_CNT">MEM_CNT</a></small></td>
249 
<td><small>0x07</small></td>
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<td colspan="16"><font size="-5">MEM_CNT[15:0]</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.1%20BRKx_CTL">BRK0_CTL</a></small></td>
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<td><small>0x08</small></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
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<td><font size="-5">RANGE_MODE</font></td>
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<td><font size="-5">INST_EN</font></td>
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<td><font size="-5">BREAK_EN</font></td>
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<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
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</tr>
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<tr align="center">
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<td><small><a href="#2.4.2%20BRKx_STAT">BRK0_STAT</a></small></td>
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<td><small>0x09</small></td>
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<td colspan="10"><font size="-5">Reserved</font></td>
265 
<td><font size="-5">RANGE_WR</font></td>
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<td><font size="-5">RANGE_RD</font></td>
267 
<td><font size="-5">ADDR1_WR</font></td>
268 
<td><font size="-5">ADDR1_RD</font></td>
269 
<td><font size="-5">ADDR0_WR</font></td>
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<td><font size="-5">ADDR0_RD</font></td>
271 
</tr>
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<tr align="center">
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<td><small><a href="#2.4.3%20BRKx_ADDR0">BRK0_ADDR0</a></small></td>
274 
<td><small>0x0A</small></td>
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
276 
</tr>
277 
<tr align="center">
278 135 olivier.gi 
<td><small><a href="#2.4.4%20BRKx_ADDR1">BRK0_ADDR1</a></small></td>
279 
<td><small>0x0B</small></td>
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
281 
</tr>
282 
<tr align="center">
283 135 olivier.gi 
<td><small><a href="#2.4.1%20BRKx_CTL">BRK1_CTL</a></small></td>
284 
<td><small>0x0C</small></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
286 
<td><font size="-5">RANGE_MODE</font></td>
287 
<td><font size="-5">INST_EN</font></td>
288 
<td><font size="-5">BREAK_EN</font></td>
289 
<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
290 
</tr>
291 
<tr align="center">
292 135 olivier.gi 
<td><small><a href="#2.4.2%20BRKx_STAT">BRK1_STAT</a></small></td>
293 
<td><small>0x0D</small></td>
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<td colspan="10"><font size="-5">Reserved</font></td>
295 
<td><font size="-5">RANGE_WR</font></td>
296 
<td><font size="-5">RANGE_RD</font></td>
297 
<td><font size="-5">ADDR1_WR</font></td>
298 
<td><font size="-5">ADDR1_RD</font></td>
299 
<td><font size="-5">ADDR0_WR</font></td>
300 
<td><font size="-5">ADDR0_RD</font></td>
301 
</tr>
302 
<tr align="center">
303 135 olivier.gi 
<td><small><a href="#2.4.3%20BRKx_ADDR0">BRK1_ADDR0</a></small></td>
304 
<td><small>0x0E</small></td>
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
306 
</tr>
307 
<tr align="center">
308 135 olivier.gi 
<td><small><a href="#2.4.4%20BRKx_ADDR1">BRK1_ADDR1</a></small></td>
309 
<td><small>0x0F</small></td>
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
311 
</tr>
312 
<tr align="center">
313 135 olivier.gi 
<td><small><a href="#2.4.1%20BRKx_CTL">BRK2_CTL</a></small></td>
314 
<td><small>0x10</small></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
316 
<td><font size="-5">RANGE_MODE</font></td>
317 
<td><font size="-5">INST_EN</font></td>
318 
<td><font size="-5">BREAK_EN</font></td>
319 
<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
320 
</tr>
321 
<tr align="center">
322 135 olivier.gi 
<td><small><a href="#2.4.2%20BRKx_STAT">BRK2_STAT</a></small></td>
323 
<td><small>0x11</small></td>
324 50 olivier.gi 
<td colspan="10"><font size="-5">Reserved</font></td>
325 
<td><font size="-5">RANGE_WR</font></td>
326 
<td><font size="-5">RANGE_RD</font></td>
327 
<td><font size="-5">ADDR1_WR</font></td>
328 
<td><font size="-5">ADDR1_RD</font></td>
329 
<td><font size="-5">ADDR0_WR</font></td>
330 
<td><font size="-5">ADDR0_RD</font></td>
331 
</tr>
332 
<tr align="center">
333 135 olivier.gi 
<td><small><a href="#2.4.3%20BRKx_ADDR0">BRK2_ADDR0</a></small></td>
334 
<td><small>0x12</small></td>
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<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
336 
</tr>
337 
<tr align="center">
338 135 olivier.gi 
<td><small><a href="#2.4.4%20BRKx_ADDR1">BRK2_ADDR1</a></small></td>
339 
<td><small>0x13</small></td>
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<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
341 
</tr>
342 
<tr align="center">
343 135 olivier.gi 
<td><small><a href="#2.4.1%20BRKx_CTL">BRK3_CTL</a></small></td>
344 
<td><small>0x14</small></td>
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<td colspan="11"><font size="-5">Reserved</font></td>
346 
<td><font size="-5">RANGE_MODE</font></td>
347 
<td><font size="-5">INST_EN</font></td>
348 
<td><font size="-5">BREAK_EN</font></td>
349 
<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
350 
</tr>
351 
<tr align="center">
352 135 olivier.gi 
<td><small><a href="#2.4.2%20BRKx_STAT">BRK3_STAT</a></small></td>
353 
<td><small>0x15</small></td>
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<td colspan="10"><font size="-5">Reserved</font></td>
355 
<td><font size="-5">RANGE_WR</font></td>
356 
<td><font size="-5">RANGE_RD</font></td>
357 
<td><font size="-5">ADDR1_WR</font></td>
358 
<td><font size="-5">ADDR1_RD</font></td>
359 
<td><font size="-5">ADDR0_WR</font></td>
360 
<td><font size="-5">ADDR0_RD</font></td>
361 
</tr>
362 
<tr align="center">
363 135 olivier.gi 
<td><small><a href="#2.4.3%20BRKx_ADDR0">BRK3_ADDR0</a></small></td>
364 
<td><small>0x16</small></td>
365 50 olivier.gi 
<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
366 
</tr>
367 
<tr align="center">
368 135 olivier.gi 
<td><small><a href="#2.4.4%20BRKx_ADDR1">BRK3_ADDR1</a></small></td>
369 
<td><small>0x17</small></td>
370 50 olivier.gi 
<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
371 
</tr>
372 166 olivier.gi 
<tr align="center">
373 
<td><small><a href="#2.2.4%20CPU_NR">CPU_NR</a></small></td>
374 
<td><small>0x18</small></td>
375 
<td colspan="8"><small>CPU_TOTAL_NR</small></td>
376 
<td colspan="8"><small>CPU_INST_NR</small></td>
377 
</tr>
378 
 
379 135 olivier.gi 
</tbody></table>
380 50 olivier.gi 
 
381 
<a name="2.2 CPU Control/Status Registers"></a>
382 135 olivier.gi 
<div style="text-align: right;"><a href="#TOC">Top</a></div>
383 50 olivier.gi 
<h2>2.2 CPU Control/Status Registers</h2>
384 
 
385 
<a name="2.2.1 CPU_ID"></a>
386 
<h3>2.2.1 CPU_ID</h3>
387 74 olivier.gi 
This 32 bit read-only register holds the program and data memory size information of the implemented openMSP430.
388 135 olivier.gi 
<br><br>
389 50 olivier.gi 
<table border="1">
390 135 olivier.gi 
<tbody><tr align="center">
391 
<td rowspan="2"><b><small>Register Name</small></b></td>
392 
<td rowspan="2"><b><small>Address</small></b></td>
393 
<td colspan="16"><b><small>Bit Field</small></b></td>
394 50 olivier.gi 
</tr>
395 
<tr align="center">
396 135 olivier.gi 
<td><small>15</small></td><td><small>14</small></td>
397 
<td><small>13</small></td><td><small>12</small></td>
398 
<td><small>11</small></td><td><small>10</small></td>
399 
<td><small> 9</small></td><td><small> 8</small></td>
400 
<td><small> 7</small></td><td><small> 6</small></td>
401 
<td><small> 5</small></td><td><small> 4</small></td>
402 
<td><small> 3</small></td><td><small> 2</small></td>
403 
<td><small> 1</small></td><td><small> 0</small></td>
404 50 olivier.gi 
</tr>
405 
<tr align="center">
406 135 olivier.gi 
<td><small>CPU_ID_LO</small></td>
407 
<td><small>0x00</small></td>
408 116 olivier.gi 
<td colspan="7"><font size="-5">PER_SPACE</font></td>
409 
<td colspan="5"><font size="-5">USER_VERSION</font></td>
410 
<td colspan="1"><font size="-5">ASIC</font></td>
411 
<td colspan="3"><font size="-5">CPU_VERSION</font></td>
412 50 olivier.gi 
</tr>
413 
<tr align="center">
414 135 olivier.gi 
<td><small>CPU_ID_HI</small></td>
415 
<td><small>0x01</small></td>
416 116 olivier.gi 
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
417 
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
418 
<td colspan="1"><font size="-5">MPY</font></td>
419 50 olivier.gi 
</tr>
420 135 olivier.gi 
</tbody></table>
421 
<br>
422 50 olivier.gi 
<table border="0">
423 135 olivier.gi 
<tbody><tr>
424 116 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>CPU_VERSION</b></li></td>
425 135 olivier.gi 
   <td>: Current CPU version<br>
426 
</td>
427 50 olivier.gi 
</tr>
428 
<tr>
429 116 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>ASIC</b></li></td>
430 
   <td>: Defines if the ASIC specific features are enabled in the current openMSP430 implementation.</td>
431 50 olivier.gi 
</tr>
432 116 olivier.gi 
<tr>
433 
   <td>&nbsp;</td><td valign="top"><li><b>USER_VERSION</b></li></td>
434 
   <td>: Reflects the value defined in the <b>openMSP430_defines.v</b> file.</td>
435 
</tr>
436 
<tr>
437 
   <td>&nbsp;</td><td valign="top"><li><b>PER_SPACE</b></li></td>
438 
   <td>: Peripheral address space for the current implementation (byte size = PER_SPACE*512)</td>
439 
</tr>
440 
<tr>
441 
   <td>&nbsp;</td><td valign="top"><li><b>MPY</b></li></td>
442 
   <td>: This bit is set if the hardware multiplier is included in the current implementation</td>
443 
</tr>
444 
<tr>
445 
   <td>&nbsp;</td><td valign="top"><li><b>DMEM_SIZE</b></li></td>
446 
   <td>: Data memory size for the current implementation (byte size = DMEM_SIZE*128)</td>
447 
</tr>
448 
<tr>
449 
   <td>&nbsp;</td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
450 
   <td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
451 
</tr>
452 135 olivier.gi 
</tbody></table>
453 50 olivier.gi 
 
454 
<a name="2.2.2 CPU_CTL"></a>
455 135 olivier.gi 
<h3>2.2.2 CPU_CTL</h3> This 8 bit read-write register is used to
456 
control the CPU and to configure some basic debug features. After a
457 
POR, this register is set to 0x10 or 0x30 (depending on the <span style="font-weight: bold;">DBG_RST_BRK_EN</span> configuration option).
458 
<br><br>
459 50 olivier.gi 
<table border="1">
460 135 olivier.gi 
<tbody><tr align="center">
461 
<td rowspan="2"><b><small>Register Name</small></b></td>
462 
<td rowspan="2"><b><small>Address</small></b></td>
463 
<td colspan="16"><b><small>Bit Field</small></b></td>
464 50 olivier.gi 
</tr>
465 
<tr align="center">
466 135 olivier.gi 
<td><small> 7</small></td><td><small> 6</small></td>
467 
<td><small> 5</small></td><td><small> 4</small></td>
468 
<td><small> 3</small></td><td><small> 2</small></td>
469 
<td><small> 1</small></td><td><small> 0</small></td>
470 50 olivier.gi 
</tr>
471 
<tr align="center">
472 135 olivier.gi 
<td><small>CPU_CTL</small></td>
473 
<td><small>0x02</small></td>
474 50 olivier.gi 
<td><font size="-5">Res.</font></td>
475 
<td><font size="-5">CPU_RST</font></td>
476 
<td><font size="-5">RST_BRK_EN</font></td>
477 
<td><font size="-5">FRZ_BRK_EN</font></td>
478 
<td><font size="-5">SW_BRK_EN</font></td>
479 
<td><font size="-5">ISTEP</font></td>
480 
<td><font size="-5">RUN</font></td>
481 
<td><font size="-5">HALT</font></td>
482 
</tr>
483 135 olivier.gi 
</tbody></table>
484 
<br>
485 50 olivier.gi 
<table border="0">
486 135 olivier.gi 
<tbody><tr>
487 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>CPU_RST</b></li></td>
488 
   <td>: Setting this bit to 1 will activate the PUC reset. Setting it back to 0 will release it.</td>
489 
</tr>
490 
<tr>
491 
   <td>&nbsp;</td><td valign="top"><li><b>RST_BRK_EN</b></li></td>
492 
   <td>: If set to 1, the CPU will automatically break after a PUC occurrence.</td>
493 
</tr>
494 
<tr>
495 
   <td>&nbsp;</td><td valign="top"><li><b>FRZ_BRK_EN</b></li></td>
496 
   <td>: If set to 1, the timers and watchdog are frozen when the CPU is halted.</td>
497 
</tr>
498 
<tr>
499 
   <td>&nbsp;</td><td valign="top"><li><b>SW_BRK_EN</b></li></td>
500 
   <td>: Enables the software breakpoint detection.</td>
501 
</tr>
502 
<tr>
503 
   <td>&nbsp;</td><td valign="top"><li><b>ISTEP</b><sup>1</sup></li></td>
504 
   <td>: Writing 1 to this bit will perform a single instruction step if the CPU is halted.</td>
505 
</tr>
506 
<tr>
507 
   <td>&nbsp;</td><td valign="top"><li><b>RUN</b><sup>1</sup></li></td>
508 
   <td>: Writing 1 to this bit will get the CPU out of halt state.</td>
509 
</tr>
510 
<tr>
511 
   <td>&nbsp;</td><td valign="top"><li><b>HALT</b><sup>1</sup></li></td>
512 
   <td>: Writing 1 to this bit will put the CPU in halt state.</td>
513 
</tr>
514 135 olivier.gi 
</tbody></table>
515 
<br><sup>1</sup>:this field is write-only and always reads back 0.
516 
<br>
517 50 olivier.gi 
<a name="2.2.3 CPU_STAT"></a>
518 
<h3>2.2.3 CPU_STAT</h3>
519 
 
520 
This 8 bit read-write register gives the global status of the debug interface. After a POR, this register is set to 0x00.
521 135 olivier.gi 
<br><br>
522 50 olivier.gi 
<table border="1">
523 135 olivier.gi 
<tbody><tr align="center">
524 
<td rowspan="2"><b><small>Register Name</small></b></td>
525 
<td rowspan="2"><b><small>Address</small></b></td>
526 
<td colspan="16"><b><small>Bit Field</small></b></td>
527 50 olivier.gi 
</tr>
528 
<tr align="center">
529 135 olivier.gi 
<td><small> 7</small></td><td><small> 6</small></td>
530 
<td><small> 5</small></td><td><small> 4</small></td>
531 
<td><small> 3</small></td><td><small> 2</small></td>
532 
<td><small> 1</small></td><td><small> 0</small></td>
533 50 olivier.gi 
</tr>
534 
<tr align="center">
535 135 olivier.gi 
<td><small>CPU_STAT</small></td>
536 
<td><small>0x03</small></td>
537 50 olivier.gi 
<td><font size="-5">HWBRK3_PND</font></td>
538 
<td><font size="-5">HWBRK2_PND</font></td>
539 
<td><font size="-5">HWBRK1_PND</font></td>
540 
<td><font size="-5">HWBRK0_PND</font></td>
541 
<td><font size="-5">SWBRK_PND</font></td>
542 
<td><font size="-5">PUC_PND</font></td>
543 
<td><font size="-5">Res.</font></td>
544 
<td><font size="-5">HALT_RUN</font></td>
545 
</tr>
546 135 olivier.gi 
</tbody></table>
547 
<br>
548 50 olivier.gi 
<table border="0">
549 135 olivier.gi 
<tbody><tr>
550 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>HWBRK3_PND</b></li></td>
551 166 olivier.gi 
   <td>: This bit reflects if one of the Hardware Breakpoint Unit 3 status bit is set (i.e. BRK3_STAT≠0).</td>
552 50 olivier.gi 
</tr>
553 
<tr>
554 
   <td>&nbsp;</td><td valign="top"><li><b>HWBRK2_PND</b></li></td>
555 166 olivier.gi 
   <td>: This bit reflects if one of the Hardware Breakpoint Unit 2 status bit is set (i.e. BRK2_STAT≠0).</td>
556 50 olivier.gi 
</tr>
557 
<tr>
558 
   <td>&nbsp;</td><td valign="top"><li><b>HWBRK1_PND</b></li></td>
559 166 olivier.gi 
   <td>: This bit reflects if one of the Hardware Breakpoint Unit 1 status bit is set (i.e. BRK1_STAT≠0).</td>
560 50 olivier.gi 
</tr>
561 
<tr>
562 
   <td>&nbsp;</td><td valign="top"><li><b>HWBRK0_PND</b></li></td>
563 166 olivier.gi 
   <td>: This bit reflects if one of the Hardware Breakpoint Unit 0 status bit is set (i.e. BRK0_STAT≠0).</td>
564 50 olivier.gi 
</tr>
565 
<tr>
566 
   <td>&nbsp;</td><td valign="top"><li><b>SWBRK_PND</b></li></td>
567 
   <td>: This bit is set to 1 when a software breakpoint occurred. It can be cleared by writing 1 to it.</td>
568 
</tr>
569 
<tr>
570 
   <td>&nbsp;</td><td valign="top"><li><b>PUC_PND</b></li></td>
571 
   <td>: This bit is set to 1 when a PUC reset occured. It can be cleared by writing 1 to it.</td>
572 
</tr>
573 
<tr>
574 
   <td>&nbsp;</td><td valign="top"><li><b>HALT_RUN</b></li></td>
575 
   <td>: This read-only bit gives the current status of the CPU:
576 
   </td>
577 
</tr>
578 
<tr>
579 
   <td>&nbsp;</td><td>&nbsp;</td>
580 
   <td>&nbsp;&nbsp;&nbsp;0 - CPU is running.
581 135 olivier.gi 
         <br>&nbsp;&nbsp;&nbsp;1 - CPU is stopped.
582 50 olivier.gi 
   </td>
583 
</tr>
584 135 olivier.gi 
</tbody></table>
585 166 olivier.gi 
<a name="2.2.4 CPU_NR"></a>
586 
<h3>2.2.4 CPU_NR</h3>
587 50 olivier.gi 
 
588 166 olivier.gi 
This 16 bit read only register gives useful information for multi-core systems.
589 
<br>
590 
<br>
591 
 
592 
<table border="1">
593 
 
594 
<tbody><tr align="center">
595 
<td rowspan="2"><b><small>Register Name</small></b></td>
596 
<td rowspan="2"><b><small>Address</small></b></td>
597 
<td colspan="16"><b><small>Bit Field</small></b></td>
598 
</tr>
599 
<tr align="center">
600 
<td><small>15</small></td><td><small>14</small></td>
601 
<td><small>13</small></td><td><small>12</small></td>
602 
<td><small>11</small></td><td><small>10</small></td>
603 
<td><small> 9</small></td><td><small> 8</small></td>
604 
<td><small> 7</small></td><td><small> 6</small></td>
605 
<td><small> 5</small></td><td><small> 4</small></td>
606 
<td><small> 3</small></td><td><small> 2</small></td>
607 
<td><small> 1</small></td><td><small> 0</small></td>
608 
</tr>
609 
    <tr>
610 
      <td style="vertical-align: top; text-align: center;"><small>CPU_NR</small></td>
611 
      <td style="vertical-align: top; text-align: center;"><small>0x18</small></td>
612 
      <td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_TOTAL_NR</font></td>
613 
      <td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_INST_NR</font></td>
614 
    </tr>
615 
 
616 
 
617 
</tbody>
618 
</table>
619 
 
620 
<br>
621 
 
622 
<table border="0">
623 
 
624 
<tbody><tr>
625 
   <td>&nbsp;</td><td valign="top"><li><b>CPU_TOTAL_NR</b></li></td>
626 
   <td>: <span style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium; display: inline ! important; float: none;">Total number of oMSP instances -1 (for multicore systems)</span>.</td>
627 
</tr>
628 
<tr>
629 
   <td>&nbsp;</td><td valign="top"><li><b>CPU_INST_NR</b></li></td>
630 
   <td>: <span style="color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; font-size: medium; display: inline ! important; float: none;">Current oMSP instance number (for multicore systems)</span>.</td>
631 
</tr>
632 
 
633 
 
634 
 
635 
 
636 
 
637 
 
638 
</tbody>
639 
</table>
640 50 olivier.gi 
<a name="2.3 Memory Access Registers"></a>
641 135 olivier.gi 
<div style="text-align: right;"><a href="#TOC">Top</a></div>
642 50 olivier.gi 
<h2>2.3 Memory Access Registers</h2>
643 
 
644 
The following four registers enable single and burst read/write access to both CPU-Registers and full memory address range.
645 135 olivier.gi 
<br>In order to perform an access, the following sequences are typically done:
646 50 olivier.gi 
<ul>
647 
   <li>single read access (MEM_CNT=0):</li>
648 
        <ol>
649 
        <li>set MEM_ADDR with the memory address (or register number) to be read</li>
650 
                <li>set MEM_CTL (in particular RD/WR=0 and START=1)</li>
651 
                <li>read MEM_DATA</li>
652 
        </ol>
653 
        <li>single write access (MEM_CNT=0):</li>
654 
        <ol>
655 
        <li>set MEM_ADDR with the memory address (or register number) to be written</li>
656 
                <li>set MEM_DATA with the data to be written</li>
657 
                <li>set MEM_CTL (in particular RD/WR=1 and START=1)</li>
658 
        </ol>
659 166 olivier.gi 
   <li>burst read/write access (MEM_CNT≠0):</li>
660 50 olivier.gi 
        <ul>
661 
        <li>burst access are optimized for the communication interface used (i.e. for the UART).
662 135 olivier.gi 
        The burst sequence are therefore described in the corresponding section (<a href="#3.4%20Read/Write%20burst%20implementation%20for%20the%20CPU%20Memory%20access">3.4 Read/Write burst implementation for the CPU Memory access</a>)</li>
663 50 olivier.gi 
        </ul>
664 
</ul>
665 
<a name="2.3.1 MEM_CTL"></a>
666 135 olivier.gi 
<h3>2.3.1 MEM_CTL</h3>This 8 bit read-write register is used to control
667 
the Memory and CPU-Register read/write access. After a POR, this
668 
register is set to 0x00.
669 
<br><br>
670 50 olivier.gi 
<table border="1">
671 135 olivier.gi 
<tbody><tr align="center">
672 
<td rowspan="2"><b><small>Register Name</small></b></td>
673 
<td rowspan="2"><b><small>Address</small></b></td>
674 
<td colspan="16"><b><small>Bit Field</small></b></td>
675 50 olivier.gi 
</tr>
676 
<tr align="center">
677 135 olivier.gi 
<td><small> 7</small></td><td><small> 6</small></td>
678 
<td><small> 5</small></td><td><small> 4</small></td>
679 
<td><small> 3</small></td><td><small> 2</small></td>
680 
<td><small> 1</small></td><td><small> 0</small></td>
681 50 olivier.gi 
</tr>
682 
<tr align="center">
683 135 olivier.gi 
<td><small>MEM_CTL</small></td>
684 
<td><small>0x04</small></td>
685 50 olivier.gi 
<td colspan="4"><font size="-5">Reserved</font></td>
686 
<td><font size="-5">B/W</font></td>
687 
<td><font size="-5">MEM/REG</font></td>
688 
<td><font size="-5">RD/WR</font></td>
689 
<td><font size="-5">START</font></td>
690 
</tr>
691 135 olivier.gi 
</tbody></table>
692 
<br>
693 50 olivier.gi 
<table border="0">
694 135 olivier.gi 
<tbody><tr>
695 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>B/W</b></li></td>
696 
   <td>: 0 - 16 bit access.</td>
697 
</tr>
698 
<tr>
699 
   <td>&nbsp;</td><td>&nbsp;</td>
700 
   <td>&nbsp;&nbsp;1 - &nbsp;&nbsp;8 bit access (not valid for CPU-Registers).</td>
701 
</tr>
702 
<tr>
703 
   <td>&nbsp;</td><td valign="top"><li><b>MEM/REG</b></li></td>
704 
   <td>: 0 - Memory access.</td>
705 
</tr>
706 
<tr>
707 
   <td>&nbsp;</td><td>&nbsp;</td>
708 
   <td>&nbsp;&nbsp;1 - CPU-Register access.</td>
709 
</tr>
710 
<tr>
711 
   <td>&nbsp;</td><td valign="top"><li><b>RD/WR</b></li></td>
712 
   <td>: 0 - Read access.</td>
713 
</tr>
714 
<tr>
715 
   <td>&nbsp;</td><td>&nbsp;</td>
716 
   <td>&nbsp;&nbsp;1 - Write access.</td>
717 
</tr>
718 
<tr>
719 
   <td>&nbsp;</td><td valign="top"><li><b>START</b></li></td>
720 
   <td>: 0- Do nothing</td>
721 
</tr>
722 
<tr>
723 
   <td>&nbsp;</td><td>&nbsp;</td>
724 
   <td>&nbsp;&nbsp;1 - Initiate memory transfer.</td>
725 
</tr>
726 135 olivier.gi 
</tbody></table>
727 50 olivier.gi 
 
728 
<a name="2.3.2 MEM_ADDR"></a>
729 135 olivier.gi 
<h3>2.3.2 MEM_ADDR</h3>This 16 bit read-write register specifies the
730 
Memory or CPU-Register address to be used for the next read/write
731 
transfer. After a POR, this register is set to 0x0000.
732 
<br>
733 166 olivier.gi 
<strong>Note:</strong> in case of burst (i.e. MEM_CNT≠0), this register
734 135 olivier.gi 
specifies the first address of the burst transfer and will be
735 
incremented automatically as the burst goes (by 1 for 8-bit access and
736 
by 2 for 16-bit access).
737 
<br><br>
738 50 olivier.gi 
<table border="1">
739 135 olivier.gi 
<tbody><tr align="center">
740 
<td rowspan="2"><b><small>Register Name</small></b></td>
741 
<td rowspan="2"><b><small>Address</small></b></td>
742 
<td colspan="16"><b><small>Bit Field</small></b></td>
743 50 olivier.gi 
</tr>
744 
<tr align="center">
745 135 olivier.gi 
<td><small>15</small></td><td><small>14</small></td>
746 
<td><small>13</small></td><td><small>12</small></td>
747 
<td><small>11</small></td><td><small>10</small></td>
748 
<td><small> 9</small></td><td><small> 8</small></td>
749 
<td><small> 7</small></td><td><small> 6</small></td>
750 
<td><small> 5</small></td><td><small> 4</small></td>
751 
<td><small> 3</small></td><td><small> 2</small></td>
752 
<td><small> 1</small></td><td><small> 0</small></td>
753 50 olivier.gi 
</tr>
754 
<tr align="center">
755 135 olivier.gi 
<td><small>MEM_ADDR</small></td>
756 
<td><small>0x05</small></td>
757 50 olivier.gi 
<td colspan="16"><font size="-5">MEM_ADDR[15:0]</font></td>
758 
</tr>
759 135 olivier.gi 
</tbody></table>
760 
<br>
761 50 olivier.gi 
<table border="0">
762 135 olivier.gi 
<tbody><tr>
763 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>MEM_ADDR</b></li></td>
764 
   <td>: Memory or CPU-Register address to be used for the next read/write transfer.</td>
765 
</tr>
766 135 olivier.gi 
</tbody></table>
767 50 olivier.gi 
 
768 
<a name="2.3.3 MEM_DATA"></a>
769 135 olivier.gi 
<h3>2.3.3 MEM_DATA</h3>This 16 bit read-write register gives (wr)
770 
or receive (rd) the Memory or CPU-Register data for the next
771 
transfer. After a POR, this register is set to 0x0000.
772 
<br><br>
773 50 olivier.gi 
<table border="1">
774 135 olivier.gi 
<tbody><tr align="center">
775 
<td rowspan="2"><b><small>Register Name</small></b></td>
776 
<td rowspan="2"><b><small>Address</small></b></td>
777 
<td colspan="16"><b><small>Bit Field</small></b></td>
778 50 olivier.gi 
</tr>
779 
<tr align="center">
780 135 olivier.gi 
<td><small>15</small></td><td><small>14</small></td>
781 
<td><small>13</small></td><td><small>12</small></td>
782 
<td><small>11</small></td><td><small>10</small></td>
783 
<td><small> 9</small></td><td><small> 8</small></td>
784 
<td><small> 7</small></td><td><small> 6</small></td>
785 
<td><small> 5</small></td><td><small> 4</small></td>
786 
<td><small> 3</small></td><td><small> 2</small></td>
787 
<td><small> 1</small></td><td><small> 0</small></td>
788 50 olivier.gi 
</tr>
789 
<tr align="center">
790 135 olivier.gi 
<td><small>MEM_DATA</small></td>
791 
<td><small>0x06</small></td>
792 50 olivier.gi 
<td colspan="16"><font size="-5">MEM_DATA[15:0]</font></td>
793 
</tr>
794 135 olivier.gi 
</tbody></table>
795 
<br>
796 50 olivier.gi 
<table border="0">
797 135 olivier.gi 
<tbody><tr>
798 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>MEM_DATA</b></li></td>
799 
   <td>: if MEM_CTL.WR - data to be written during the next write transfer.</td>
800 
</tr>
801 
<tr>
802 
   <td>&nbsp;</td><td>&nbsp;</td>
803 
   <td>&nbsp;&nbsp;if MEM_CTL.RD - updated with the data from the read transfer</td>
804 
</tr>
805 135 olivier.gi 
</tbody></table>
806 50 olivier.gi 
 
807 
<a name="2.3.4 MEM_CNT"></a>
808 135 olivier.gi 
<h3>2.3.4 MEM_CNT</h3>This 16 bit read-write register controls the
809 
burst access to the Memory or CPU-Registers. If set to 0, a single
810 
access will occur, otherwise, a burst will be performed. The burst
811 
being optimized for the communication interface, more details are given
812 
<a href="#3.4%20Read/Write%20burst%20implementation%20for%20the%20CPU%20Memory%20access">there</a>. After a POR, this register is set to 0x0000.
813 
<br><br>
814 50 olivier.gi 
<table border="1">
815 135 olivier.gi 
<tbody><tr align="center">
816 
<td rowspan="2"><b><small>Register Name</small></b></td>
817 
<td rowspan="2"><b><small>Address</small></b></td>
818 
<td colspan="16"><b><small>Bit Field</small></b></td>
819 50 olivier.gi 
</tr>
820 
<tr align="center">
821 135 olivier.gi 
<td><small>15</small></td><td><small>14</small></td>
822 
<td><small>13</small></td><td><small>12</small></td>
823 
<td><small>11</small></td><td><small>10</small></td>
824 
<td><small> 9</small></td><td><small> 8</small></td>
825 
<td><small> 7</small></td><td><small> 6</small></td>
826 
<td><small> 5</small></td><td><small> 4</small></td>
827 
<td><small> 3</small></td><td><small> 2</small></td>
828 
<td><small> 1</small></td><td><small> 0</small></td>
829 50 olivier.gi 
</tr>
830 
<tr align="center">
831 135 olivier.gi 
<td><small>MEM_CNT</small></td>
832 
<td><small>0x07</small></td>
833 50 olivier.gi 
<td colspan="16"><font size="-5">MEM_CNT[15:0]</font></td>
834 
</tr>
835 135 olivier.gi 
</tbody></table>
836 
<br>
837 50 olivier.gi 
<table border="0">
838 135 olivier.gi 
<tbody><tr>
839 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>MEM_CNT</b></li></td>
840 
   <td>: =0 - a single access will be performed with the next transfer.</td>
841 
</tr>
842 
<tr>
843 
   <td>&nbsp;</td><td>&nbsp;</td>
844 166 olivier.gi 
   <td>&nbsp;&nbsp;≠0 -
845 135 olivier.gi 
specifies the burst size for the next transfer (i.e number of data
846 
access). This field will be automatically decremented as the burst goes.</td>
847 50 olivier.gi 
</tr>
848 135 olivier.gi 
</tbody></table>
849 50 olivier.gi 
 
850 
<a name="2.4 Hardware Breakpoint Unit Registers"></a>
851 135 olivier.gi 
<div style="text-align: right;"><a href="#TOC">Top</a></div>
852 50 olivier.gi 
<h2>2.4 Hardware Breakpoint Unit Registers</h2>
853 135 olivier.gi 
Depending on the <a href="http://opencores.org/project,openmsp430,core#2.1.3%20Configuration">defines</a>
854 
located in the "openmsp430_defines.v" file, up to four hardware
855 
breakpoint units can be included in the design. These units can be
856 
individually controlled with the following registers.
857 50 olivier.gi 
<a name="2.4.1 BRKx_CTL"></a>
858 
<h3>2.4.1 BRKx_CTL</h3>
859 
 
860 
This 8 bit read-write register controls the hardware breakpoint unit x. After a POR, this register is set to 0x00.
861 135 olivier.gi 
<br><br>
862 50 olivier.gi 
<table border="1">
863 135 olivier.gi 
<tbody><tr align="center">
864 
<td rowspan="2"><b><small>Register Name</small></b></td>
865 
<td rowspan="2"><b><small>Address</small></b></td>
866 
<td colspan="16"><b><small>Bit Field</small></b></td>
867 50 olivier.gi 
</tr>
868 
<tr align="center">
869 135 olivier.gi 
<td><small> 7</small></td><td><small> 6</small></td>
870 
<td><small> 5</small></td><td><small> 4</small></td>
871 
<td><small> 3</small></td><td><small> 2</small></td>
872 
<td><small> 1</small></td><td><small> 0</small></td>
873 50 olivier.gi 
</tr>
874 
<tr align="center">
875 135 olivier.gi 
<td><small>BRKx_CTL</small></td>
876 
<td><small>0x08, 0x0C, 0x10, 0x14</small></td>
877 50 olivier.gi 
<td colspan="3"><font size="-5">Reserved</font></td>
878 
<td><font size="-5">RANGE_MODE</font></td>
879 
<td><font size="-5">INST_EN</font></td>
880 
<td><font size="-5">BREAK_EN</font></td>
881 
<td colspan="2"><font size="-5">ACCESS_MODE</font></td>
882 
</tr>
883 135 olivier.gi 
</tbody></table>
884 
<br>
885 50 olivier.gi 
<table border="0">
886 135 olivier.gi 
<tbody><tr>
887 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>RANGE_MODE</b></li></td>
888 
   <td>:  0 - Address match on BRK_ADDR0 or BRK_ADDR1 (normal mode)</td>
889 
</tr>
890 
<tr>
891 
   <td>&nbsp;</td><td>&nbsp;</td>
892 166 olivier.gi 
   <td>&nbsp;&nbsp;1 - Address match on BRK_ADDR0→BRK_ADDR1 range (range mode)
893 135 olivier.gi 
   <br><font color="red"><b>Note</b>: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
894 
 
895 50 olivier.gi 
</tr>
896 
<tr>
897 
   <td>&nbsp;</td><td valign="top"><li><b>INST_EN</b></li></td>
898 
   <td>: 0 - Checks are done on the execution unit (data flow).</td>
899 
</tr>
900 
<tr>
901 
   <td>&nbsp;</td><td>&nbsp;</td>
902 
   <td>&nbsp;&nbsp;1 - Checks are done on the frontend (instruction flow).</td>
903 
</tr>
904 
 
905 
<tr>
906 
   <td>&nbsp;</td><td valign="top"><li><b>BREAK_EN</b></li></td>
907 
   <td>: 0 - Watchpoint mode enable (don't stop on address match).</td>
908 
</tr>
909 
<tr>
910 
   <td>&nbsp;</td><td>&nbsp;</td>
911 
   <td>&nbsp;&nbsp;1 - Breakpoint mode enable (stop on address match).</td>
912 
</tr>
913 
 
914 
<tr>
915 
   <td>&nbsp;</td><td valign="top"><li><b>ACCESS_MODE</b></li></td>
916 
   <td>: 00 - Disabled</td>
917 
</tr>
918 
<tr>
919 
   <td>&nbsp;</td><td>&nbsp;</td>
920 
   <td>  &nbsp;&nbsp;01 - Detect read access.
921 135 olivier.gi 
   <br>&nbsp;&nbsp;10 - Detect write access.
922 
   <br>&nbsp;&nbsp;11 - Detect read/write access
923 
   <br><b>Note</b>: '10' &amp; '11' modes are not supported on the instruction flow</td>
924 50 olivier.gi 
</tr>
925 135 olivier.gi 
</tbody></table>
926 50 olivier.gi 
 
927 
<a name="2.4.2 BRKx_STAT"></a>
928 135 olivier.gi 
<h3>2.4.2 BRKx_STAT</h3>This 8 bit read-write register gives the status
929 
of the hardware breakpoint unit x. Each status bit can be cleared by
930 
writing 1 to it. After a POR, this register is set to 0x00.
931 
<br><br>
932 50 olivier.gi 
<table border="1">
933 135 olivier.gi 
<tbody><tr align="center">
934 
<td rowspan="2"><b><small>Register Name</small></b></td>
935 
<td rowspan="2"><b><small>Address</small></b></td>
936 
<td colspan="16"><b><small>Bit Field</small></b></td>
937 50 olivier.gi 
</tr>
938 
<tr align="center">
939 135 olivier.gi 
<td><small> 7</small></td><td><small> 6</small></td>
940 
<td><small> 5</small></td><td><small> 4</small></td>
941 
<td><small> 3</small></td><td><small> 2</small></td>
942 
<td><small> 1</small></td><td><small> 0</small></td>
943 50 olivier.gi 
</tr>
944 
<tr align="center">
945 135 olivier.gi 
<td><small>BRKx_STAT</small></td>
946 
<td><small>0x09, 0x0D, 0x11, 0x15</small></td>
947 50 olivier.gi 
<td colspan="2"><font size="-5">Reserved</font></td>
948 
<td><font size="-5">RANGE_WR</font></td>
949 
<td><font size="-5">RANGE_RD</font></td>
950 
<td><font size="-5">ADDR1_WR</font></td>
951 
<td><font size="-5">ADDR1_RD</font></td>
952 
<td><font size="-5">ADDR0_WR</font></td>
953 
<td><font size="-5">ADDR0_RD</font></td>
954 
</tr>
955 135 olivier.gi 
</tbody></table>
956 
<br>
957 50 olivier.gi 
<table border="0">
958 135 olivier.gi 
<tbody><tr>
959 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>RANGE_WR</b></li></td>
960 135 olivier.gi 
   <td>:
961 
This bit is set whenever the CPU performs a write access within the
962 166 olivier.gi 
BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and
963 135 olivier.gi 
ACCESS_MODE[1]=1).</td>
964 50 olivier.gi 
</tr>
965 
<tr>
966 
   <td>&nbsp;</td><td valign="top"><li><b>RANGE_RD</b></li></td>
967 135 olivier.gi 
   <td>:
968 
This bit is set whenever the CPU performs a read access within the
969 166 olivier.gi 
BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and
970 135 olivier.gi 
ACCESS_MODE[0]=1). <br><font color="red"><b>Note</b>: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
971 50 olivier.gi 
</tr>
972 
<tr>
973 
   <td>&nbsp;</td><td valign="top"><li><b>ADDR1_WR</b></li></td>
974 135 olivier.gi 
   <td>:
975 
This bit is set whenever the CPU performs a write access at the
976 
BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).</td>
977 50 olivier.gi 
</tr>
978 
<tr>
979 
   <td>&nbsp;</td><td valign="top"><li><b>ADDR1_RD</b></li></td>
980 135 olivier.gi 
   <td>:
981 
This bit is set whenever the CPU performs a read access at the
982 
BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[0]=1).</td>
983 50 olivier.gi 
</tr>
984 
<tr>
985 
   <td>&nbsp;</td><td valign="top"><li><b>ADDR0_WR</b></li></td>
986 135 olivier.gi 
   <td>:
987 
This bit is set whenever the CPU performs a write access at the
988 
BRKx_ADDR0 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).</td>
989 50 olivier.gi 
</tr>
990 
<tr>
991 
   <td>&nbsp;</td><td valign="top"><li><b>ADDR0_RD</b></li></td>
992 135 olivier.gi 
   <td>:
993 
This bit is set whenever the CPU performs a read access at the
994 
BRKx_ADDR0 address (valid if RANGE_MODE=0 and ACCESS_MODE[0]=1).</td>
995 50 olivier.gi 
</tr>
996 135 olivier.gi 
</tbody></table>
997 50 olivier.gi 
 
998 
<a name="2.4.3 BRKx_ADDR0"></a>
999 
<h3>2.4.3 BRKx_ADDR0</h3>
1000 135 olivier.gi 
This 16 bit read-write register holds the value which is compared
1001 
against the address value currently present on the program or data
1002 
address bus. After a POR, this register is set to 0x0000.
1003 
<br><br>
1004 50 olivier.gi 
<table border="1">
1005 135 olivier.gi 
<tbody><tr align="center">
1006 
<td rowspan="2"><b><small>Register Name</small></b></td>
1007 
<td rowspan="2"><b><small>Address</small></b></td>
1008 
<td colspan="16"><b><small>Bit Field</small></b></td>
1009 50 olivier.gi 
</tr>
1010 
<tr align="center">
1011 135 olivier.gi 
<td><small>15</small></td><td><small>14</small></td>
1012 
<td><small>13</small></td><td><small>12</small></td>
1013 
<td><small>11</small></td><td><small>10</small></td>
1014 
<td><small> 9</small></td><td><small> 8</small></td>
1015 
<td><small> 7</small></td><td><small> 6</small></td>
1016 
<td><small> 5</small></td><td><small> 4</small></td>
1017 
<td><small> 3</small></td><td><small> 2</small></td>
1018 
<td><small> 1</small></td><td><small> 0</small></td>
1019 50 olivier.gi 
</tr>
1020 
<tr align="center">
1021 135 olivier.gi 
<td><small>BRKx_ADDR0</small></td>
1022 
<td><small>0x0A, 0x0E, 0x12, 0x16</small></td>
1023 50 olivier.gi 
<td colspan="16"><font size="-5">BRK_ADDR0[15:0]</font></td>
1024 
</tr>
1025 135 olivier.gi 
</tbody></table>
1026 
<br>
1027 50 olivier.gi 
<table border="0">
1028 135 olivier.gi 
<tbody><tr>
1029 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>BRK_ADDR0</b></li></td>
1030 
   <td>: Value compared against the address value currently present on the program or data address bus.</td>
1031 
</tr>
1032 135 olivier.gi 
</tbody></table>
1033 50 olivier.gi 
 
1034 
<a name="2.4.4 BRKx_ADDR1"></a>
1035 135 olivier.gi 
<h3>2.4.4 BRKx_ADDR1</h3>This 16 bit read-write register holds the
1036 
value which is compared against the address value currently present on
1037 
the program or data address bus. After a POR, this register is set to
1038 
0x0000.
1039 
<br><br>
1040 50 olivier.gi 
<table border="1">
1041 135 olivier.gi 
<tbody><tr align="center">
1042 
<td rowspan="2"><b><small>Register Name</small></b></td>
1043 
<td rowspan="2"><b><small>Addresses</small></b></td>
1044 
<td colspan="16"><b><small>Bit Field</small></b></td>
1045 50 olivier.gi 
</tr>
1046 
<tr align="center">
1047 135 olivier.gi 
<td><small>15</small></td><td><small>14</small></td>
1048 
<td><small>13</small></td><td><small>12</small></td>
1049 
<td><small>11</small></td><td><small>10</small></td>
1050 
<td><small> 9</small></td><td><small> 8</small></td>
1051 
<td><small> 7</small></td><td><small> 6</small></td>
1052 
<td><small> 5</small></td><td><small> 4</small></td>
1053 
<td><small> 3</small></td><td><small> 2</small></td>
1054 
<td><small> 1</small></td><td><small> 0</small></td>
1055 50 olivier.gi 
</tr>
1056 
<tr align="center">
1057 135 olivier.gi 
<td><small>BRKx_ADDR1</small></td>
1058 
<td><small>0x0B, 0x0F, 0x13, 0x17</small></td>
1059 50 olivier.gi 
<td colspan="16"><font size="-5">BRK_ADDR1[15:0]</font></td>
1060 
</tr>
1061 135 olivier.gi 
</tbody></table>
1062 
<br>
1063 50 olivier.gi 
<table border="0">
1064 135 olivier.gi 
<tbody><tr>
1065 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>BRK_ADDR1</b></li></td>
1066 
   <td>: Value compared against the address value currently present on the program or data address bus.</td>
1067 
</tr>
1068 135 olivier.gi 
</tbody></table>
1069 50 olivier.gi 
 
1070 
<a name="3. Debug Communication Interface: UART"></a>
1071 135 olivier.gi 
<div style="text-align: right;"><a href="#TOC">Top</a></div>
1072 
<h1>3. Debug Communication Interface: UART</h1>With its UART interface,
1073 
the openMSP430 debug unit can communicate with the host computer using
1074 
a simple RS232 cable (connected to the <a href="http://opencores.org/project,openmsp430,core#2.1.5%20Pinout">dbg_uart_txd</a> and <a href="http://opencores.org/project,openmsp430,core#2.1.5%20Pinout">dbg_uart_rxd</a> ports of the IP).<br>Typically, a <a href="http://www.google.com/search?q=usb+to+rs232+converter">USB to RS232</a> or <a href="http://www.ftdichip.com/Products/Cables/USBTTLSerial.htm">USB to serial TTL</a>
1075 166 olivier.gi 
cable will provides a reliable communication link between your host PC
1076 135 olivier.gi 
and the openMSP430 (speed being typically limited by the cable length).
1077 50 olivier.gi 
<a name="3.1 Serial communication protocol: 8N1"></a>
1078 
<h2>3.1 Serial communication protocol: 8N1</h2>
1079 135 olivier.gi 
There are plenty tutorials on Internet regarding RS232 based protocols.
1080 
However, here is quick recap about 8N1 (1 Start bit, 8 Data bits, No
1081 
Parity, 1 Stop bit):<br>
1082 
<br>
1083 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1247419201" alt="8N1 Serial Protocol" title="8N1 Serial Protocol">
1084 135 olivier.gi 
<br>
1085 
As you can see in the above diagram, data transmission starts with a
1086 
Start bit, followed by the data bits (LSB sent first and MSB sent
1087 
last), and ends with a "Stop" bit.
1088 50 olivier.gi 
<a name="3.2 Synchronization frame"></a>
1089 135 olivier.gi 
<h2>3.2 Synchronization frame</h2>After a POR, the Serial Debug
1090 
Interface expects a synchronization frame from the host computer in
1091 
order to determine the communication speed (i.e. the baud rate).<br>
1092 50 olivier.gi 
The synchronization frame looks as following:
1093 135 olivier.gi 
<br>
1094 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1247420610" alt="Debug Synchronization Frame" title="Debug Synchronization Frame">
1095 135 olivier.gi 
<br>
1096 
As you can see, the host simply sends the 0x80 value. The openMSP430
1097 
will then measure the time between the falling and rising edge, divide
1098 
it by 8 and automatically deduce the baud rate it should use to
1099 
properly communicate with the host.
1100 
<br><br>
1101 
<b>Important note</b>: if you want to change the communication speed
1102 
between two debugging sessions, the Serial Debug Interface needs to go through a reset cycle (i.e. through the <span style="font-style: italic;">reset_n</span> or <span style="font-style: italic;">dbg_en</span> pins) and a new synchronization frame needs to be send.
1103 
<br>
1104 50 olivier.gi 
<a name="3.3 Read/Write access to the debug registers"></a>
1105 
<h2>3.3 Read/Write access to the debug registers</h2>
1106 135 olivier.gi 
In order to perform a read / write access to a debug register, the host needs to send a command frame to the openMSP430.<br>In
1107 
case of write access, this command frame will be followed by 1 or 2
1108 
data frames and in case of read access, the openMSP430 will send 1 or 2
1109 
data frames after receiving the command.
1110 50 olivier.gi 
<a name="3.3.1 Command Frame"></a>
1111 
<h3>3.3.1 Command Frame</h3>
1112 
The command frame looks as following:
1113 135 olivier.gi 
<br>
1114 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1247427400" alt="Debug Command Frame" title="Debug Command Frame">
1115 135 olivier.gi 
<br>
1116 50 olivier.gi 
<table border="0">
1117 135 olivier.gi 
<tbody><tr>
1118 50 olivier.gi 
   <td>&nbsp;</td><td valign="top"><li><b>WR</b></li></td>
1119 
   <td>: Perform a Write access when set. Read otherwise.</td>
1120 
</tr>
1121 
<tr>
1122 
   <td>&nbsp;</td><td valign="top"><li><b>B/W</b></li></td>
1123 135 olivier.gi 
   <td>: Perform a 8-bit data access when set (one data frame). 16-bit otherwise (two data frame).</td></tr><tr>
1124 50 olivier.gi 
</tr>
1125 
<tr>
1126 
   <td>&nbsp;</td><td valign="top"><li><b>Address</b></li></td>
1127 135 olivier.gi 
   <td>: Debug register address.</td></tr><tr>
1128 50 olivier.gi 
</tr>
1129 135 olivier.gi 
</tbody></table>
1130 50 olivier.gi 
 
1131 
<a name="3.3.2 Write access"></a>
1132 
<h3>3.3.2 Write access</h3>
1133 
A write access transaction looks like this:
1134 135 olivier.gi 
<br>
1135 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1247428987" alt="Debug Write Transaction" title="Debug Write Transaction">
1136 50 olivier.gi 
 
1137 
<a name="3.3.3 Read access"></a>
1138 
<h3>3.3.3 Read access</h3>
1139 
A read access transaction looks like this:
1140 135 olivier.gi 
<br>
1141 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1247429086" alt="Debug Read Transaction" title="Debug Read Transaction">
1142 50 olivier.gi 
 
1143 
<a name="3.4 Read/Write burst implementation for the CPU Memory access"></a>
1144 135 olivier.gi 
<h2>3.4 Read/Write burst implementation for the CPU Memory access</h2>In
1145 
order to optimize the data burst transactions for the UART, read/write
1146 
access are not done by reading or writing the MEM_DATA register.<br>
1147 50 olivier.gi 
Instead, the data transfer starts immediately after the MEM_CTL.START bit has been set.
1148 
 
1149 
<a name="3.4.1 Write Burst access"></a>
1150 
<h3>3.4.1 Write Burst access</h3>
1151 
A write burst transaction looks like this:
1152 135 olivier.gi 
<br>
1153 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1247430408" alt="Debug Write Burst Transaction" title="Debug Write Burst Transaction">
1154 50 olivier.gi 
 
1155 
<a name="3.4.2 Read Burst access"></a>
1156 
<h3>3.4.2 Read Burst access</h3>
1157 
A read burst transaction looks like this:
1158 135 olivier.gi 
<br>
1159 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1247430449" alt="Debug Read Burst Transaction" title="Debug Read Burst Transaction">
1160 50 olivier.gi 
 
1161 166 olivier.gi 
<a name="4. Debug Communication Interface: I2C"></a>
1162 135 olivier.gi 
<div style="text-align: right;"><a href="#TOC">Top</a></div>
1163 166 olivier.gi 
<h1>4. Debug Communication Interface: I2C</h1>
1164 
With its I2C interface, the openMSP430 debug unit can communicate with the host computer using
1165 
an I2C adapter (connected to the <a href="http://opencores.org/project,openmsp430,core#2.1.5%20Pinout">dbg_i2c_scl</a> and <a href="http://opencores.org/project,openmsp430,core#2.1.5%20Pinout">dbg_i2c_sda_in / dbg_i2c_sda_out</a> ports of the IP).<br>Currently, the <a href="http://www.robot-electronics.co.uk/acatalog/USB_I2C.html">USB-ISS</a>
1166 
adapter from Devantech (Robot Electronics) is supported by the software
1167 
development tools and provides a reliable communication link between
1168 
your host PC
1169 
and the openMSP430.
1170 
<a name="4.1 I2C communication protocol"></a>
1171 
<h2>4.1 I2C communication protocol</h2>
1172 
There are plenty tutorials on Internet regarding the I2C protocol (see the official <a href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I2C specification</a> for more info).<br>
1173 
A simple byte read or write frame looks as following:<br>
1174 
<br>
1175 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1352582784" alt="I2C Protocol" title="I2C Protocol" width="80%">
1176 166 olivier.gi 
<br><a name="4.2 Synchronization frame"></a>
1177 
<h2>4.2 Synchronization frame</h2>
1178 
Unlike the UART interface, the I2C is a synchronous communication protocol.<br>
1179 
A synchronization frame is therefore not required.<br><br>
1180 
 
1181 
<a name="4.3 Read/Write access to the debug registers"></a>
1182 
<h2>4.3 Read/Write access to the debug registers</h2>
1183 
In order to perform a read / write access to a debug register, the host needs to send a command frame to the openMSP430.<br>In
1184 
case of write access, this command frame will be followed by 1 or 2
1185 
data frames and in case of read access, the openMSP430 will send 1 or 2
1186 
data frames after receiving the command.
1187 
<a name="4.3.1 Command Frame"></a>
1188 
<h3>4.3.1 Command Frame</h3>
1189 
The command frame looks as following:
1190 
<br>
1191 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1352584261" alt="Debug command frame" title="Debug command frame" width="100%">
1192 166 olivier.gi 
<br>
1193 
<table border="0">
1194 
<tbody><tr>
1195 
   <td>&nbsp;</td><td valign="top"><li><b>WR</b></li></td>
1196 
   <td>: Perform a Write access when set. Read otherwise.</td>
1197 
</tr>
1198 
<tr>
1199 
   <td>&nbsp;</td><td valign="top"><li><b>B/W</b></li></td>
1200 
   <td>: Perform a 8-bit data access when set (one data frame). 16-bit otherwise (two data frame).</td></tr><tr>
1201 
</tr>
1202 
<tr>
1203 
   <td>&nbsp;</td><td valign="top"><li><b>Address</b></li></td>
1204 
   <td>: Debug register address.</td></tr><tr>
1205 
</tr>
1206 
</tbody></table>
1207 
 
1208 
<a name="4.3.2 Write access"></a>
1209 
<h3>4.3.2 Write access</h3>
1210 
A write access transaction looks like this:
1211 
<br>
1212 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1352586896" alt="I2C Debug Write Transaction" title="I2C Debug Write Transaction" width="100%">
1213 166 olivier.gi 
 
1214 
<a name="4.3.3 Read access"></a>
1215 
<h3>4.3.3 Read access</h3>
1216 
A read access transaction looks like this:
1217 
<br>
1218 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1352586064" alt="I2C Debug Read Transaction" title="I2C Debug Read Transaction" width="100%">
1219 166 olivier.gi 
 
1220 
<a name="4.4 Read/Write burst implementation for the CPU Memory access"></a>
1221 
<h2>4.4 Read/Write burst implementation for the CPU Memory access</h2>In
1222 
order to optimize the data burst transactions for the I2C, read/write
1223 
access are not done by reading or writing the MEM_DATA register.<br>
1224 
Instead, the data transfer starts immediately after the MEM_CTL.START bit has been set.
1225 
 
1226 
<a name="4.4.1 Write Burst access"></a>
1227 
<h3>4.4.1 Write Burst access</h3>
1228 
A write burst transaction looks like this:
1229 
<br>
1230 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1352673100" alt="I2C Debug Write Burst Transaction" title="I2C Debug Write Burst Transaction" width="100%">
1231 166 olivier.gi 
 
1232 
<a name="4.4.2 Read Burst access"></a>
1233 
<h3>4.4.2 Read Burst access</h3>
1234 
A read burst transaction looks like this:
1235 
<br>
1236 202 olivier.gi 
<img src="http://opencores.org/usercontent,img,1352672466" alt="I2C Debug Read Burst Transaction" title="I2C Debug Read Burst Transaction" width="100%">
1237 166 olivier.gi 
 
1238 
<div style="text-align: right;"><a href="#TOC">Top</a></div>
1239 
 
1240 135 olivier.gi 
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