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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_ADC.htm] - Blame information for rev 221

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Line No. Rev Author Line
1 221 olivier.gi
<html>
2
<body>
3
<h1 align="center">DE0-Nano-SoC Board Configuration</h1>
4
<br />
5
<br />
6
<h2 align="left">Pin Assignments:</h2>
7
<ul>
8
<a href="#ADC"><li>ADC</li></a>
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<br />
10
<a href="#CLOCK"><li>CLOCK</li></a>
11
<br />
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<a href="#HPS"><li>HPS</li></a>
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<br />
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<a href="#KEY"><li>KEY</li></a>
15
<br />
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<a href="#LED"><li>LED</li></a>
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<br />
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<a href="#SW"><li>SW</li></a>
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<br />
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<a href="#GPIO_0"><li>GPIO_0</li></a>
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<br />
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<a href="#GPIO_1"><li>GPIO_1</li></a>
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<br />
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</ul>
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<br />
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<br />
27
<br />
28
<h2 align="left">Pin Assignment Table:</h2>
29
<h2><a name="ADC"></a></h2><table border="3">
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<caption  align="left">ADC</caption>
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<br />
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<br />
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<tr>
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   <th align="left" bgcolor="Khaki">Name</th>
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   <th align="left" bgcolor="Khaki">Location</th>
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   <th align="left" bgcolor="Khaki">Direction</th>
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   <th align="left" bgcolor="Khaki">Standard</th>
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</tr>
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<tr>
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   <td align="left">ADC_CONVST</td>
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   <td align="left">U9</td>
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   <td align="left">output</td>
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   <td align="left">3.3-V LVTTL</td>
44
</tr>
45
<tr>
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   <td align="left">ADC_SCK</td>
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   <td align="left">V10</td>
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   <td align="left">output</td>
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   <td align="left">3.3-V LVTTL</td>
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</tr>
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<tr>
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   <td align="left">ADC_SDI</td>
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   <td align="left">AC4</td>
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   <td align="left">output</td>
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   <td align="left">3.3-V LVTTL</td>
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</tr>
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<tr>
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   <td align="left">ADC_SDO</td>
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   <td align="left">AD4</td>
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   <td align="left">input </td>
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   <td align="left">3.3-V LVTTL</td>
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</tr>
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</table>
64
<h2><a name="CLOCK"></a></h2><table border="3">
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<caption  align="left">CLOCK</caption>
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<br />
67
<br />
68
<tr>
69
   <th align="left" bgcolor="Khaki">Name</th>
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   <th align="left" bgcolor="Khaki">Location</th>
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   <th align="left" bgcolor="Khaki">Direction</th>
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   <th align="left" bgcolor="Khaki">Standard</th>
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</tr>
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<tr>
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   <td align="left">FPGA_CLK1_50</td>
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   <td align="left">V11</td>
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   <td align="left">input </td>
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   <td align="left">3.3-V LVTTL</td>
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</tr>
80
<tr>
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   <td align="left">FPGA_CLK2_50</td>
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   <td align="left">Y13</td>
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   <td align="left">input </td>
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   <td align="left">3.3-V LVTTL</td>
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</tr>
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<tr>
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   <td align="left">FPGA_CLK3_50</td>
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   <td align="left">E11</td>
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   <td align="left">input </td>
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   <td align="left">3.3-V LVTTL</td>
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</tr>
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</table>
93
<h2><a name="HPS"></a></h2><table border="3">
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<caption  align="left">HPS</caption>
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<br />
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<br />
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<tr>
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   <th align="left" bgcolor="Khaki">Name</th>
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   <th align="left" bgcolor="Khaki">Location</th>
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   <th align="left" bgcolor="Khaki">Direction</th>
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   <th align="left" bgcolor="Khaki">Standard</th>
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</tr>
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<tr>
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   <td align="left">HPS_CONV_USB_N</td>
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   <td align="left"></td>
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   <td align="left">inout </td>
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   <td align="left">3.3-V LVTTL</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[0]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[1]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[2]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[3]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[4]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[5]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[6]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[7]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[8]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[9]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[10]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[11]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[12]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[13]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_ADDR[14]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_BA[0]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_BA[1]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_BA[2]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_CAS_N</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_CKE</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_CK_N</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">Differential 1.5-V SSTL Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_CK_P</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">Differential 1.5-V SSTL Class I</td>
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</tr>
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<tr>
242
   <td align="left">HPS_DDR3_CS_N</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_DM[0]</td>
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   <td align="left"></td>
250
   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_DM[1]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_DM[2]</td>
261
   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_DM[3]</td>
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   <td align="left"></td>
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   <td align="left">output</td>
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   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
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   <td align="left">HPS_DDR3_DQ[0]</td>
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   <td align="left"></td>
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   <td align="left">inout </td>
275
   <td align="left">SSTL-15 Class I</td>
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</tr>
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<tr>
278
   <td align="left">HPS_DDR3_DQ[1]</td>
279
   <td align="left"></td>
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   <td align="left">inout </td>
281
   <td align="left">SSTL-15 Class I</td>
282
</tr>
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<tr>
284
   <td align="left">HPS_DDR3_DQ[2]</td>
285
   <td align="left"></td>
286
   <td align="left">inout </td>
287
   <td align="left">SSTL-15 Class I</td>
288
</tr>
289
<tr>
290
   <td align="left">HPS_DDR3_DQ[3]</td>
291
   <td align="left"></td>
292
   <td align="left">inout </td>
293
   <td align="left">SSTL-15 Class I</td>
294
</tr>
295
<tr>
296
   <td align="left">HPS_DDR3_DQ[4]</td>
297
   <td align="left"></td>
298
   <td align="left">inout </td>
299
   <td align="left">SSTL-15 Class I</td>
300
</tr>
301
<tr>
302
   <td align="left">HPS_DDR3_DQ[5]</td>
303
   <td align="left"></td>
304
   <td align="left">inout </td>
305
   <td align="left">SSTL-15 Class I</td>
306
</tr>
307
<tr>
308
   <td align="left">HPS_DDR3_DQ[6]</td>
309
   <td align="left"></td>
310
   <td align="left">inout </td>
311
   <td align="left">SSTL-15 Class I</td>
312
</tr>
313
<tr>
314
   <td align="left">HPS_DDR3_DQ[7]</td>
315
   <td align="left"></td>
316
   <td align="left">inout </td>
317
   <td align="left">SSTL-15 Class I</td>
318
</tr>
319
<tr>
320
   <td align="left">HPS_DDR3_DQ[8]</td>
321
   <td align="left"></td>
322
   <td align="left">inout </td>
323
   <td align="left">SSTL-15 Class I</td>
324
</tr>
325
<tr>
326
   <td align="left">HPS_DDR3_DQ[9]</td>
327
   <td align="left"></td>
328
   <td align="left">inout </td>
329
   <td align="left">SSTL-15 Class I</td>
330
</tr>
331
<tr>
332
   <td align="left">HPS_DDR3_DQ[10]</td>
333
   <td align="left"></td>
334
   <td align="left">inout </td>
335
   <td align="left">SSTL-15 Class I</td>
336
</tr>
337
<tr>
338
   <td align="left">HPS_DDR3_DQ[11]</td>
339
   <td align="left"></td>
340
   <td align="left">inout </td>
341
   <td align="left">SSTL-15 Class I</td>
342
</tr>
343
<tr>
344
   <td align="left">HPS_DDR3_DQ[12]</td>
345
   <td align="left"></td>
346
   <td align="left">inout </td>
347
   <td align="left">SSTL-15 Class I</td>
348
</tr>
349
<tr>
350
   <td align="left">HPS_DDR3_DQ[13]</td>
351
   <td align="left"></td>
352
   <td align="left">inout </td>
353
   <td align="left">SSTL-15 Class I</td>
354
</tr>
355
<tr>
356
   <td align="left">HPS_DDR3_DQ[14]</td>
357
   <td align="left"></td>
358
   <td align="left">inout </td>
359
   <td align="left">SSTL-15 Class I</td>
360
</tr>
361
<tr>
362
   <td align="left">HPS_DDR3_DQ[15]</td>
363
   <td align="left"></td>
364
   <td align="left">inout </td>
365
   <td align="left">SSTL-15 Class I</td>
366
</tr>
367
<tr>
368
   <td align="left">HPS_DDR3_DQ[16]</td>
369
   <td align="left"></td>
370
   <td align="left">inout </td>
371
   <td align="left">SSTL-15 Class I</td>
372
</tr>
373
<tr>
374
   <td align="left">HPS_DDR3_DQ[17]</td>
375
   <td align="left"></td>
376
   <td align="left">inout </td>
377
   <td align="left">SSTL-15 Class I</td>
378
</tr>
379
<tr>
380
   <td align="left">HPS_DDR3_DQ[18]</td>
381
   <td align="left"></td>
382
   <td align="left">inout </td>
383
   <td align="left">SSTL-15 Class I</td>
384
</tr>
385
<tr>
386
   <td align="left">HPS_DDR3_DQ[19]</td>
387
   <td align="left"></td>
388
   <td align="left">inout </td>
389
   <td align="left">SSTL-15 Class I</td>
390
</tr>
391
<tr>
392
   <td align="left">HPS_DDR3_DQ[20]</td>
393
   <td align="left"></td>
394
   <td align="left">inout </td>
395
   <td align="left">SSTL-15 Class I</td>
396
</tr>
397
<tr>
398
   <td align="left">HPS_DDR3_DQ[21]</td>
399
   <td align="left"></td>
400
   <td align="left">inout </td>
401
   <td align="left">SSTL-15 Class I</td>
402
</tr>
403
<tr>
404
   <td align="left">HPS_DDR3_DQ[22]</td>
405
   <td align="left"></td>
406
   <td align="left">inout </td>
407
   <td align="left">SSTL-15 Class I</td>
408
</tr>
409
<tr>
410
   <td align="left">HPS_DDR3_DQ[23]</td>
411
   <td align="left"></td>
412
   <td align="left">inout </td>
413
   <td align="left">SSTL-15 Class I</td>
414
</tr>
415
<tr>
416
   <td align="left">HPS_DDR3_DQ[24]</td>
417
   <td align="left"></td>
418
   <td align="left">inout </td>
419
   <td align="left">SSTL-15 Class I</td>
420
</tr>
421
<tr>
422
   <td align="left">HPS_DDR3_DQ[25]</td>
423
   <td align="left"></td>
424
   <td align="left">inout </td>
425
   <td align="left">SSTL-15 Class I</td>
426
</tr>
427
<tr>
428
   <td align="left">HPS_DDR3_DQ[26]</td>
429
   <td align="left"></td>
430
   <td align="left">inout </td>
431
   <td align="left">SSTL-15 Class I</td>
432
</tr>
433
<tr>
434
   <td align="left">HPS_DDR3_DQ[27]</td>
435
   <td align="left"></td>
436
   <td align="left">inout </td>
437
   <td align="left">SSTL-15 Class I</td>
438
</tr>
439
<tr>
440
   <td align="left">HPS_DDR3_DQ[28]</td>
441
   <td align="left"></td>
442
   <td align="left">inout </td>
443
   <td align="left">SSTL-15 Class I</td>
444
</tr>
445
<tr>
446
   <td align="left">HPS_DDR3_DQ[29]</td>
447
   <td align="left"></td>
448
   <td align="left">inout </td>
449
   <td align="left">SSTL-15 Class I</td>
450
</tr>
451
<tr>
452
   <td align="left">HPS_DDR3_DQ[30]</td>
453
   <td align="left"></td>
454
   <td align="left">inout </td>
455
   <td align="left">SSTL-15 Class I</td>
456
</tr>
457
<tr>
458
   <td align="left">HPS_DDR3_DQ[31]</td>
459
   <td align="left"></td>
460
   <td align="left">inout </td>
461
   <td align="left">SSTL-15 Class I</td>
462
</tr>
463
<tr>
464
   <td align="left">HPS_DDR3_DQS_N[0]</td>
465
   <td align="left"></td>
466
   <td align="left">inout </td>
467
   <td align="left">Differential 1.5-V SSTL Class I</td>
468
</tr>
469
<tr>
470
   <td align="left">HPS_DDR3_DQS_N[1]</td>
471
   <td align="left"></td>
472
   <td align="left">inout </td>
473
   <td align="left">Differential 1.5-V SSTL Class I</td>
474
</tr>
475
<tr>
476
   <td align="left">HPS_DDR3_DQS_N[2]</td>
477
   <td align="left"></td>
478
   <td align="left">inout </td>
479
   <td align="left">Differential 1.5-V SSTL Class I</td>
480
</tr>
481
<tr>
482
   <td align="left">HPS_DDR3_DQS_N[3]</td>
483
   <td align="left"></td>
484
   <td align="left">inout </td>
485
   <td align="left">Differential 1.5-V SSTL Class I</td>
486
</tr>
487
<tr>
488
   <td align="left">HPS_DDR3_DQS_P[0]</td>
489
   <td align="left"></td>
490
   <td align="left">inout </td>
491
   <td align="left">Differential 1.5-V SSTL Class I</td>
492
</tr>
493
<tr>
494
   <td align="left">HPS_DDR3_DQS_P[1]</td>
495
   <td align="left"></td>
496
   <td align="left">inout </td>
497
   <td align="left">Differential 1.5-V SSTL Class I</td>
498
</tr>
499
<tr>
500
   <td align="left">HPS_DDR3_DQS_P[2]</td>
501
   <td align="left"></td>
502
   <td align="left">inout </td>
503
   <td align="left">Differential 1.5-V SSTL Class I</td>
504
</tr>
505
<tr>
506
   <td align="left">HPS_DDR3_DQS_P[3]</td>
507
   <td align="left"></td>
508
   <td align="left">inout </td>
509
   <td align="left">Differential 1.5-V SSTL Class I</td>
510
</tr>
511
<tr>
512
   <td align="left">HPS_DDR3_ODT</td>
513
   <td align="left"></td>
514
   <td align="left">output</td>
515
   <td align="left">SSTL-15 Class I</td>
516
</tr>
517
<tr>
518
   <td align="left">HPS_DDR3_RAS_N</td>
519
   <td align="left"></td>
520
   <td align="left">output</td>
521
   <td align="left">SSTL-15 Class I</td>
522
</tr>
523
<tr>
524
   <td align="left">HPS_DDR3_RESET_N</td>
525
   <td align="left"></td>
526
   <td align="left">output</td>
527
   <td align="left">SSTL-15 Class I</td>
528
</tr>
529
<tr>
530
   <td align="left">HPS_DDR3_RZQ</td>
531
   <td align="left"></td>
532
   <td align="left">input </td>
533
   <td align="left">1.5 V</td>
534
</tr>
535
<tr>
536
   <td align="left">HPS_DDR3_WE_N</td>
537
   <td align="left"></td>
538
   <td align="left">output</td>
539
   <td align="left">SSTL-15 Class I</td>
540
</tr>
541
<tr>
542
   <td align="left">HPS_ENET_GTX_CLK</td>
543
   <td align="left"></td>
544
   <td align="left">output</td>
545
   <td align="left">3.3-V LVTTL</td>
546
</tr>
547
<tr>
548
   <td align="left">HPS_ENET_INT_N</td>
549
   <td align="left"></td>
550
   <td align="left">inout </td>
551
   <td align="left">3.3-V LVTTL</td>
552
</tr>
553
<tr>
554
   <td align="left">HPS_ENET_MDC</td>
555
   <td align="left"></td>
556
   <td align="left">output</td>
557
   <td align="left">3.3-V LVTTL</td>
558
</tr>
559
<tr>
560
   <td align="left">HPS_ENET_MDIO</td>
561
   <td align="left"></td>
562
   <td align="left">inout </td>
563
   <td align="left">3.3-V LVTTL</td>
564
</tr>
565
<tr>
566
   <td align="left">HPS_ENET_RX_CLK</td>
567
   <td align="left"></td>
568
   <td align="left">input </td>
569
   <td align="left">3.3-V LVTTL</td>
570
</tr>
571
<tr>
572
   <td align="left">HPS_ENET_RX_DATA[0]</td>
573
   <td align="left"></td>
574
   <td align="left">input </td>
575
   <td align="left">3.3-V LVTTL</td>
576
</tr>
577
<tr>
578
   <td align="left">HPS_ENET_RX_DATA[1]</td>
579
   <td align="left"></td>
580
   <td align="left">input </td>
581
   <td align="left">3.3-V LVTTL</td>
582
</tr>
583
<tr>
584
   <td align="left">HPS_ENET_RX_DATA[2]</td>
585
   <td align="left"></td>
586
   <td align="left">input </td>
587
   <td align="left">3.3-V LVTTL</td>
588
</tr>
589
<tr>
590
   <td align="left">HPS_ENET_RX_DATA[3]</td>
591
   <td align="left"></td>
592
   <td align="left">input </td>
593
   <td align="left">3.3-V LVTTL</td>
594
</tr>
595
<tr>
596
   <td align="left">HPS_ENET_RX_DV</td>
597
   <td align="left"></td>
598
   <td align="left">input </td>
599
   <td align="left">3.3-V LVTTL</td>
600
</tr>
601
<tr>
602
   <td align="left">HPS_ENET_TX_DATA[0]</td>
603
   <td align="left"></td>
604
   <td align="left">output</td>
605
   <td align="left">3.3-V LVTTL</td>
606
</tr>
607
<tr>
608
   <td align="left">HPS_ENET_TX_DATA[1]</td>
609
   <td align="left"></td>
610
   <td align="left">output</td>
611
   <td align="left">3.3-V LVTTL</td>
612
</tr>
613
<tr>
614
   <td align="left">HPS_ENET_TX_DATA[2]</td>
615
   <td align="left"></td>
616
   <td align="left">output</td>
617
   <td align="left">3.3-V LVTTL</td>
618
</tr>
619
<tr>
620
   <td align="left">HPS_ENET_TX_DATA[3]</td>
621
   <td align="left"></td>
622
   <td align="left">output</td>
623
   <td align="left">3.3-V LVTTL</td>
624
</tr>
625
<tr>
626
   <td align="left">HPS_ENET_TX_EN</td>
627
   <td align="left"></td>
628
   <td align="left">output</td>
629
   <td align="left">3.3-V LVTTL</td>
630
</tr>
631
<tr>
632
   <td align="left">HPS_GSENSOR_INT</td>
633
   <td align="left"></td>
634
   <td align="left">inout </td>
635
   <td align="left">3.3-V LVTTL</td>
636
</tr>
637
<tr>
638
   <td align="left">HPS_I2C0_SCLK</td>
639
   <td align="left"></td>
640
   <td align="left">inout </td>
641
   <td align="left">3.3-V LVTTL</td>
642
</tr>
643
<tr>
644
   <td align="left">HPS_I2C0_SDAT</td>
645
   <td align="left"></td>
646
   <td align="left">inout </td>
647
   <td align="left">3.3-V LVTTL</td>
648
</tr>
649
<tr>
650
   <td align="left">HPS_I2C1_SCLK</td>
651
   <td align="left"></td>
652
   <td align="left">inout </td>
653
   <td align="left">3.3-V LVTTL</td>
654
</tr>
655
<tr>
656
   <td align="left">HPS_I2C1_SDAT</td>
657
   <td align="left"></td>
658
   <td align="left">inout </td>
659
   <td align="left">3.3-V LVTTL</td>
660
</tr>
661
<tr>
662
   <td align="left">HPS_KEY</td>
663
   <td align="left"></td>
664
   <td align="left">inout </td>
665
   <td align="left">3.3-V LVTTL</td>
666
</tr>
667
<tr>
668
   <td align="left">HPS_LED</td>
669
   <td align="left"></td>
670
   <td align="left">inout </td>
671
   <td align="left">3.3-V LVTTL</td>
672
</tr>
673
<tr>
674
   <td align="left">HPS_LTC_GPIO</td>
675
   <td align="left"></td>
676
   <td align="left">inout </td>
677
   <td align="left">3.3-V LVTTL</td>
678
</tr>
679
<tr>
680
   <td align="left">HPS_SD_CLK</td>
681
   <td align="left"></td>
682
   <td align="left">output</td>
683
   <td align="left">3.3-V LVTTL</td>
684
</tr>
685
<tr>
686
   <td align="left">HPS_SD_CMD</td>
687
   <td align="left"></td>
688
   <td align="left">inout </td>
689
   <td align="left">3.3-V LVTTL</td>
690
</tr>
691
<tr>
692
   <td align="left">HPS_SD_DATA[0]</td>
693
   <td align="left"></td>
694
   <td align="left">inout </td>
695
   <td align="left">3.3-V LVTTL</td>
696
</tr>
697
<tr>
698
   <td align="left">HPS_SD_DATA[1]</td>
699
   <td align="left"></td>
700
   <td align="left">inout </td>
701
   <td align="left">3.3-V LVTTL</td>
702
</tr>
703
<tr>
704
   <td align="left">HPS_SD_DATA[2]</td>
705
   <td align="left"></td>
706
   <td align="left">inout </td>
707
   <td align="left">3.3-V LVTTL</td>
708
</tr>
709
<tr>
710
   <td align="left">HPS_SD_DATA[3]</td>
711
   <td align="left"></td>
712
   <td align="left">inout </td>
713
   <td align="left">3.3-V LVTTL</td>
714
</tr>
715
<tr>
716
   <td align="left">HPS_SPIM_CLK</td>
717
   <td align="left"></td>
718
   <td align="left">output</td>
719
   <td align="left">3.3-V LVTTL</td>
720
</tr>
721
<tr>
722
   <td align="left">HPS_SPIM_MISO</td>
723
   <td align="left"></td>
724
   <td align="left">input </td>
725
   <td align="left">3.3-V LVTTL</td>
726
</tr>
727
<tr>
728
   <td align="left">HPS_SPIM_MOSI</td>
729
   <td align="left"></td>
730
   <td align="left">output</td>
731
   <td align="left">3.3-V LVTTL</td>
732
</tr>
733
<tr>
734
   <td align="left">HPS_SPIM_SS</td>
735
   <td align="left"></td>
736
   <td align="left">inout </td>
737
   <td align="left">3.3-V LVTTL</td>
738
</tr>
739
<tr>
740
   <td align="left">HPS_UART_RX</td>
741
   <td align="left"></td>
742
   <td align="left">input </td>
743
   <td align="left">3.3-V LVTTL</td>
744
</tr>
745
<tr>
746
   <td align="left">HPS_UART_TX</td>
747
   <td align="left"></td>
748
   <td align="left">output</td>
749
   <td align="left">3.3-V LVTTL</td>
750
</tr>
751
<tr>
752
   <td align="left">HPS_USB_CLKOUT</td>
753
   <td align="left"></td>
754
   <td align="left">input </td>
755
   <td align="left">3.3-V LVTTL</td>
756
</tr>
757
<tr>
758
   <td align="left">HPS_USB_DATA[0]</td>
759
   <td align="left"></td>
760
   <td align="left">inout </td>
761
   <td align="left">3.3-V LVTTL</td>
762
</tr>
763
<tr>
764
   <td align="left">HPS_USB_DATA[1]</td>
765
   <td align="left"></td>
766
   <td align="left">inout </td>
767
   <td align="left">3.3-V LVTTL</td>
768
</tr>
769
<tr>
770
   <td align="left">HPS_USB_DATA[2]</td>
771
   <td align="left"></td>
772
   <td align="left">inout </td>
773
   <td align="left">3.3-V LVTTL</td>
774
</tr>
775
<tr>
776
   <td align="left">HPS_USB_DATA[3]</td>
777
   <td align="left"></td>
778
   <td align="left">inout </td>
779
   <td align="left">3.3-V LVTTL</td>
780
</tr>
781
<tr>
782
   <td align="left">HPS_USB_DATA[4]</td>
783
   <td align="left"></td>
784
   <td align="left">inout </td>
785
   <td align="left">3.3-V LVTTL</td>
786
</tr>
787
<tr>
788
   <td align="left">HPS_USB_DATA[5]</td>
789
   <td align="left"></td>
790
   <td align="left">inout </td>
791
   <td align="left">3.3-V LVTTL</td>
792
</tr>
793
<tr>
794
   <td align="left">HPS_USB_DATA[6]</td>
795
   <td align="left"></td>
796
   <td align="left">inout </td>
797
   <td align="left">3.3-V LVTTL</td>
798
</tr>
799
<tr>
800
   <td align="left">HPS_USB_DATA[7]</td>
801
   <td align="left"></td>
802
   <td align="left">inout </td>
803
   <td align="left">3.3-V LVTTL</td>
804
</tr>
805
<tr>
806
   <td align="left">HPS_USB_DIR</td>
807
   <td align="left"></td>
808
   <td align="left">input </td>
809
   <td align="left">3.3-V LVTTL</td>
810
</tr>
811
<tr>
812
   <td align="left">HPS_USB_NXT</td>
813
   <td align="left"></td>
814
   <td align="left">input </td>
815
   <td align="left">3.3-V LVTTL</td>
816
</tr>
817
<tr>
818
   <td align="left">HPS_USB_STP</td>
819
   <td align="left"></td>
820
   <td align="left">output</td>
821
   <td align="left">3.3-V LVTTL</td>
822
</tr>
823
</table>
824
<h2><a name="KEY"></a></h2><table border="3">
825
<caption  align="left">KEY</caption>
826
<br />
827
<br />
828
<tr>
829
   <th align="left" bgcolor="Khaki">Name</th>
830
   <th align="left" bgcolor="Khaki">Location</th>
831
   <th align="left" bgcolor="Khaki">Direction</th>
832
   <th align="left" bgcolor="Khaki">Standard</th>
833
</tr>
834
<tr>
835
   <td align="left">KEY[0]</td>
836
   <td align="left">AH17</td>
837
   <td align="left">input </td>
838
   <td align="left">3.3-V LVTTL</td>
839
</tr>
840
<tr>
841
   <td align="left">KEY[1]</td>
842
   <td align="left">AH16</td>
843
   <td align="left">input </td>
844
   <td align="left">3.3-V LVTTL</td>
845
</tr>
846
</table>
847
<h2><a name="LED"></a></h2><table border="3">
848
<caption  align="left">LED</caption>
849
<br />
850
<br />
851
<tr>
852
   <th align="left" bgcolor="Khaki">Name</th>
853
   <th align="left" bgcolor="Khaki">Location</th>
854
   <th align="left" bgcolor="Khaki">Direction</th>
855
   <th align="left" bgcolor="Khaki">Standard</th>
856
</tr>
857
<tr>
858
   <td align="left">LED[0]</td>
859
   <td align="left">W15</td>
860
   <td align="left">output</td>
861
   <td align="left">3.3-V LVTTL</td>
862
</tr>
863
<tr>
864
   <td align="left">LED[1]</td>
865
   <td align="left">AA24</td>
866
   <td align="left">output</td>
867
   <td align="left">3.3-V LVTTL</td>
868
</tr>
869
<tr>
870
   <td align="left">LED[2]</td>
871
   <td align="left">V16</td>
872
   <td align="left">output</td>
873
   <td align="left">3.3-V LVTTL</td>
874
</tr>
875
<tr>
876
   <td align="left">LED[3]</td>
877
   <td align="left">V15</td>
878
   <td align="left">output</td>
879
   <td align="left">3.3-V LVTTL</td>
880
</tr>
881
<tr>
882
   <td align="left">LED[4]</td>
883
   <td align="left">AF26</td>
884
   <td align="left">output</td>
885
   <td align="left">3.3-V LVTTL</td>
886
</tr>
887
<tr>
888
   <td align="left">LED[5]</td>
889
   <td align="left">AE26</td>
890
   <td align="left">output</td>
891
   <td align="left">3.3-V LVTTL</td>
892
</tr>
893
<tr>
894
   <td align="left">LED[6]</td>
895
   <td align="left">Y16</td>
896
   <td align="left">output</td>
897
   <td align="left">3.3-V LVTTL</td>
898
</tr>
899
<tr>
900
   <td align="left">LED[7]</td>
901
   <td align="left">AA23</td>
902
   <td align="left">output</td>
903
   <td align="left">3.3-V LVTTL</td>
904
</tr>
905
</table>
906
<h2><a name="SW"></a></h2><table border="3">
907
<caption  align="left">SW</caption>
908
<br />
909
<br />
910
<tr>
911
   <th align="left" bgcolor="Khaki">Name</th>
912
   <th align="left" bgcolor="Khaki">Location</th>
913
   <th align="left" bgcolor="Khaki">Direction</th>
914
   <th align="left" bgcolor="Khaki">Standard</th>
915
</tr>
916
<tr>
917
   <td align="left">SW[0]</td>
918
   <td align="left">L10</td>
919
   <td align="left">input </td>
920
   <td align="left">3.3-V LVTTL</td>
921
</tr>
922
<tr>
923
   <td align="left">SW[1]</td>
924
   <td align="left">L9</td>
925
   <td align="left">input </td>
926
   <td align="left">3.3-V LVTTL</td>
927
</tr>
928
<tr>
929
   <td align="left">SW[2]</td>
930
   <td align="left">H6</td>
931
   <td align="left">input </td>
932
   <td align="left">3.3-V LVTTL</td>
933
</tr>
934
<tr>
935
   <td align="left">SW[3]</td>
936
   <td align="left">H5</td>
937
   <td align="left">input </td>
938
   <td align="left">3.3-V LVTTL</td>
939
</tr>
940
</table>
941
<h2><a name="GPIO_0"></a></h2><table border="3">
942
<caption  align="left">GPIO connect to GPIO Default</caption>
943
<br />
944
<br />
945
<tr>
946
   <th align="left" bgcolor="Khaki">Name</th>
947
   <th align="left" bgcolor="Khaki">Location</th>
948
   <th align="left" bgcolor="Khaki">Direction</th>
949
   <th align="left" bgcolor="Khaki">Standard</th>
950
   <th align="left" bgcolor="Khaki">GPIO Pin Index</th>
951
</tr>
952
<tr>
953
   <td align="left">GPIO_0[0]</td>
954
   <td align="left">V12</td>
955
   <td align="left">inout </td>
956
   <td align="left">3.3-V LVTTL</td>
957
   <td align="left">1</td>
958
</tr>
959
<tr>
960
   <td align="left">GPIO_0[1]</td>
961
   <td align="left">AF7</td>
962
   <td align="left">inout </td>
963
   <td align="left">3.3-V LVTTL</td>
964
   <td align="left">2</td>
965
</tr>
966
<tr>
967
   <td align="left">GPIO_0[2]</td>
968
   <td align="left">W12</td>
969
   <td align="left">inout </td>
970
   <td align="left">3.3-V LVTTL</td>
971
   <td align="left">3</td>
972
</tr>
973
<tr>
974
   <td align="left">GPIO_0[3]</td>
975
   <td align="left">AF8</td>
976
   <td align="left">inout </td>
977
   <td align="left">3.3-V LVTTL</td>
978
   <td align="left">4</td>
979
</tr>
980
<tr>
981
   <td align="left">GPIO_0[4]</td>
982
   <td align="left">Y8</td>
983
   <td align="left">inout </td>
984
   <td align="left">3.3-V LVTTL</td>
985
   <td align="left">5</td>
986
</tr>
987
<tr>
988
   <td align="left">GPIO_0[5]</td>
989
   <td align="left">AB4</td>
990
   <td align="left">inout </td>
991
   <td align="left">3.3-V LVTTL</td>
992
   <td align="left">6</td>
993
</tr>
994
<tr>
995
   <td align="left">GPIO_0[6]</td>
996
   <td align="left">W8</td>
997
   <td align="left">inout </td>
998
   <td align="left">3.3-V LVTTL</td>
999
   <td align="left">7</td>
1000
</tr>
1001
<tr>
1002
   <td align="left">GPIO_0[7]</td>
1003
   <td align="left">Y4</td>
1004
   <td align="left">inout </td>
1005
   <td align="left">3.3-V LVTTL</td>
1006
   <td align="left">8</td>
1007
</tr>
1008
<tr>
1009
   <td align="left">GPIO_0[8]</td>
1010
   <td align="left">Y5</td>
1011
   <td align="left">inout </td>
1012
   <td align="left">3.3-V LVTTL</td>
1013
   <td align="left">9</td>
1014
</tr>
1015
<tr>
1016
   <td align="left">GPIO_0[9]</td>
1017
   <td align="left">U11</td>
1018
   <td align="left">inout </td>
1019
   <td align="left">3.3-V LVTTL</td>
1020
   <td align="left">10</td>
1021
</tr>
1022
<tr>
1023
   <td align="left">GPIO_0[10]</td>
1024
   <td align="left">T8</td>
1025
   <td align="left">inout </td>
1026
   <td align="left">3.3-V LVTTL</td>
1027
   <td align="left">13</td>
1028
</tr>
1029
<tr>
1030
   <td align="left">GPIO_0[11]</td>
1031
   <td align="left">T12</td>
1032
   <td align="left">inout </td>
1033
   <td align="left">3.3-V LVTTL</td>
1034
   <td align="left">14</td>
1035
</tr>
1036
<tr>
1037
   <td align="left">GPIO_0[12]</td>
1038
   <td align="left">AH5</td>
1039
   <td align="left">inout </td>
1040
   <td align="left">3.3-V LVTTL</td>
1041
   <td align="left">15</td>
1042
</tr>
1043
<tr>
1044
   <td align="left">GPIO_0[13]</td>
1045
   <td align="left">AH6</td>
1046
   <td align="left">inout </td>
1047
   <td align="left">3.3-V LVTTL</td>
1048
   <td align="left">16</td>
1049
</tr>
1050
<tr>
1051
   <td align="left">GPIO_0[14]</td>
1052
   <td align="left">AH4</td>
1053
   <td align="left">inout </td>
1054
   <td align="left">3.3-V LVTTL</td>
1055
   <td align="left">17</td>
1056
</tr>
1057
<tr>
1058
   <td align="left">GPIO_0[15]</td>
1059
   <td align="left">AG5</td>
1060
   <td align="left">inout </td>
1061
   <td align="left">3.3-V LVTTL</td>
1062
   <td align="left">18</td>
1063
</tr>
1064
<tr>
1065
   <td align="left">GPIO_0[16]</td>
1066
   <td align="left">AH3</td>
1067
   <td align="left">inout </td>
1068
   <td align="left">3.3-V LVTTL</td>
1069
   <td align="left">19</td>
1070
</tr>
1071
<tr>
1072
   <td align="left">GPIO_0[17]</td>
1073
   <td align="left">AH2</td>
1074
   <td align="left">inout </td>
1075
   <td align="left">3.3-V LVTTL</td>
1076
   <td align="left">20</td>
1077
</tr>
1078
<tr>
1079
   <td align="left">GPIO_0[18]</td>
1080
   <td align="left">AF4</td>
1081
   <td align="left">inout </td>
1082
   <td align="left">3.3-V LVTTL</td>
1083
   <td align="left">21</td>
1084
</tr>
1085
<tr>
1086
   <td align="left">GPIO_0[19]</td>
1087
   <td align="left">AG6</td>
1088
   <td align="left">inout </td>
1089
   <td align="left">3.3-V LVTTL</td>
1090
   <td align="left">22</td>
1091
</tr>
1092
<tr>
1093
   <td align="left">GPIO_0[20]</td>
1094
   <td align="left">AF5</td>
1095
   <td align="left">inout </td>
1096
   <td align="left">3.3-V LVTTL</td>
1097
   <td align="left">23</td>
1098
</tr>
1099
<tr>
1100
   <td align="left">GPIO_0[21]</td>
1101
   <td align="left">AE4</td>
1102
   <td align="left">inout </td>
1103
   <td align="left">3.3-V LVTTL</td>
1104
   <td align="left">24</td>
1105
</tr>
1106
<tr>
1107
   <td align="left">GPIO_0[22]</td>
1108
   <td align="left">T13</td>
1109
   <td align="left">inout </td>
1110
   <td align="left">3.3-V LVTTL</td>
1111
   <td align="left">25</td>
1112
</tr>
1113
<tr>
1114
   <td align="left">GPIO_0[23]</td>
1115
   <td align="left">T11</td>
1116
   <td align="left">inout </td>
1117
   <td align="left">3.3-V LVTTL</td>
1118
   <td align="left">26</td>
1119
</tr>
1120
<tr>
1121
   <td align="left">GPIO_0[24]</td>
1122
   <td align="left">AE7</td>
1123
   <td align="left">inout </td>
1124
   <td align="left">3.3-V LVTTL</td>
1125
   <td align="left">27</td>
1126
</tr>
1127
<tr>
1128
   <td align="left">GPIO_0[25]</td>
1129
   <td align="left">AF6</td>
1130
   <td align="left">inout </td>
1131
   <td align="left">3.3-V LVTTL</td>
1132
   <td align="left">28</td>
1133
</tr>
1134
<tr>
1135
   <td align="left">GPIO_0[26]</td>
1136
   <td align="left">AF9</td>
1137
   <td align="left">inout </td>
1138
   <td align="left">3.3-V LVTTL</td>
1139
   <td align="left">31</td>
1140
</tr>
1141
<tr>
1142
   <td align="left">GPIO_0[27]</td>
1143
   <td align="left">AE8</td>
1144
   <td align="left">inout </td>
1145
   <td align="left">3.3-V LVTTL</td>
1146
   <td align="left">32</td>
1147
</tr>
1148
<tr>
1149
   <td align="left">GPIO_0[28]</td>
1150
   <td align="left">AD10</td>
1151
   <td align="left">inout </td>
1152
   <td align="left">3.3-V LVTTL</td>
1153
   <td align="left">33</td>
1154
</tr>
1155
<tr>
1156
   <td align="left">GPIO_0[29]</td>
1157
   <td align="left">AE9</td>
1158
   <td align="left">inout </td>
1159
   <td align="left">3.3-V LVTTL</td>
1160
   <td align="left">34</td>
1161
</tr>
1162
<tr>
1163
   <td align="left">GPIO_0[30]</td>
1164
   <td align="left">AD11</td>
1165
   <td align="left">inout </td>
1166
   <td align="left">3.3-V LVTTL</td>
1167
   <td align="left">35</td>
1168
</tr>
1169
<tr>
1170
   <td align="left">GPIO_0[31]</td>
1171
   <td align="left">AF10</td>
1172
   <td align="left">inout </td>
1173
   <td align="left">3.3-V LVTTL</td>
1174
   <td align="left">36</td>
1175
</tr>
1176
<tr>
1177
   <td align="left">GPIO_0[32]</td>
1178
   <td align="left">AD12</td>
1179
   <td align="left">inout </td>
1180
   <td align="left">3.3-V LVTTL</td>
1181
   <td align="left">37</td>
1182
</tr>
1183
<tr>
1184
   <td align="left">GPIO_0[33]</td>
1185
   <td align="left">AE11</td>
1186
   <td align="left">inout </td>
1187
   <td align="left">3.3-V LVTTL</td>
1188
   <td align="left">38</td>
1189
</tr>
1190
<tr>
1191
   <td align="left">GPIO_0[34]</td>
1192
   <td align="left">AF11</td>
1193
   <td align="left">inout </td>
1194
   <td align="left">3.3-V LVTTL</td>
1195
   <td align="left">39</td>
1196
</tr>
1197
<tr>
1198
   <td align="left">GPIO_0[35]</td>
1199
   <td align="left">AE12</td>
1200
   <td align="left">inout </td>
1201
   <td align="left">3.3-V LVTTL</td>
1202
   <td align="left">40</td>
1203
</tr>
1204
</table>
1205
<h2><a name="GPIO_1"></a></h2><table border="3">
1206
<caption  align="left">GPIO connect to GPIO Default</caption>
1207
<br />
1208
<br />
1209
<tr>
1210
   <th align="left" bgcolor="Khaki">Name</th>
1211
   <th align="left" bgcolor="Khaki">Location</th>
1212
   <th align="left" bgcolor="Khaki">Direction</th>
1213
   <th align="left" bgcolor="Khaki">Standard</th>
1214
   <th align="left" bgcolor="Khaki">GPIO Pin Index</th>
1215
</tr>
1216
<tr>
1217
   <td align="left">GPIO_1[0]</td>
1218
   <td align="left">Y15</td>
1219
   <td align="left">inout </td>
1220
   <td align="left">3.3-V LVTTL</td>
1221
   <td align="left">1</td>
1222
</tr>
1223
<tr>
1224
   <td align="left">GPIO_1[1]</td>
1225
   <td align="left">AG28</td>
1226
   <td align="left">inout </td>
1227
   <td align="left">3.3-V LVTTL</td>
1228
   <td align="left">2</td>
1229
</tr>
1230
<tr>
1231
   <td align="left">GPIO_1[2]</td>
1232
   <td align="left">AA15</td>
1233
   <td align="left">inout </td>
1234
   <td align="left">3.3-V LVTTL</td>
1235
   <td align="left">3</td>
1236
</tr>
1237
<tr>
1238
   <td align="left">GPIO_1[3]</td>
1239
   <td align="left">AH27</td>
1240
   <td align="left">inout </td>
1241
   <td align="left">3.3-V LVTTL</td>
1242
   <td align="left">4</td>
1243
</tr>
1244
<tr>
1245
   <td align="left">GPIO_1[4]</td>
1246
   <td align="left">AG26</td>
1247
   <td align="left">inout </td>
1248
   <td align="left">3.3-V LVTTL</td>
1249
   <td align="left">5</td>
1250
</tr>
1251
<tr>
1252
   <td align="left">GPIO_1[5]</td>
1253
   <td align="left">AH24</td>
1254
   <td align="left">inout </td>
1255
   <td align="left">3.3-V LVTTL</td>
1256
   <td align="left">6</td>
1257
</tr>
1258
<tr>
1259
   <td align="left">GPIO_1[6]</td>
1260
   <td align="left">AF23</td>
1261
   <td align="left">inout </td>
1262
   <td align="left">3.3-V LVTTL</td>
1263
   <td align="left">7</td>
1264
</tr>
1265
<tr>
1266
   <td align="left">GPIO_1[7]</td>
1267
   <td align="left">AE22</td>
1268
   <td align="left">inout </td>
1269
   <td align="left">3.3-V LVTTL</td>
1270
   <td align="left">8</td>
1271
</tr>
1272
<tr>
1273
   <td align="left">GPIO_1[8]</td>
1274
   <td align="left">AF21</td>
1275
   <td align="left">inout </td>
1276
   <td align="left">3.3-V LVTTL</td>
1277
   <td align="left">9</td>
1278
</tr>
1279
<tr>
1280
   <td align="left">GPIO_1[9]</td>
1281
   <td align="left">AG20</td>
1282
   <td align="left">inout </td>
1283
   <td align="left">3.3-V LVTTL</td>
1284
   <td align="left">10</td>
1285
</tr>
1286
<tr>
1287
   <td align="left">GPIO_1[10]</td>
1288
   <td align="left">AG19</td>
1289
   <td align="left">inout </td>
1290
   <td align="left">3.3-V LVTTL</td>
1291
   <td align="left">13</td>
1292
</tr>
1293
<tr>
1294
   <td align="left">GPIO_1[11]</td>
1295
   <td align="left">AF20</td>
1296
   <td align="left">inout </td>
1297
   <td align="left">3.3-V LVTTL</td>
1298
   <td align="left">14</td>
1299
</tr>
1300
<tr>
1301
   <td align="left">GPIO_1[12]</td>
1302
   <td align="left">AC23</td>
1303
   <td align="left">inout </td>
1304
   <td align="left">3.3-V LVTTL</td>
1305
   <td align="left">15</td>
1306
</tr>
1307
<tr>
1308
   <td align="left">GPIO_1[13]</td>
1309
   <td align="left">AG18</td>
1310
   <td align="left">inout </td>
1311
   <td align="left">3.3-V LVTTL</td>
1312
   <td align="left">16</td>
1313
</tr>
1314
<tr>
1315
   <td align="left">GPIO_1[14]</td>
1316
   <td align="left">AH26</td>
1317
   <td align="left">inout </td>
1318
   <td align="left">3.3-V LVTTL</td>
1319
   <td align="left">17</td>
1320
</tr>
1321
<tr>
1322
   <td align="left">GPIO_1[15]</td>
1323
   <td align="left">AA19</td>
1324
   <td align="left">inout </td>
1325
   <td align="left">3.3-V LVTTL</td>
1326
   <td align="left">18</td>
1327
</tr>
1328
<tr>
1329
   <td align="left">GPIO_1[16]</td>
1330
   <td align="left">AG24</td>
1331
   <td align="left">inout </td>
1332
   <td align="left">3.3-V LVTTL</td>
1333
   <td align="left">19</td>
1334
</tr>
1335
<tr>
1336
   <td align="left">GPIO_1[17]</td>
1337
   <td align="left">AF25</td>
1338
   <td align="left">inout </td>
1339
   <td align="left">3.3-V LVTTL</td>
1340
   <td align="left">20</td>
1341
</tr>
1342
<tr>
1343
   <td align="left">GPIO_1[18]</td>
1344
   <td align="left">AH23</td>
1345
   <td align="left">inout </td>
1346
   <td align="left">3.3-V LVTTL</td>
1347
   <td align="left">21</td>
1348
</tr>
1349
<tr>
1350
   <td align="left">GPIO_1[19]</td>
1351
   <td align="left">AG23</td>
1352
   <td align="left">inout </td>
1353
   <td align="left">3.3-V LVTTL</td>
1354
   <td align="left">22</td>
1355
</tr>
1356
<tr>
1357
   <td align="left">GPIO_1[20]</td>
1358
   <td align="left">AE19</td>
1359
   <td align="left">inout </td>
1360
   <td align="left">3.3-V LVTTL</td>
1361
   <td align="left">23</td>
1362
</tr>
1363
<tr>
1364
   <td align="left">GPIO_1[21]</td>
1365
   <td align="left">AF18</td>
1366
   <td align="left">inout </td>
1367
   <td align="left">3.3-V LVTTL</td>
1368
   <td align="left">24</td>
1369
</tr>
1370
<tr>
1371
   <td align="left">GPIO_1[22]</td>
1372
   <td align="left">AD19</td>
1373
   <td align="left">inout </td>
1374
   <td align="left">3.3-V LVTTL</td>
1375
   <td align="left">25</td>
1376
</tr>
1377
<tr>
1378
   <td align="left">GPIO_1[23]</td>
1379
   <td align="left">AE20</td>
1380
   <td align="left">inout </td>
1381
   <td align="left">3.3-V LVTTL</td>
1382
   <td align="left">26</td>
1383
</tr>
1384
<tr>
1385
   <td align="left">GPIO_1[24]</td>
1386
   <td align="left">AE24</td>
1387
   <td align="left">inout </td>
1388
   <td align="left">3.3-V LVTTL</td>
1389
   <td align="left">27</td>
1390
</tr>
1391
<tr>
1392
   <td align="left">GPIO_1[25]</td>
1393
   <td align="left">AD20</td>
1394
   <td align="left">inout </td>
1395
   <td align="left">3.3-V LVTTL</td>
1396
   <td align="left">28</td>
1397
</tr>
1398
<tr>
1399
   <td align="left">GPIO_1[26]</td>
1400
   <td align="left">AF22</td>
1401
   <td align="left">inout </td>
1402
   <td align="left">3.3-V LVTTL</td>
1403
   <td align="left">31</td>
1404
</tr>
1405
<tr>
1406
   <td align="left">GPIO_1[27]</td>
1407
   <td align="left">AH22</td>
1408
   <td align="left">inout </td>
1409
   <td align="left">3.3-V LVTTL</td>
1410
   <td align="left">32</td>
1411
</tr>
1412
<tr>
1413
   <td align="left">GPIO_1[28]</td>
1414
   <td align="left">AH19</td>
1415
   <td align="left">inout </td>
1416
   <td align="left">3.3-V LVTTL</td>
1417
   <td align="left">33</td>
1418
</tr>
1419
<tr>
1420
   <td align="left">GPIO_1[29]</td>
1421
   <td align="left">AH21</td>
1422
   <td align="left">inout </td>
1423
   <td align="left">3.3-V LVTTL</td>
1424
   <td align="left">34</td>
1425
</tr>
1426
<tr>
1427
   <td align="left">GPIO_1[30]</td>
1428
   <td align="left">AG21</td>
1429
   <td align="left">inout </td>
1430
   <td align="left">3.3-V LVTTL</td>
1431
   <td align="left">35</td>
1432
</tr>
1433
<tr>
1434
   <td align="left">GPIO_1[31]</td>
1435
   <td align="left">AH18</td>
1436
   <td align="left">inout </td>
1437
   <td align="left">3.3-V LVTTL</td>
1438
   <td align="left">36</td>
1439
</tr>
1440
<tr>
1441
   <td align="left">GPIO_1[32]</td>
1442
   <td align="left">AD23</td>
1443
   <td align="left">inout </td>
1444
   <td align="left">3.3-V LVTTL</td>
1445
   <td align="left">37</td>
1446
</tr>
1447
<tr>
1448
   <td align="left">GPIO_1[33]</td>
1449
   <td align="left">AE23</td>
1450
   <td align="left">inout </td>
1451
   <td align="left">3.3-V LVTTL</td>
1452
   <td align="left">38</td>
1453
</tr>
1454
<tr>
1455
   <td align="left">GPIO_1[34]</td>
1456
   <td align="left">AA18</td>
1457
   <td align="left">inout </td>
1458
   <td align="left">3.3-V LVTTL</td>
1459
   <td align="left">39</td>
1460
</tr>
1461
<tr>
1462
   <td align="left">GPIO_1[35]</td>
1463
   <td align="left">AC22</td>
1464
   <td align="left">inout </td>
1465
   <td align="left">3.3-V LVTTL</td>
1466
   <td align="left">40</td>
1467
</tr>
1468
</table>
1469
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1470
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