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// (C) 2001-2014 Altera Corporation. All rights reserved.

// Your use of Altera Corporation's design tools, logic functions and other

// software and tools, and its AMPP partner logic functions, and any output

// files any of the foregoing (including device programming or simulation

// files), and any associated documentation or information are expressly subject

// to the terms and conditions of the Altera Program License Subscription

// Agreement, Altera MegaCore Function License Agreement, or other applicable

// license agreement, including, without limitation, that your use is for the

// sole purpose of programming logic devices manufactured by Altera and sold by

// Altera or its authorized distributors.  Please refer to the applicable

// agreement for further details.

// $Id: //acds/rel/14.0/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $

// $Revision: #1 $

// $Date: 2014/02/16 $

// $Author: swbranch $

// -------------------------------------------------------

// Altera IRQ Mapper

//

// Parameters

//   NUM_RCVRS        : 2

//   SENDER_IRW_WIDTH : 32

//   IRQ_MAP          : 0:0,1:1

//

// -------------------------------------------------------

`timescale 1 ns / 1 ns

module DE0_NANO_SOC_QSYS_irq_mapper

(

    // -------------------

    // Clock & Reset

    // -------------------

    input clk,

    input reset,

    // -------------------

    // IRQ Receivers

    // -------------------

    input                receiver0_irq,

    input                receiver1_irq,

    // -------------------

    // Command Source (Output)

    // -------------------

    output reg [31 : 0] sender_irq

);

    always @* begin

        sender_irq = 0;

        sender_irq[0] = receiver0_irq;

        sender_irq[1] = receiver1_irq;

    end

endmodule