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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_QSYS/] [synthesis/] [submodules/] [DE0_NANO_SOC_QSYS_jtag_uart.v] - Blame information for rev 221

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//Legal Notice: (C)2014 Altera Corporation. All rights reserved.  Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w (
                                                  // inputs:
                                                   clk,
                                                   fifo_wdata,
                                                   fifo_wr,
 
                                                  // outputs:
                                                   fifo_FF,
                                                   r_dat,
                                                   wfifo_empty,
                                                   wfifo_used
                                                )
;
 
  output           fifo_FF;
  output  [  7: 0] r_dat;
  output           wfifo_empty;
  output  [  5: 0] wfifo_used;
  input            clk;
  input   [  7: 0] fifo_wdata;
  input            fifo_wr;
 
  wire             fifo_FF;
  wire    [  7: 0] r_dat;
  wire             wfifo_empty;
  wire    [  5: 0] wfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  always @(posedge clk)
    begin
      if (fifo_wr)
          $write("%c", fifo_wdata);
    end
 
 
  assign wfifo_used = {6{1'b0}};
  assign r_dat = {8{1'b0}};
  assign fifo_FF = 1'b0;
  assign wfifo_empty = 1'b1;
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w (
                                              // inputs:
                                               clk,
                                               fifo_clear,
                                               fifo_wdata,
                                               fifo_wr,
                                               rd_wfifo,
 
                                              // outputs:
                                               fifo_FF,
                                               r_dat,
                                               wfifo_empty,
                                               wfifo_used
                                            )
;
 
  output           fifo_FF;
  output  [  7: 0] r_dat;
  output           wfifo_empty;
  output  [  5: 0] wfifo_used;
  input            clk;
  input            fifo_clear;
  input   [  7: 0] fifo_wdata;
  input            fifo_wr;
  input            rd_wfifo;
 
  wire             fifo_FF;
  wire    [  7: 0] r_dat;
  wire             wfifo_empty;
  wire    [  5: 0] wfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w the_DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w
    (
      .clk         (clk),
      .fifo_FF     (fifo_FF),
      .fifo_wdata  (fifo_wdata),
      .fifo_wr     (fifo_wr),
      .r_dat       (r_dat),
      .wfifo_empty (wfifo_empty),
      .wfifo_used  (wfifo_used)
    );
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
//synthesis read_comments_as_HDL on
//  scfifo wfifo
//    (
//      .aclr (fifo_clear),
//      .clock (clk),
//      .data (fifo_wdata),
//      .empty (wfifo_empty),
//      .full (fifo_FF),
//      .q (r_dat),
//      .rdreq (rd_wfifo),
//      .usedw (wfifo_used),
//      .wrreq (fifo_wr)
//    );
//
//  defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
//           wfifo.lpm_numwords = 64,
//           wfifo.lpm_showahead = "OFF",
//           wfifo.lpm_type = "scfifo",
//           wfifo.lpm_width = 8,
//           wfifo.lpm_widthu = 6,
//           wfifo.overflow_checking = "OFF",
//           wfifo.underflow_checking = "OFF",
//           wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r (
                                                  // inputs:
                                                   clk,
                                                   fifo_rd,
                                                   rst_n,
 
                                                  // outputs:
                                                   fifo_EF,
                                                   fifo_rdata,
                                                   rfifo_full,
                                                   rfifo_used
                                                )
;
 
  output           fifo_EF;
  output  [  7: 0] fifo_rdata;
  output           rfifo_full;
  output  [  5: 0] rfifo_used;
  input            clk;
  input            fifo_rd;
  input            rst_n;
 
  reg     [ 31: 0] bytes_left;
  wire             fifo_EF;
  reg              fifo_rd_d;
  wire    [  7: 0] fifo_rdata;
  wire             new_rom;
  wire    [ 31: 0] num_bytes;
  wire    [  6: 0] rfifo_entries;
  wire             rfifo_full;
  wire    [  5: 0] rfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  // Generate rfifo_entries for simulation
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
        begin
          bytes_left <= 32'h0;
          fifo_rd_d <= 1'b0;
        end
      else
        begin
          fifo_rd_d <= fifo_rd;
          // decrement on read
          if (fifo_rd_d)
              bytes_left <= bytes_left - 1'b1;
          // catch new contents
          if (new_rom)
              bytes_left <= num_bytes;
        end
    end
 
 
  assign fifo_EF = bytes_left == 32'b0;
  assign rfifo_full = bytes_left > 7'h40;
  assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
  assign rfifo_used = rfifo_entries[5 : 0];
  assign new_rom = 1'b0;
  assign num_bytes = 32'b0;
  assign fifo_rdata = 8'b0;
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r (
                                              // inputs:
                                               clk,
                                               fifo_clear,
                                               fifo_rd,
                                               rst_n,
                                               t_dat,
                                               wr_rfifo,
 
                                              // outputs:
                                               fifo_EF,
                                               fifo_rdata,
                                               rfifo_full,
                                               rfifo_used
                                            )
;
 
  output           fifo_EF;
  output  [  7: 0] fifo_rdata;
  output           rfifo_full;
  output  [  5: 0] rfifo_used;
  input            clk;
  input            fifo_clear;
  input            fifo_rd;
  input            rst_n;
  input   [  7: 0] t_dat;
  input            wr_rfifo;
 
  wire             fifo_EF;
  wire    [  7: 0] fifo_rdata;
  wire             rfifo_full;
  wire    [  5: 0] rfifo_used;
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r the_DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r
    (
      .clk        (clk),
      .fifo_EF    (fifo_EF),
      .fifo_rd    (fifo_rd),
      .fifo_rdata (fifo_rdata),
      .rfifo_full (rfifo_full),
      .rfifo_used (rfifo_used),
      .rst_n      (rst_n)
    );
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
//synthesis read_comments_as_HDL on
//  scfifo rfifo
//    (
//      .aclr (fifo_clear),
//      .clock (clk),
//      .data (t_dat),
//      .empty (fifo_EF),
//      .full (rfifo_full),
//      .q (fifo_rdata),
//      .rdreq (fifo_rd),
//      .usedw (rfifo_used),
//      .wrreq (wr_rfifo)
//    );
//
//  defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
//           rfifo.lpm_numwords = 64,
//           rfifo.lpm_showahead = "OFF",
//           rfifo.lpm_type = "scfifo",
//           rfifo.lpm_width = 8,
//           rfifo.lpm_widthu = 6,
//           rfifo.overflow_checking = "OFF",
//           rfifo.underflow_checking = "OFF",
//           rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
 
endmodule
 
 
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
 
// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 
 
module DE0_NANO_SOC_QSYS_jtag_uart (
                                     // inputs:
                                      av_address,
                                      av_chipselect,
                                      av_read_n,
                                      av_write_n,
                                      av_writedata,
                                      clk,
                                      rst_n,
 
                                     // outputs:
                                      av_irq,
                                      av_readdata,
                                      av_waitrequest,
                                      dataavailable,
                                      readyfordata
                                   )
  /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
 
  output           av_irq;
  output  [ 31: 0] av_readdata;
  output           av_waitrequest;
  output           dataavailable;
  output           readyfordata;
  input            av_address;
  input            av_chipselect;
  input            av_read_n;
  input            av_write_n;
  input   [ 31: 0] av_writedata;
  input            clk;
  input            rst_n;
 
  reg              ac;
  wire             activity;
  wire             av_irq;
  wire    [ 31: 0] av_readdata;
  reg              av_waitrequest;
  reg              dataavailable;
  reg              fifo_AE;
  reg              fifo_AF;
  wire             fifo_EF;
  wire             fifo_FF;
  wire             fifo_clear;
  wire             fifo_rd;
  wire    [  7: 0] fifo_rdata;
  wire    [  7: 0] fifo_wdata;
  reg              fifo_wr;
  reg              ien_AE;
  reg              ien_AF;
  wire             ipen_AE;
  wire             ipen_AF;
  reg              pause_irq;
  wire    [  7: 0] r_dat;
  wire             r_ena;
  reg              r_val;
  wire             rd_wfifo;
  reg              read_0;
  reg              readyfordata;
  wire             rfifo_full;
  wire    [  5: 0] rfifo_used;
  reg              rvalid;
  reg              sim_r_ena;
  reg              sim_t_dat;
  reg              sim_t_ena;
  reg              sim_t_pause;
  wire    [  7: 0] t_dat;
  reg              t_dav;
  wire             t_ena;
  wire             t_pause;
  wire             wfifo_empty;
  wire    [  5: 0] wfifo_used;
  reg              woverflow;
  wire             wr_rfifo;
  //avalon_jtag_slave, which is an e_avalon_slave
  assign rd_wfifo = r_ena & ~wfifo_empty;
  assign wr_rfifo = t_ena & ~rfifo_full;
  assign fifo_clear = ~rst_n;
  DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w the_DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w
    (
      .clk         (clk),
      .fifo_FF     (fifo_FF),
      .fifo_clear  (fifo_clear),
      .fifo_wdata  (fifo_wdata),
      .fifo_wr     (fifo_wr),
      .r_dat       (r_dat),
      .rd_wfifo    (rd_wfifo),
      .wfifo_empty (wfifo_empty),
      .wfifo_used  (wfifo_used)
    );
 
  DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r the_DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r
    (
      .clk        (clk),
      .fifo_EF    (fifo_EF),
      .fifo_clear (fifo_clear),
      .fifo_rd    (fifo_rd),
      .fifo_rdata (fifo_rdata),
      .rfifo_full (rfifo_full),
      .rfifo_used (rfifo_used),
      .rst_n      (rst_n),
      .t_dat      (t_dat),
      .wr_rfifo   (wr_rfifo)
    );
 
  assign ipen_AE = ien_AE & fifo_AE;
  assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
  assign av_irq = ipen_AE | ipen_AF;
  assign activity = t_pause | t_ena;
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
          pause_irq <= 1'b0;
      else // only if fifo is not empty...
      if (t_pause & ~fifo_EF)
          pause_irq <= 1'b1;
      else if (read_0)
          pause_irq <= 1'b0;
    end
 
 
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
        begin
          r_val <= 1'b0;
          t_dav <= 1'b1;
        end
      else
        begin
          r_val <= r_ena & ~wfifo_empty;
          t_dav <= ~rfifo_full;
        end
    end
 
 
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
        begin
          fifo_AE <= 1'b0;
          fifo_AF <= 1'b0;
          fifo_wr <= 1'b0;
          rvalid <= 1'b0;
          read_0 <= 1'b0;
          ien_AE <= 1'b0;
          ien_AF <= 1'b0;
          ac <= 1'b0;
          woverflow <= 1'b0;
          av_waitrequest <= 1'b1;
        end
      else
        begin
          fifo_AE <= {fifo_FF,wfifo_used} <= 8;
          fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
          fifo_wr <= 1'b0;
          read_0 <= 1'b0;
          av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
          if (activity)
              ac <= 1'b1;
          // write
          if (av_chipselect & ~av_write_n & av_waitrequest)
              // addr 1 is control; addr 0 is data
              if (av_address)
                begin
                  ien_AF <= av_writedata[0];
                  ien_AE <= av_writedata[1];
                  if (av_writedata[10] & ~activity)
                      ac <= 1'b0;
                end
              else
                begin
                  fifo_wr <= ~fifo_FF;
                  woverflow <= fifo_FF;
                end
          // read
          if (av_chipselect & ~av_read_n & av_waitrequest)
            begin
              // addr 1 is interrupt; addr 0 is data
              if (~av_address)
                  rvalid <= ~fifo_EF;
              read_0 <= ~av_address;
            end
        end
    end
 
 
  assign fifo_wdata = av_writedata[7 : 0];
  assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
  assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
  always @(posedge clk or negedge rst_n)
    begin
      if (rst_n == 0)
          readyfordata <= 0;
      else
        readyfordata <= ~fifo_FF;
    end
 
 
 
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  // Tie off Atlantic Interface signals not used for simulation
  always @(posedge clk)
    begin
      sim_t_pause <= 1'b0;
      sim_t_ena <= 1'b0;
      sim_t_dat <= t_dav ? r_dat : {8{r_val}};
      sim_r_ena <= 1'b0;
    end
 
 
  assign r_ena = sim_r_ena;
  assign t_ena = sim_t_ena;
  assign t_dat = sim_t_dat;
  assign t_pause = sim_t_pause;
  always @(fifo_EF)
    begin
      dataavailable = ~fifo_EF;
    end
 
 
 
//////////////// END SIMULATION-ONLY CONTENTS
 
//synthesis translate_on
//synthesis read_comments_as_HDL on
//  alt_jtag_atlantic DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic
//    (
//      .clk (clk),
//      .r_dat (r_dat),
//      .r_ena (r_ena),
//      .r_val (r_val),
//      .rst_n (rst_n),
//      .t_dat (t_dat),
//      .t_dav (t_dav),
//      .t_ena (t_ena),
//      .t_pause (t_pause)
//    );
//
//  defparam DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
//           DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
//           DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
//           DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
//  always @(posedge clk or negedge rst_n)
//    begin
//      if (rst_n == 0)
//          dataavailable <= 0;
//      else 
//        dataavailable <= ~fifo_EF;
//    end
//
//
//synthesis read_comments_as_HDL off
 
endmodule
 

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_QSYS/] [synthesis/] [submodules/] [DE0_NANO_SOC_QSYS_jtag_uart.v] - Blame information for rev 221

Line No.	Rev	Author	Line
1	221	olivier.gi	`//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`// synthesis translate_off`
14			`timescale 1ns / 1ps
15			`// synthesis translate_on`
16
17			`// turn off superfluous verilog processor warnings`
18			`// altera message_level Level1`
19			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
20
21			`module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w (`
22			`// inputs:`
23			`clk,`
24			`fifo_wdata,`
25			`fifo_wr,`
26
27			`// outputs:`
28			`fifo_FF,`
29			`r_dat,`
30			`wfifo_empty,`
31			`wfifo_used`
32			`)`
33			`;`
34
35			`output fifo_FF;`
36			`output [ 7: 0] r_dat;`
37			`output wfifo_empty;`
38			`output [ 5: 0] wfifo_used;`
39			`input clk;`
40			`input [ 7: 0] fifo_wdata;`
41			`input fifo_wr;`
42
43			`wire fifo_FF;`
44			`wire [ 7: 0] r_dat;`
45			`wire wfifo_empty;`
46			`wire [ 5: 0] wfifo_used;`
47
48			`//synthesis translate_off`
49			`//////////////// SIMULATION-ONLY CONTENTS`
50			`always @(posedge clk)`
51			`begin`
52			`if (fifo_wr)`
53			`$write("%c", fifo_wdata);`
54			`end`
55
56
57			`assign wfifo_used = {6{1'b0}};`
58			`assign r_dat = {8{1'b0}};`
59			`assign fifo_FF = 1'b0;`
60			`assign wfifo_empty = 1'b1;`
61
62			`//////////////// END SIMULATION-ONLY CONTENTS`
63
64			`//synthesis translate_on`
65
66			`endmodule`
67
68
69			`// synthesis translate_off`
70			`timescale 1ns / 1ps
71			`// synthesis translate_on`
72
73			`// turn off superfluous verilog processor warnings`
74			`// altera message_level Level1`
75			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
76
77			`module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w (`
78			`// inputs:`
79			`clk,`
80			`fifo_clear,`
81			`fifo_wdata,`
82			`fifo_wr,`
83			`rd_wfifo,`
84
85			`// outputs:`
86			`fifo_FF,`
87			`r_dat,`
88			`wfifo_empty,`
89			`wfifo_used`
90			`)`
91			`;`
92
93			`output fifo_FF;`
94			`output [ 7: 0] r_dat;`
95			`output wfifo_empty;`
96			`output [ 5: 0] wfifo_used;`
97			`input clk;`
98			`input fifo_clear;`
99			`input [ 7: 0] fifo_wdata;`
100			`input fifo_wr;`
101			`input rd_wfifo;`
102
103			`wire fifo_FF;`
104			`wire [ 7: 0] r_dat;`
105			`wire wfifo_empty;`
106			`wire [ 5: 0] wfifo_used;`
107
108			`//synthesis translate_off`
109			`//////////////// SIMULATION-ONLY CONTENTS`
110			`DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w the_DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_w`
111			`(`
112			`.clk (clk),`
113			`.fifo_FF (fifo_FF),`
114			`.fifo_wdata (fifo_wdata),`
115			`.fifo_wr (fifo_wr),`
116			`.r_dat (r_dat),`
117			`.wfifo_empty (wfifo_empty),`
118			`.wfifo_used (wfifo_used)`
119			`);`
120
121
122			`//////////////// END SIMULATION-ONLY CONTENTS`
123
124			`//synthesis translate_on`
125			`//synthesis read_comments_as_HDL on`
126			`// scfifo wfifo`
127			`// (`
128			`// .aclr (fifo_clear),`
129			`// .clock (clk),`
130			`// .data (fifo_wdata),`
131			`// .empty (wfifo_empty),`
132			`// .full (fifo_FF),`
133			`// .q (r_dat),`
134			`// .rdreq (rd_wfifo),`
135			`// .usedw (wfifo_used),`
136			`// .wrreq (fifo_wr)`
137			`// );`
138			`//`
139			`// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",`
140			`// wfifo.lpm_numwords = 64,`
141			`// wfifo.lpm_showahead = "OFF",`
142			`// wfifo.lpm_type = "scfifo",`
143			`// wfifo.lpm_width = 8,`
144			`// wfifo.lpm_widthu = 6,`
145			`// wfifo.overflow_checking = "OFF",`
146			`// wfifo.underflow_checking = "OFF",`
147			`// wfifo.use_eab = "ON";`
148			`//`
149			`//synthesis read_comments_as_HDL off`
150
151			`endmodule`
152
153
154			`// synthesis translate_off`
155			`timescale 1ns / 1ps
156			`// synthesis translate_on`
157
158			`// turn off superfluous verilog processor warnings`
159			`// altera message_level Level1`
160			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
161
162			`module DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r (`
163			`// inputs:`
164			`clk,`
165			`fifo_rd,`
166			`rst_n,`
167
168			`// outputs:`
169			`fifo_EF,`
170			`fifo_rdata,`
171			`rfifo_full,`
172			`rfifo_used`
173			`)`
174			`;`
175
176			`output fifo_EF;`
177			`output [ 7: 0] fifo_rdata;`
178			`output rfifo_full;`
179			`output [ 5: 0] rfifo_used;`
180			`input clk;`
181			`input fifo_rd;`
182			`input rst_n;`
183
184			`reg [ 31: 0] bytes_left;`
185			`wire fifo_EF;`
186			`reg fifo_rd_d;`
187			`wire [ 7: 0] fifo_rdata;`
188			`wire new_rom;`
189			`wire [ 31: 0] num_bytes;`
190			`wire [ 6: 0] rfifo_entries;`
191			`wire rfifo_full;`
192			`wire [ 5: 0] rfifo_used;`
193
194			`//synthesis translate_off`
195			`//////////////// SIMULATION-ONLY CONTENTS`
196			`// Generate rfifo_entries for simulation`
197			`always @(posedge clk or negedge rst_n)`
198			`begin`
199			`if (rst_n == 0)`
200			`begin`
201			`bytes_left <= 32'h0;`
202			`fifo_rd_d <= 1'b0;`
203			`end`
204			`else`
205			`begin`
206			`fifo_rd_d <= fifo_rd;`
207			`// decrement on read`
208			`if (fifo_rd_d)`
209			`bytes_left <= bytes_left - 1'b1;`
210			`// catch new contents`
211			`if (new_rom)`
212			`bytes_left <= num_bytes;`
213			`end`
214			`end`
215
216
217			`assign fifo_EF = bytes_left == 32'b0;`
218			`assign rfifo_full = bytes_left > 7'h40;`
219			`assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;`
220			`assign rfifo_used = rfifo_entries[5 : 0];`
221			`assign new_rom = 1'b0;`
222			`assign num_bytes = 32'b0;`
223			`assign fifo_rdata = 8'b0;`
224
225			`//////////////// END SIMULATION-ONLY CONTENTS`
226
227			`//synthesis translate_on`
228
229			`endmodule`
230
231
232			`// synthesis translate_off`
233			`timescale 1ns / 1ps
234			`// synthesis translate_on`
235
236			`// turn off superfluous verilog processor warnings`
237			`// altera message_level Level1`
238			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
239
240			`module DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r (`
241			`// inputs:`
242			`clk,`
243			`fifo_clear,`
244			`fifo_rd,`
245			`rst_n,`
246			`t_dat,`
247			`wr_rfifo,`
248
249			`// outputs:`
250			`fifo_EF,`
251			`fifo_rdata,`
252			`rfifo_full,`
253			`rfifo_used`
254			`)`
255			`;`
256
257			`output fifo_EF;`
258			`output [ 7: 0] fifo_rdata;`
259			`output rfifo_full;`
260			`output [ 5: 0] rfifo_used;`
261			`input clk;`
262			`input fifo_clear;`
263			`input fifo_rd;`
264			`input rst_n;`
265			`input [ 7: 0] t_dat;`
266			`input wr_rfifo;`
267
268			`wire fifo_EF;`
269			`wire [ 7: 0] fifo_rdata;`
270			`wire rfifo_full;`
271			`wire [ 5: 0] rfifo_used;`
272
273			`//synthesis translate_off`
274			`//////////////// SIMULATION-ONLY CONTENTS`
275			`DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r the_DE0_NANO_SOC_QSYS_jtag_uart_sim_scfifo_r`
276			`(`
277			`.clk (clk),`
278			`.fifo_EF (fifo_EF),`
279			`.fifo_rd (fifo_rd),`
280			`.fifo_rdata (fifo_rdata),`
281			`.rfifo_full (rfifo_full),`
282			`.rfifo_used (rfifo_used),`
283			`.rst_n (rst_n)`
284			`);`
285
286
287			`//////////////// END SIMULATION-ONLY CONTENTS`
288
289			`//synthesis translate_on`
290			`//synthesis read_comments_as_HDL on`
291			`// scfifo rfifo`
292			`// (`
293			`// .aclr (fifo_clear),`
294			`// .clock (clk),`
295			`// .data (t_dat),`
296			`// .empty (fifo_EF),`
297			`// .full (rfifo_full),`
298			`// .q (fifo_rdata),`
299			`// .rdreq (fifo_rd),`
300			`// .usedw (rfifo_used),`
301			`// .wrreq (wr_rfifo)`
302			`// );`
303			`//`
304			`// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",`
305			`// rfifo.lpm_numwords = 64,`
306			`// rfifo.lpm_showahead = "OFF",`
307			`// rfifo.lpm_type = "scfifo",`
308			`// rfifo.lpm_width = 8,`
309			`// rfifo.lpm_widthu = 6,`
310			`// rfifo.overflow_checking = "OFF",`
311			`// rfifo.underflow_checking = "OFF",`
312			`// rfifo.use_eab = "ON";`
313			`//`
314			`//synthesis read_comments_as_HDL off`
315
316			`endmodule`
317
318
319			`// synthesis translate_off`
320			`timescale 1ns / 1ps
321			`// synthesis translate_on`
322
323			`// turn off superfluous verilog processor warnings`
324			`// altera message_level Level1`
325			`// altera message_off 10034 10035 10036 10037 10230 10240 10030`
326
327			`module DE0_NANO_SOC_QSYS_jtag_uart (`
328			`// inputs:`
329			`av_address,`
330			`av_chipselect,`
331			`av_read_n,`
332			`av_write_n,`
333			`av_writedata,`
334			`clk,`
335			`rst_n,`
336
337			`// outputs:`
338			`av_irq,`
339			`av_readdata,`
340			`av_waitrequest,`
341			`dataavailable,`
342			`readyfordata`
343			`)`
344			`/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;`
345
346			`output av_irq;`
347			`output [ 31: 0] av_readdata;`
348			`output av_waitrequest;`
349			`output dataavailable;`
350			`output readyfordata;`
351			`input av_address;`
352			`input av_chipselect;`
353			`input av_read_n;`
354			`input av_write_n;`
355			`input [ 31: 0] av_writedata;`
356			`input clk;`
357			`input rst_n;`
358
359			`reg ac;`
360			`wire activity;`
361			`wire av_irq;`
362			`wire [ 31: 0] av_readdata;`
363			`reg av_waitrequest;`
364			`reg dataavailable;`
365			`reg fifo_AE;`
366			`reg fifo_AF;`
367			`wire fifo_EF;`
368			`wire fifo_FF;`
369			`wire fifo_clear;`
370			`wire fifo_rd;`
371			`wire [ 7: 0] fifo_rdata;`
372			`wire [ 7: 0] fifo_wdata;`
373			`reg fifo_wr;`
374			`reg ien_AE;`
375			`reg ien_AF;`
376			`wire ipen_AE;`
377			`wire ipen_AF;`
378			`reg pause_irq;`
379			`wire [ 7: 0] r_dat;`
380			`wire r_ena;`
381			`reg r_val;`
382			`wire rd_wfifo;`
383			`reg read_0;`
384			`reg readyfordata;`
385			`wire rfifo_full;`
386			`wire [ 5: 0] rfifo_used;`
387			`reg rvalid;`
388			`reg sim_r_ena;`
389			`reg sim_t_dat;`
390			`reg sim_t_ena;`
391			`reg sim_t_pause;`
392			`wire [ 7: 0] t_dat;`
393			`reg t_dav;`
394			`wire t_ena;`
395			`wire t_pause;`
396			`wire wfifo_empty;`
397			`wire [ 5: 0] wfifo_used;`
398			`reg woverflow;`
399			`wire wr_rfifo;`
400			`//avalon_jtag_slave, which is an e_avalon_slave`
401			`assign rd_wfifo = r_ena & ~wfifo_empty;`
402			`assign wr_rfifo = t_ena & ~rfifo_full;`
403			`assign fifo_clear = ~rst_n;`
404			`DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w the_DE0_NANO_SOC_QSYS_jtag_uart_scfifo_w`
405			`(`
406			`.clk (clk),`
407			`.fifo_FF (fifo_FF),`
408			`.fifo_clear (fifo_clear),`
409			`.fifo_wdata (fifo_wdata),`
410			`.fifo_wr (fifo_wr),`
411			`.r_dat (r_dat),`
412			`.rd_wfifo (rd_wfifo),`
413			`.wfifo_empty (wfifo_empty),`
414			`.wfifo_used (wfifo_used)`
415			`);`
416
417			`DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r the_DE0_NANO_SOC_QSYS_jtag_uart_scfifo_r`
418			`(`
419			`.clk (clk),`
420			`.fifo_EF (fifo_EF),`
421			`.fifo_clear (fifo_clear),`
422			`.fifo_rd (fifo_rd),`
423			`.fifo_rdata (fifo_rdata),`
424			`.rfifo_full (rfifo_full),`
425			`.rfifo_used (rfifo_used),`
426			`.rst_n (rst_n),`
427			`.t_dat (t_dat),`
428			`.wr_rfifo (wr_rfifo)`
429			`);`
430
431			`assign ipen_AE = ien_AE & fifo_AE;`
432			`assign ipen_AF = ien_AF & (pause_irq \| fifo_AF);`
433			`assign av_irq = ipen_AE \| ipen_AF;`
434			`assign activity = t_pause \| t_ena;`
435			`always @(posedge clk or negedge rst_n)`
436			`begin`
437			`if (rst_n == 0)`
438			`pause_irq <= 1'b0;`
439			`else // only if fifo is not empty...`
440			`if (t_pause & ~fifo_EF)`
441			`pause_irq <= 1'b1;`
442			`else if (read_0)`
443			`pause_irq <= 1'b0;`
444			`end`
445
446
447			`always @(posedge clk or negedge rst_n)`
448			`begin`
449			`if (rst_n == 0)`
450			`begin`
451			`r_val <= 1'b0;`
452			`t_dav <= 1'b1;`
453			`end`
454			`else`
455			`begin`
456			`r_val <= r_ena & ~wfifo_empty;`
457			`t_dav <= ~rfifo_full;`
458			`end`
459			`end`
460
461
462			`always @(posedge clk or negedge rst_n)`
463			`begin`
464			`if (rst_n == 0)`
465			`begin`
466			`fifo_AE <= 1'b0;`
467			`fifo_AF <= 1'b0;`
468			`fifo_wr <= 1'b0;`
469			`rvalid <= 1'b0;`
470			`read_0 <= 1'b0;`
471			`ien_AE <= 1'b0;`
472			`ien_AF <= 1'b0;`
473			`ac <= 1'b0;`
474			`woverflow <= 1'b0;`
475			`av_waitrequest <= 1'b1;`
476			`end`
477			`else`
478			`begin`
479			`fifo_AE <= {fifo_FF,wfifo_used} <= 8;`
480			`fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;`
481			`fifo_wr <= 1'b0;`
482			`read_0 <= 1'b0;`
483			`av_waitrequest <= ~(av_chipselect & (~av_write_n \| ~av_read_n) & av_waitrequest);`
484			`if (activity)`
485			`ac <= 1'b1;`
486			`// write`
487			`if (av_chipselect & ~av_write_n & av_waitrequest)`
488			`// addr 1 is control; addr 0 is data`
489			`if (av_address)`
490			`begin`
491			`ien_AF <= av_writedata[0];`
492			`ien_AE <= av_writedata[1];`
493			`if (av_writedata[10] & ~activity)`
494			`ac <= 1'b0;`
495			`end`
496			`else`
497			`begin`
498			`fifo_wr <= ~fifo_FF;`
499			`woverflow <= fifo_FF;`
500			`end`
501			`// read`
502			`if (av_chipselect & ~av_read_n & av_waitrequest)`
503			`begin`
504			`// addr 1 is interrupt; addr 0 is data`
505			`if (~av_address)`
506			`rvalid <= ~fifo_EF;`
507			`read_0 <= ~av_address;`
508			`end`
509			`end`
510			`end`
511
512
513			`assign fifo_wdata = av_writedata[7 : 0];`
514			`assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;`
515			`assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };`
516			`always @(posedge clk or negedge rst_n)`
517			`begin`
518			`if (rst_n == 0)`
519			`readyfordata <= 0;`
520			`else`
521			`readyfordata <= ~fifo_FF;`
522			`end`
523
524
525
526			`//synthesis translate_off`
527			`//////////////// SIMULATION-ONLY CONTENTS`
528			`// Tie off Atlantic Interface signals not used for simulation`
529			`always @(posedge clk)`
530			`begin`
531			`sim_t_pause <= 1'b0;`
532			`sim_t_ena <= 1'b0;`
533			`sim_t_dat <= t_dav ? r_dat : {8{r_val}};`
534			`sim_r_ena <= 1'b0;`
535			`end`
536
537
538			`assign r_ena = sim_r_ena;`
539			`assign t_ena = sim_t_ena;`
540			`assign t_dat = sim_t_dat;`
541			`assign t_pause = sim_t_pause;`
542			`always @(fifo_EF)`
543			`begin`
544			`dataavailable = ~fifo_EF;`
545			`end`
546
547
548
549			`//////////////// END SIMULATION-ONLY CONTENTS`
550
551			`//synthesis translate_on`
552			`//synthesis read_comments_as_HDL on`
553			`// alt_jtag_atlantic DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic`
554			`// (`
555			`// .clk (clk),`
556			`// .r_dat (r_dat),`
557			`// .r_ena (r_ena),`
558			`// .r_val (r_val),`
559			`// .rst_n (rst_n),`
560			`// .t_dat (t_dat),`
561			`// .t_dav (t_dav),`
562			`// .t_ena (t_ena),`
563			`// .t_pause (t_pause)`
564			`// );`
565			`//`
566			`// defparam DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,`
567			`// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,`
568			`// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,`
569			`// DE0_NANO_SOC_QSYS_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";`
570			`//`
571			`// always @(posedge clk or negedge rst_n)`
572			`// begin`
573			`// if (rst_n == 0)`
574			`// dataavailable <= 0;`
575			`// else`
576			`// dataavailable <= ~fifo_EF;`
577			`// end`
578			`//`
579			`//`
580			`//synthesis read_comments_as_HDL off`
581
582			`endmodule`
583