OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_QSYS/] [synthesis/] [submodules/] [DE0_NANO_SOC_QSYS_nios2_qsys.sdc] - Blame information for rev 221

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 221 olivier.gi
# Legal Notice: (C)2014 Altera Corporation. All rights reserved.  Your
2
# use of Altera Corporation's design tools, logic functions and other
3
# software and tools, and its AMPP partner logic functions, and any
4
# output files any of the foregoing (including device programming or
5
# simulation files), and any associated documentation or information are
6
# expressly subject to the terms and conditions of the Altera Program
7
# License Subscription Agreement or other applicable license agreement,
8
# including, without limitation, that your use is for the sole purpose
9
# of programming logic devices manufactured by Altera and sold by Altera
10
# or its authorized distributors.  Please refer to the applicable
11
# agreement for further details.
12
 
13
#**************************************************************
14
# Timequest JTAG clock definition
15
#   Uncommenting the following lines will define the JTAG
16
#   clock in TimeQuest Timing Analyzer
17
#**************************************************************
18
 
19
#create_clock -period 10MHz {altera_reserved_tck}
20
#set_clock_groups -asynchronous -group {altera_reserved_tck}
21
 
22
#**************************************************************
23
# Set TCL Path Variables
24
#**************************************************************
25
 
26
set     DE0_NANO_SOC_QSYS_nios2_qsys    DE0_NANO_SOC_QSYS_nios2_qsys:*
27
set     DE0_NANO_SOC_QSYS_nios2_qsys_oci        DE0_NANO_SOC_QSYS_nios2_qsys_nios2_oci:the_DE0_NANO_SOC_QSYS_nios2_qsys_nios2_oci
28
set     DE0_NANO_SOC_QSYS_nios2_qsys_oci_break  DE0_NANO_SOC_QSYS_nios2_qsys_nios2_oci_break:the_DE0_NANO_SOC_QSYS_nios2_qsys_nios2_oci_break
29
set     DE0_NANO_SOC_QSYS_nios2_qsys_ocimem     DE0_NANO_SOC_QSYS_nios2_qsys_nios2_ocimem:the_DE0_NANO_SOC_QSYS_nios2_qsys_nios2_ocimem
30
set     DE0_NANO_SOC_QSYS_nios2_qsys_oci_debug  DE0_NANO_SOC_QSYS_nios2_qsys_nios2_oci_debug:the_DE0_NANO_SOC_QSYS_nios2_qsys_nios2_oci_debug
31
set     DE0_NANO_SOC_QSYS_nios2_qsys_wrapper    DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_wrapper:the_DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_wrapper
32
set     DE0_NANO_SOC_QSYS_nios2_qsys_jtag_tck   DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_tck:the_DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_tck
33
set     DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sysclk        DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk:the_DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk
34
set     DE0_NANO_SOC_QSYS_nios2_qsys_oci_path    [format "%s|%s" $DE0_NANO_SOC_QSYS_nios2_qsys $DE0_NANO_SOC_QSYS_nios2_qsys_oci]
35
set     DE0_NANO_SOC_QSYS_nios2_qsys_oci_break_path      [format "%s|%s" $DE0_NANO_SOC_QSYS_nios2_qsys_oci_path $DE0_NANO_SOC_QSYS_nios2_qsys_oci_break]
36
set     DE0_NANO_SOC_QSYS_nios2_qsys_ocimem_path         [format "%s|%s" $DE0_NANO_SOC_QSYS_nios2_qsys_oci_path $DE0_NANO_SOC_QSYS_nios2_qsys_ocimem]
37
set     DE0_NANO_SOC_QSYS_nios2_qsys_oci_debug_path      [format "%s|%s" $DE0_NANO_SOC_QSYS_nios2_qsys_oci_path $DE0_NANO_SOC_QSYS_nios2_qsys_oci_debug]
38
set     DE0_NANO_SOC_QSYS_nios2_qsys_jtag_tck_path       [format "%s|%s|%s" $DE0_NANO_SOC_QSYS_nios2_qsys_oci_path $DE0_NANO_SOC_QSYS_nios2_qsys_wrapper $DE0_NANO_SOC_QSYS_nios2_qsys_jtag_tck]
39
set     DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sysclk_path    [format "%s|%s|%s" $DE0_NANO_SOC_QSYS_nios2_qsys_oci_path $DE0_NANO_SOC_QSYS_nios2_qsys_wrapper $DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sysclk]
40
set     DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sr     [format "%s|*sr" $DE0_NANO_SOC_QSYS_nios2_qsys_jtag_tck_path]
41
 
42
#**************************************************************
43
# Set False Paths
44
#**************************************************************
45
 
46
set_false_path -from [get_keepers *$DE0_NANO_SOC_QSYS_nios2_qsys_oci_break_path|break_readreg*] -to [get_keepers *$DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sr*]
47
set_false_path -from [get_keepers *$DE0_NANO_SOC_QSYS_nios2_qsys_oci_debug_path|*resetlatch]     -to [get_keepers *$DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sr[33]]
48
set_false_path -from [get_keepers *$DE0_NANO_SOC_QSYS_nios2_qsys_oci_debug_path|monitor_ready]  -to [get_keepers *$DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sr[0]]
49
set_false_path -from [get_keepers *$DE0_NANO_SOC_QSYS_nios2_qsys_oci_debug_path|monitor_error]  -to [get_keepers *$DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sr[34]]
50
set_false_path -from [get_keepers *$DE0_NANO_SOC_QSYS_nios2_qsys_ocimem_path|*MonDReg*] -to [get_keepers *$DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sr*]
51
set_false_path -from *$DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sr*    -to *$DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sysclk_path|*jdo*
52
set_false_path -from sld_hub:*|irf_reg* -to *$DE0_NANO_SOC_QSYS_nios2_qsys_jtag_sysclk_path|ir*
53
set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$DE0_NANO_SOC_QSYS_nios2_qsys_oci_debug_path|monitor_go

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.