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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_QSYS/] [synthesis/] [submodules/] [adc_ltc2308_fifo.v] - Blame information for rev 221

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/* note for avalon interface
        bus type: nagtive
        read legacy = 0 (to consistent to FIFO)
 
*/
 
module adc_ltc2308_fifo(
        // avalon slave port
        slave_clk,
        slave_reset_n,
        slave_chipselect_n,
        slave_addr,
        slave_read_n,
        slave_wrtie_n,
        slave_readdata,
        slave_wriredata,
 
        adc_clk, // max 40mhz
        // adc interface
        ADC_CONVST,
        ADC_SCK,
        ADC_SDI,
        ADC_SDO
);
 
        // avalon slave port
input                                                                   slave_clk;
input                                                                   slave_reset_n;
input                                                                   slave_chipselect_n;
input                                                                   slave_addr;
input                                                                   slave_read_n;
input                                                                   slave_wrtie_n;
output  reg     [15:0]                   slave_readdata;
input                           [15:0]                   slave_wriredata;
 
 
 
input                                                           adc_clk;
 
output                                  ADC_CONVST;
output                                  ADC_SCK;
output                          ADC_SDI;
input                                   ADC_SDO;
 
 
////////////////////////////////////
// avalon slave port
`define WRITE_REG_START_CH                              0
`define WRITE_REG_MEASURE_NUM                   1
 
// write for control
reg                             measure_fifo_start;
reg  [11:0]      measure_fifo_num;
reg     [2:0]            measure_fifo_ch;
always @ (posedge slave_clk or negedge slave_reset_n)
begin
        if (~slave_reset_n)
                measure_fifo_start <= 1'b0;
        else if (~slave_chipselect_n && ~slave_wrtie_n && slave_addr == `WRITE_REG_START_CH)
                {measure_fifo_ch, measure_fifo_start} <= slave_wriredata[3:0];
        else if (~slave_chipselect_n && ~slave_wrtie_n && slave_addr == `WRITE_REG_MEASURE_NUM)
                measure_fifo_num <= slave_wriredata;
end
 
///////////////////////
// read 
`define READ_REG_MEASURE_DONE   0
`define READ_REG_ADC_VALUE              1
wire slave_read_status;
wire slave_read_data;
 
 
assign slave_read_status = (~slave_chipselect_n && ~slave_read_n && slave_addr == `READ_REG_MEASURE_DONE) ?1'b1:1'b0;
assign slave_read_data = (~slave_chipselect_n && ~slave_read_n && slave_addr == `READ_REG_ADC_VALUE) ?1'b1:1'b0;
 
reg measure_fifo_done;
always @ (posedge slave_clk)
begin
        if (slave_read_status)
                slave_readdata <= {11'b0, measure_fifo_done};
        else if (slave_read_data)
                slave_readdata <= fifo_q;
end
 
reg pre_slave_read_data;
always @ (posedge slave_clk or negedge slave_reset_n)
begin
        if (~slave_reset_n)
                pre_slave_read_data <= 1'b0;
        else
                pre_slave_read_data <= slave_read_data;
end
 
// read ack for adc data. (note. Slave_read_data is read lency=2, so slave_read_data is assert two clock)
assign fifo_rdreq = (pre_slave_read_data & slave_read_data)?1'b1:1'b0;
 
////////////////////////////////////
// create triggle message: adc_reset_n
 
reg pre_measure_fifo_start;
always @ (posedge adc_clk)
begin
        pre_measure_fifo_start <= measure_fifo_start;
end
 
wire adc_reset_n;
assign adc_reset_n = (~pre_measure_fifo_start & measure_fifo_start)?1'b0:1'b1;
 
////////////////////////////////////
// control measure_start 
reg [11:0] measure_count;
 
reg config_first;
reg wait_measure_done;
reg measure_start;
wire measure_done;
wire [11:0] measure_dataread;
 
always @ (posedge adc_clk or negedge adc_reset_n)
begin
        if (~adc_reset_n)
        begin
                measure_start <= 1'b0;
                config_first <= 1'b1;
                measure_count <= 0;
                measure_fifo_done <= 1'b0;
                wait_measure_done <= 1'b0;
        end
        else if (~measure_fifo_done & ~measure_start & ~wait_measure_done)
        begin
                measure_start <= 1'b1;
                wait_measure_done <= 1'b1;
        end
        else if (wait_measure_done) // && measure_start)
        begin
                measure_start <= 1'b0;
                if (measure_done)
                begin
                        if (config_first)
                                config_first <= 1'b0;
                        else
                        begin   // read data and save into fifo
 
                                if (measure_count < measure_fifo_num) // && ~fifo_wrfull)
                                begin
                                        measure_count <= measure_count + 1;
                                        wait_measure_done <= 1'b0;
                                end
                                else
                                        measure_fifo_done <= 1'b1;
                        end
                end
        end
end
 
 
// write data into fifo
 
reg pre_measure_done;
 
always @ (posedge adc_clk or negedge adc_reset_n)
begin
        if (~adc_reset_n)
                pre_measure_done <= 1'b0;
        else
                pre_measure_done <= measure_done;
end
 
assign fifo_wrreq = (~pre_measure_done & measure_done & ~config_first)?1'b1:1'b0;
 
 
///////////////////////////////////////
// SPI
 
adc_ltc2308 adc_ltc2308_inst(
        .clk(adc_clk), // max 40mhz
 
        // start measure
        .measure_start(measure_start), // posedge triggle
        .measure_done(measure_done),
        .measure_ch(measure_fifo_ch),
        .measure_dataread(measure_dataread),
 
 
        // adc interface
        .ADC_CONVST(ADC_CONVST),
        .ADC_SCK(ADC_SCK),
        .ADC_SDI(ADC_SDI),
        .ADC_SDO(ADC_SDO)
);
 
 
///////////////////////////////////////
// FIFO
wire fifo_wrfull;
wire fifo_rdempty;
wire  fifo_wrreq;
wire [11:0]       fifo_q;
wire fifo_rdreq;
 
 
adc_data_fifo adc_data_fifo_inst(
        .aclr(~adc_reset_n),
        .data(measure_dataread),
        .rdclk(slave_clk),
        .rdreq(fifo_rdreq),
        .wrclk(adc_clk),
        .wrreq(fifo_wrreq),
        .q(fifo_q),
        .rdempty(fifo_rdempty),
        .wrfull(fifo_wrfull)
);
 
 
endmodule
 

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [DE0_NANO_SOC_ADC/] [DE0_NANO_SOC_QSYS/] [synthesis/] [submodules/] [adc_ltc2308_fifo.v] - Blame information for rev 221

Line No.	Rev	Author	Line
1	221	olivier.gi	`/* note for avalon interface`
2			`bus type: nagtive`
3			`read legacy = 0 (to consistent to FIFO)`
4
5			`*/`
6
7			`module adc_ltc2308_fifo(`
8			`// avalon slave port`
9			`slave_clk,`
10			`slave_reset_n,`
11			`slave_chipselect_n,`
12			`slave_addr,`
13			`slave_read_n,`
14			`slave_wrtie_n,`
15			`slave_readdata,`
16			`slave_wriredata,`
17
18			`adc_clk, // max 40mhz`
19			`// adc interface`
20			`ADC_CONVST,`
21			`ADC_SCK,`
22			`ADC_SDI,`
23			`ADC_SDO`
24			`);`
25
26			`// avalon slave port`
27			`input slave_clk;`
28			`input slave_reset_n;`
29			`input slave_chipselect_n;`
30			`input slave_addr;`
31			`input slave_read_n;`
32			`input slave_wrtie_n;`
33			`output reg [15:0] slave_readdata;`
34			`input [15:0] slave_wriredata;`
35
36
37
38			`input adc_clk;`
39
40			`output ADC_CONVST;`
41			`output ADC_SCK;`
42			`output ADC_SDI;`
43			`input ADC_SDO;`
44
45
46			`////////////////////////////////////`
47			`// avalon slave port`
48			`define WRITE_REG_START_CH 0
49			`define WRITE_REG_MEASURE_NUM 1
50
51			`// write for control`
52			`reg measure_fifo_start;`
53			`reg [11:0] measure_fifo_num;`
54			`reg [2:0] measure_fifo_ch;`
55			`always @ (posedge slave_clk or negedge slave_reset_n)`
56			`begin`
57			`if (~slave_reset_n)`
58			`measure_fifo_start <= 1'b0;`
59			else if (~slave_chipselect_n && ~slave_wrtie_n && slave_addr == `WRITE_REG_START_CH)
60			`{measure_fifo_ch, measure_fifo_start} <= slave_wriredata[3:0];`
61			else if (~slave_chipselect_n && ~slave_wrtie_n && slave_addr == `WRITE_REG_MEASURE_NUM)
62			`measure_fifo_num <= slave_wriredata;`
63			`end`
64
65			`///////////////////////`
66			`// read`
67			`define READ_REG_MEASURE_DONE 0
68			`define READ_REG_ADC_VALUE 1
69			`wire slave_read_status;`
70			`wire slave_read_data;`
71
72
73			assign slave_read_status = (~slave_chipselect_n && ~slave_read_n && slave_addr == `READ_REG_MEASURE_DONE) ?1'b1:1'b0;
74			assign slave_read_data = (~slave_chipselect_n && ~slave_read_n && slave_addr == `READ_REG_ADC_VALUE) ?1'b1:1'b0;
75
76			`reg measure_fifo_done;`
77			`always @ (posedge slave_clk)`
78			`begin`
79			`if (slave_read_status)`
80			`slave_readdata <= {11'b0, measure_fifo_done};`
81			`else if (slave_read_data)`
82			`slave_readdata <= fifo_q;`
83			`end`
84
85			`reg pre_slave_read_data;`
86			`always @ (posedge slave_clk or negedge slave_reset_n)`
87			`begin`
88			`if (~slave_reset_n)`
89			`pre_slave_read_data <= 1'b0;`
90			`else`
91			`pre_slave_read_data <= slave_read_data;`
92			`end`
93
94			`// read ack for adc data. (note. Slave_read_data is read lency=2, so slave_read_data is assert two clock)`
95			`assign fifo_rdreq = (pre_slave_read_data & slave_read_data)?1'b1:1'b0;`
96
97			`////////////////////////////////////`
98			`// create triggle message: adc_reset_n`
99
100			`reg pre_measure_fifo_start;`
101			`always @ (posedge adc_clk)`
102			`begin`
103			`pre_measure_fifo_start <= measure_fifo_start;`
104			`end`
105
106			`wire adc_reset_n;`
107			`assign adc_reset_n = (~pre_measure_fifo_start & measure_fifo_start)?1'b0:1'b1;`
108
109			`////////////////////////////////////`
110			`// control measure_start`
111			`reg [11:0] measure_count;`
112
113			`reg config_first;`
114			`reg wait_measure_done;`
115			`reg measure_start;`
116			`wire measure_done;`
117			`wire [11:0] measure_dataread;`
118
119			`always @ (posedge adc_clk or negedge adc_reset_n)`
120			`begin`
121			`if (~adc_reset_n)`
122			`begin`
123			`measure_start <= 1'b0;`
124			`config_first <= 1'b1;`
125			`measure_count <= 0;`
126			`measure_fifo_done <= 1'b0;`
127			`wait_measure_done <= 1'b0;`
128			`end`
129			`else if (~measure_fifo_done & ~measure_start & ~wait_measure_done)`
130			`begin`
131			`measure_start <= 1'b1;`
132			`wait_measure_done <= 1'b1;`
133			`end`
134			`else if (wait_measure_done) // && measure_start)`
135			`begin`
136			`measure_start <= 1'b0;`
137			`if (measure_done)`
138			`begin`
139			`if (config_first)`
140			`config_first <= 1'b0;`
141			`else`
142			`begin // read data and save into fifo`
143
144			`if (measure_count < measure_fifo_num) // && ~fifo_wrfull)`
145			`begin`
146			`measure_count <= measure_count + 1;`
147			`wait_measure_done <= 1'b0;`
148			`end`
149			`else`
150			`measure_fifo_done <= 1'b1;`
151			`end`
152			`end`
153			`end`
154			`end`
155
156
157			`// write data into fifo`
158
159			`reg pre_measure_done;`
160
161			`always @ (posedge adc_clk or negedge adc_reset_n)`
162			`begin`
163			`if (~adc_reset_n)`
164			`pre_measure_done <= 1'b0;`
165			`else`
166			`pre_measure_done <= measure_done;`
167			`end`
168
169			`assign fifo_wrreq = (~pre_measure_done & measure_done & ~config_first)?1'b1:1'b0;`
170
171
172			`///////////////////////////////////////`
173			`// SPI`
174
175			`adc_ltc2308 adc_ltc2308_inst(`
176			`.clk(adc_clk), // max 40mhz`
177
178			`// start measure`
179			`.measure_start(measure_start), // posedge triggle`
180			`.measure_done(measure_done),`
181			`.measure_ch(measure_fifo_ch),`
182			`.measure_dataread(measure_dataread),`
183
184
185			`// adc interface`
186			`.ADC_CONVST(ADC_CONVST),`
187			`.ADC_SCK(ADC_SCK),`
188			`.ADC_SDI(ADC_SDI),`
189			`.ADC_SDO(ADC_SDO)`
190			`);`
191
192
193			`///////////////////////////////////////`
194			`// FIFO`
195			`wire fifo_wrfull;`
196			`wire fifo_rdempty;`
197			`wire fifo_wrreq;`
198			`wire [11:0] fifo_q;`
199			`wire fifo_rdreq;`
200
201
202			`adc_data_fifo adc_data_fifo_inst(`
203			`.aclr(~adc_reset_n),`
204			`.data(measure_dataread),`
205			`.rdclk(slave_clk),`
206			`.rdreq(fifo_rdreq),`
207			`.wrclk(adc_clk),`
208			`.wrreq(fifo_wrreq),`
209			`.q(fifo_q),`
210			`.rdempty(fifo_rdempty),`
211			`.wrfull(fifo_wrfull)`
212			`);`
213
214
215			`endmodule`
216