Subversion Repositories openmsp430

# TCL File Generated by Component Editor 13.1

# Thu May 08 16:25:08 CST 2014

# DO NOT MODIFY

# 

# adc_ltc2308 "adc_ltc2308" v1.1

# Richard 2014.05.08.16:25:08

# for DE2-SoC  (no level shift version)

# 

# 

# request TCL package from ACDS 13.1

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package require -exact qsys 13.1

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# module adc_ltc2308

# 

set_module_property DESCRIPTION "for DE2-SoC  (no level shift version)"

set_module_property NAME adc_ltc2308

set_module_property VERSION 1.1

set_module_property INTERNAL false

set_module_property OPAQUE_ADDRESS_MAP true

set_module_property GROUP "Terasic Qsys Component"

set_module_property AUTHOR Richard

set_module_property DISPLAY_NAME adc_ltc2308

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property ANALYZE_HDL AUTO

set_module_property REPORT_TO_TALKBACK false

set_module_property ALLOW_GREYBOX_GENERATION false

# 

# file sets

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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""

set_fileset_property QUARTUS_SYNTH TOP_LEVEL adc_ltc2308_fifo

set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false

add_fileset_file adc_ltc2308_fifo.v VERILOG PATH adc_ltc2308_fifo.v TOP_LEVEL_FILE

add_fileset_file adc_ltc2308.v VERILOG PATH adc_ltc2308.v

add_fileset_file adc_data_fifo.v VERILOG PATH adc_data_fifo.v

# 

# parameters

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# 

# display items

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# 

# connection point slave

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add_interface slave avalon end

set_interface_property slave addressAlignment NATIVE

set_interface_property slave addressUnits WORDS

set_interface_property slave associatedClock clock_sink

set_interface_property slave associatedReset reset_sink

set_interface_property slave bitsPerSymbol 8

set_interface_property slave burstOnBurstBoundariesOnly false

set_interface_property slave burstcountUnits WORDS

set_interface_property slave explicitAddressSpan 0

set_interface_property slave holdTime 0

set_interface_property slave linewrapBursts false

set_interface_property slave maximumPendingReadTransactions 0

set_interface_property slave readLatency 0

set_interface_property slave readWaitTime 1

set_interface_property slave setupTime 0

set_interface_property slave timingUnits Cycles

set_interface_property slave writeWaitTime 0

set_interface_property slave ENABLED true

set_interface_property slave EXPORT_OF ""

set_interface_property slave PORT_NAME_MAP ""

set_interface_property slave CMSIS_SVD_VARIABLES ""

set_interface_property slave SVD_ADDRESS_GROUP ""

add_interface_port slave slave_chipselect_n chipselect_n Input 1

add_interface_port slave slave_read_n read_n Input 1

add_interface_port slave slave_readdata readdata Output 16

add_interface_port slave slave_addr address Input 1

add_interface_port slave slave_wrtie_n write_n Input 1

add_interface_port slave slave_wriredata writedata Input 16

set_interface_assignment slave embeddedsw.configuration.isFlash 0

set_interface_assignment slave embeddedsw.configuration.isMemoryDevice 0

set_interface_assignment slave embeddedsw.configuration.isNonVolatileStorage 0

set_interface_assignment slave embeddedsw.configuration.isPrintableDevice 0

# 

# connection point conduit_end

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add_interface conduit_end conduit end

set_interface_property conduit_end associatedClock ""

set_interface_property conduit_end associatedReset ""

set_interface_property conduit_end ENABLED true

set_interface_property conduit_end EXPORT_OF ""

set_interface_property conduit_end PORT_NAME_MAP ""

set_interface_property conduit_end CMSIS_SVD_VARIABLES ""

set_interface_property conduit_end SVD_ADDRESS_GROUP ""

add_interface_port conduit_end ADC_CONVST export Output 1

add_interface_port conduit_end ADC_SCK export Output 1

add_interface_port conduit_end ADC_SDI export Output 1

add_interface_port conduit_end ADC_SDO export Input 1

# 

# connection point reset_sink

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add_interface reset_sink reset end

set_interface_property reset_sink associatedClock clock_sink

set_interface_property reset_sink synchronousEdges DEASSERT

set_interface_property reset_sink ENABLED true

set_interface_property reset_sink EXPORT_OF ""

set_interface_property reset_sink PORT_NAME_MAP ""

set_interface_property reset_sink CMSIS_SVD_VARIABLES ""

set_interface_property reset_sink SVD_ADDRESS_GROUP ""

add_interface_port reset_sink slave_reset_n reset_n Input 1

# 

# connection point clock_sink

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add_interface clock_sink clock end

set_interface_property clock_sink clockRate 0

set_interface_property clock_sink ENABLED true

set_interface_property clock_sink EXPORT_OF ""

set_interface_property clock_sink PORT_NAME_MAP ""

set_interface_property clock_sink CMSIS_SVD_VARIABLES ""

set_interface_property clock_sink SVD_ADDRESS_GROUP ""

add_interface_port clock_sink slave_clk clk Input 1

# 

# connection point clock_sink_adc

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add_interface clock_sink_adc clock end

set_interface_property clock_sink_adc clockRate 0

set_interface_property clock_sink_adc ENABLED true

set_interface_property clock_sink_adc EXPORT_OF ""

set_interface_property clock_sink_adc PORT_NAME_MAP ""

set_interface_property clock_sink_adc CMSIS_SVD_VARIABLES ""

set_interface_property clock_sink_adc SVD_ADDRESS_GROUP ""

add_interface_port clock_sink_adc adc_clk clk Input 1