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olivier.gi |
/*
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* system.h - SOPC Builder system and BSP software package information
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*
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* Machine generated for CPU 'nios2_qsys' in SOPC Builder design 'DE0_NANO_SOC_QSYS'
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* SOPC Builder design path: ../../DE0_NANO_SOC_QSYS.sopcinfo
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*
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* Generated: Thu Dec 18 16:09:20 CST 2014
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*/
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/*
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* DO NOT MODIFY THIS FILE
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*
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* Changing this file will have subtle consequences
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* which will almost certainly lead to a nonfunctioning
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* system. If you do modify this file, be aware that your
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* changes will be overwritten and lost when this file
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* is generated again.
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*
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* DO NOT MODIFY THIS FILE
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*/
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/*
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* License Agreement
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*
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* Copyright (c) 2008
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* Altera Corporation, San Jose, California, USA.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* This agreement shall be governed in all respects by the laws of the State
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* of California and by the laws of the United States of America.
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*/
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#ifndef __SYSTEM_H_
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#define __SYSTEM_H_
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/* Include definitions from linker script generator */
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#include "linker.h"
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/*
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* CPU configuration
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*
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*/
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#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys"
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#define ALT_CPU_BIG_ENDIAN 0
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#define ALT_CPU_BREAK_ADDR 0x00080820
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#define ALT_CPU_CPU_FREQ 100000000u
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#define ALT_CPU_CPU_ID_SIZE 1
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#define ALT_CPU_CPU_ID_VALUE 0x00000000
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#define ALT_CPU_CPU_IMPLEMENTATION "fast"
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#define ALT_CPU_DATA_ADDR_WIDTH 0x14
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#define ALT_CPU_DCACHE_LINE_SIZE 32
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#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
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#define ALT_CPU_DCACHE_SIZE 2048
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#define ALT_CPU_EXCEPTION_ADDR 0x00040020
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#define ALT_CPU_FLUSHDA_SUPPORTED
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#define ALT_CPU_FREQ 100000000
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#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
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#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
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#define ALT_CPU_HARDWARE_MULX_PRESENT 0
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#define ALT_CPU_HAS_DEBUG_CORE 1
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#define ALT_CPU_HAS_DEBUG_STUB
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#define ALT_CPU_HAS_JMPI_INSTRUCTION
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#define ALT_CPU_ICACHE_LINE_SIZE 32
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#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
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#define ALT_CPU_ICACHE_SIZE 4096
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#define ALT_CPU_INITDA_SUPPORTED
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#define ALT_CPU_INST_ADDR_WIDTH 0x14
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#define ALT_CPU_NAME "nios2_qsys"
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#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
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#define ALT_CPU_RESET_ADDR 0x00040000
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/*
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* CPU configuration (with legacy prefix - don't use these anymore)
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*
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*/
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#define NIOS2_BIG_ENDIAN 0
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#define NIOS2_BREAK_ADDR 0x00080820
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#define NIOS2_CPU_FREQ 100000000u
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#define NIOS2_CPU_ID_SIZE 1
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#define NIOS2_CPU_ID_VALUE 0x00000000
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#define NIOS2_CPU_IMPLEMENTATION "fast"
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#define NIOS2_DATA_ADDR_WIDTH 0x14
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#define NIOS2_DCACHE_LINE_SIZE 32
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#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
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#define NIOS2_DCACHE_SIZE 2048
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#define NIOS2_EXCEPTION_ADDR 0x00040020
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#define NIOS2_FLUSHDA_SUPPORTED
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#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
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#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
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#define NIOS2_HARDWARE_MULX_PRESENT 0
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#define NIOS2_HAS_DEBUG_CORE 1
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#define NIOS2_HAS_DEBUG_STUB
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#define NIOS2_HAS_JMPI_INSTRUCTION
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#define NIOS2_ICACHE_LINE_SIZE 32
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#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
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#define NIOS2_ICACHE_SIZE 4096
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#define NIOS2_INITDA_SUPPORTED
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#define NIOS2_INST_ADDR_WIDTH 0x14
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#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
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#define NIOS2_RESET_ADDR 0x00040000
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/*
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* Define for each module class mastered by the CPU
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*
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*/
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#define __ADC_LTC2308
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#define __ALTERA_AVALON_JTAG_UART
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#define __ALTERA_AVALON_ONCHIP_MEMORY2
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#define __ALTERA_AVALON_PIO
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#define __ALTERA_AVALON_SYSID_QSYS
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#define __ALTERA_NIOS2_QSYS
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/*
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* System configuration
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*
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*/
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#define ALT_DEVICE_FAMILY "Cyclone V"
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#define ALT_ENHANCED_INTERRUPT_API_PRESENT
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#define ALT_IRQ_BASE NULL
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#define ALT_LOG_PORT "/dev/null"
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#define ALT_LOG_PORT_BASE 0x0
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#define ALT_LOG_PORT_DEV null
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#define ALT_LOG_PORT_TYPE ""
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#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
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#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
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#define ALT_NUM_INTERRUPT_CONTROLLERS 1
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#define ALT_STDERR "/dev/jtag_uart"
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#define ALT_STDERR_BASE 0x81000
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#define ALT_STDERR_DEV jtag_uart
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#define ALT_STDERR_IS_JTAG_UART
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#define ALT_STDERR_PRESENT
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#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
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#define ALT_STDIN "/dev/jtag_uart"
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#define ALT_STDIN_BASE 0x81000
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#define ALT_STDIN_DEV jtag_uart
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#define ALT_STDIN_IS_JTAG_UART
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#define ALT_STDIN_PRESENT
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#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
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#define ALT_STDOUT "/dev/jtag_uart"
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#define ALT_STDOUT_BASE 0x81000
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#define ALT_STDOUT_DEV jtag_uart
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#define ALT_STDOUT_IS_JTAG_UART
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#define ALT_STDOUT_PRESENT
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#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
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#define ALT_SYSTEM_NAME "DE0_NANO_SOC_QSYS"
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/*
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* adc_ltc2308 configuration
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*
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*/
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#define ADC_LTC2308_BASE 0x81010
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#define ADC_LTC2308_IRQ -1
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#define ADC_LTC2308_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define ADC_LTC2308_NAME "/dev/adc_ltc2308"
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#define ADC_LTC2308_SPAN 8
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#define ADC_LTC2308_TYPE "adc_ltc2308"
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#define ALT_MODULE_CLASS_adc_ltc2308 adc_ltc2308
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/*
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* hal configuration
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*
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*/
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#define ALT_MAX_FD 32
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#define ALT_SYS_CLK none
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#define ALT_TIMESTAMP_CLK none
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/*
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* jtag_uart configuration
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*
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*/
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#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
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#define JTAG_UART_BASE 0x81000
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#define JTAG_UART_IRQ 0
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#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
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#define JTAG_UART_NAME "/dev/jtag_uart"
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#define JTAG_UART_READ_DEPTH 64
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#define JTAG_UART_READ_THRESHOLD 8
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#define JTAG_UART_SPAN 8
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#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
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#define JTAG_UART_WRITE_DEPTH 64
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#define JTAG_UART_WRITE_THRESHOLD 8
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/*
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* onchip_memory2 configuration
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*
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*/
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#define ALT_MODULE_CLASS_onchip_memory2 altera_avalon_onchip_memory2
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#define ONCHIP_MEMORY2_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
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#define ONCHIP_MEMORY2_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
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#define ONCHIP_MEMORY2_BASE 0x40000
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#define ONCHIP_MEMORY2_CONTENTS_INFO ""
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#define ONCHIP_MEMORY2_DUAL_PORT 0
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#define ONCHIP_MEMORY2_GUI_RAM_BLOCK_TYPE "AUTO"
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#define ONCHIP_MEMORY2_INIT_CONTENTS_FILE "DE0_NANO_SOC_QSYS_onchip_memory2"
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#define ONCHIP_MEMORY2_INIT_MEM_CONTENT 1
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#define ONCHIP_MEMORY2_INSTANCE_ID "NONE"
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#define ONCHIP_MEMORY2_IRQ -1
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#define ONCHIP_MEMORY2_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define ONCHIP_MEMORY2_NAME "/dev/onchip_memory2"
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#define ONCHIP_MEMORY2_NON_DEFAULT_INIT_FILE_ENABLED 0
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#define ONCHIP_MEMORY2_RAM_BLOCK_TYPE "AUTO"
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#define ONCHIP_MEMORY2_READ_DURING_WRITE_MODE "DONT_CARE"
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#define ONCHIP_MEMORY2_SINGLE_CLOCK_OP 0
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#define ONCHIP_MEMORY2_SIZE_MULTIPLE 1
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#define ONCHIP_MEMORY2_SIZE_VALUE 160000
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#define ONCHIP_MEMORY2_SPAN 160000
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#define ONCHIP_MEMORY2_TYPE "altera_avalon_onchip_memory2"
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#define ONCHIP_MEMORY2_WRITABLE 1
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/*
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* sw configuration
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*
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*/
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#define ALT_MODULE_CLASS_sw altera_avalon_pio
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#define SW_BASE 0x0
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#define SW_BIT_CLEARING_EDGE_REGISTER 0
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#define SW_BIT_MODIFYING_OUTPUT_REGISTER 0
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#define SW_CAPTURE 1
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#define SW_DATA_WIDTH 10
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#define SW_DO_TEST_BENCH_WIRING 0
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#define SW_DRIVEN_SIM_VALUE 0
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#define SW_EDGE_TYPE "ANY"
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#define SW_FREQ 100000000
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#define SW_HAS_IN 1
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#define SW_HAS_OUT 0
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#define SW_HAS_TRI 0
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#define SW_IRQ 1
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#define SW_IRQ_INTERRUPT_CONTROLLER_ID 0
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#define SW_IRQ_TYPE "EDGE"
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#define SW_NAME "/dev/sw"
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#define SW_RESET_VALUE 0
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#define SW_SPAN 16
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#define SW_TYPE "altera_avalon_pio"
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/*
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* sysid_qsys configuration
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*
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*/
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#define ALT_MODULE_CLASS_sysid_qsys altera_avalon_sysid_qsys
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#define SYSID_QSYS_BASE 0x81008
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#define SYSID_QSYS_ID 0
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#define SYSID_QSYS_IRQ -1
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#define SYSID_QSYS_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define SYSID_QSYS_NAME "/dev/sysid_qsys"
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#define SYSID_QSYS_SPAN 8
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#define SYSID_QSYS_TIMESTAMP 1418889131
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#define SYSID_QSYS_TYPE "altera_avalon_sysid_qsys"
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#endif /* __SYSTEM_H_ */
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