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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [my_first_fpga/] [simple_counter.v] - Blame information for rev 221

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//It has a single clock input and a 32-bit output port
 
module simple_counter (
                        CLOCK_50,
                        counter_out
                       );
 
input   CLOCK_50 ;
output [31:0] counter_out;
reg    [31:0] counter_out;
 
always @ (posedge CLOCK_50)                // on positive clock edge
        begin
                counter_out <= #1 counter_out + 1;   // increment counter
        end
endmodule                                  // end of module counter

Line No.	Rev	Author	Line
1	221	olivier.gi	`//It has a single clock input and a 32-bit output port`
2
3			`module simple_counter (`
4			`CLOCK_50,`
5			`counter_out`
6			`);`
7
8			`input CLOCK_50 ;`
9			`output [31:0] counter_out;`
10			`reg [31:0] counter_out;`
11
12			`always @ (posedge CLOCK_50) // on positive clock edge`
13			`begin`
14			`counter_out <= #1 counter_out + 1; // increment counter`
15			`end`
16			`endmodule // end of module counter`

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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [doc/] [Terasic/] [DE0_NANO_SOC/] [Demonstrations/] [FPGA/] [my_first_fpga/] [simple_counter.v] - Blame information for rev 221