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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [rtl/] [verilog/] [opengfx430/] [ogfx_backend.v] - Blame information for rev 222

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1 221 olivier.gi 
//----------------------------------------------------------------------------
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// Copyright (C) 2015 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: ogfx_backend.v
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//
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// *Module Description:
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//                      Backend module of the graphic controller.
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//                      The purpose of this block is to:
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//
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//                          - fetch the data from the specified frame buffer
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//                          - convert data depending on selected video mode
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//
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// *Author(s):
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//              - Olivier Girard,    olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev$
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// $LastChangedBy$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_defines.v"
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`endif
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module  ogfx_backend (
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// OUTPUTs
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    refresh_data_o,                               // Display refresh data
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    refresh_data_ready_o,                         // Display refresh new data is ready
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    vid_ram_addr_o,                               // Video-RAM refresh address
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    vid_ram_cen_o,                                // Video-RAM refresh enable (active low)
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`ifdef WITH_PROGRAMMABLE_LUT
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    lut_ram_addr_o,                               // LUT-RAM refresh address
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    lut_ram_cen_o,                                // LUT-RAM refresh enable (active low)
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`endif
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// INPUTs
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    mclk,                                         // Main system clock
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    puc_rst,                                      // Main system reset
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    display_width_i,                              // Display width
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    display_height_i,                             // Display height
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    display_size_i,                               // Display size (number of pixels)
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    display_y_swap_i,                             // Display configuration: swap Y axis (horizontal symmetry)
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    display_x_swap_i,                             // Display configuration: swap X axis (vertical symmetry)
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    display_cl_swap_i,                            // Display configuration: swap column/lines
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    gfx_mode_i,                                   // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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`ifdef WITH_PROGRAMMABLE_LUT
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    lut_ram_dout_i,                               // LUT-RAM data output
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    lut_ram_dout_rdy_nxt_i,                       // LUT-RAM data output ready during next cycle
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`endif
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    vid_ram_dout_i,                               // Video-RAM data output
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    vid_ram_dout_rdy_nxt_i,                       // Video-RAM data output ready during next cycle
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    refresh_active_i,                             // Display refresh on going
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    refresh_data_request_i,                       // Display refresh new data request
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    refresh_frame_base_addr_i,                    // Refresh frame base address
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    hw_lut_palette_sel_i,                         // Hardware LUT palette configuration
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    hw_lut_bgcolor_i,                             // Hardware LUT background-color selection
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    hw_lut_fgcolor_i,                             // Hardware LUT foreground-color selection
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    sw_lut_enable_i,                              // Refresh LUT-RAM enable
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    sw_lut_bank_select_i                          // Refresh LUT-RAM bank selection
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);
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// OUTPUTs
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//=========
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output        [15:0] refresh_data_o;              // Display refresh data
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output               refresh_data_ready_o;        // Display refresh new data is ready
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output [`VRAM_MSB:0] vid_ram_addr_o;              // Video-RAM refresh address
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output               vid_ram_cen_o;               // Video-RAM refresh enable (active low)
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`ifdef WITH_PROGRAMMABLE_LUT
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output [`LRAM_MSB:0] lut_ram_addr_o;              // LUT-RAM refresh address
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output               lut_ram_cen_o;               // LUT-RAM refresh enable (active low)
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`endif
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// INPUTs
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//=========
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input                mclk;                        // Main system clock
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input                puc_rst;                     // Main system reset
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input  [`LPIX_MSB:0] display_width_i;             // Display width
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input  [`LPIX_MSB:0] display_height_i;            // Display height
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input  [`SPIX_MSB:0] display_size_i;              // Display size (number of pixels)
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input                display_y_swap_i;            // Display configuration: swap Y axis (horizontal symmetry)
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input                display_x_swap_i;            // Display configuration: swap X axis (vertical symmetry)
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input                display_cl_swap_i;           // Display configuration: swap column/lines
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input          [2:0] gfx_mode_i;                  // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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`ifdef WITH_PROGRAMMABLE_LUT
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input         [15:0] lut_ram_dout_i;              // LUT-RAM data output
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input                lut_ram_dout_rdy_nxt_i;      // LUT-RAM data output ready during next cycle
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`endif
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input         [15:0] vid_ram_dout_i;              // Video-RAM data output
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input                vid_ram_dout_rdy_nxt_i;      // Video-RAM data output ready during next cycle
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input                refresh_active_i;            // Display refresh on going
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input                refresh_data_request_i;      // Display refresh new data request
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input  [`APIX_MSB:0] refresh_frame_base_addr_i;   // Refresh frame base address
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input          [2:0] hw_lut_palette_sel_i;        // Hardware LUT palette configuration
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input          [3:0] hw_lut_bgcolor_i;            // Hardware LUT background-color selection
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input          [3:0] hw_lut_fgcolor_i;            // Hardware LUT foreground-color selection
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input                sw_lut_enable_i;             // Refresh LUT-RAM enable
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input                sw_lut_bank_select_i;        // Refresh LUT-RAM bank selection
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//=============================================================================
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// 1)  WIRE, REGISTERS AND PARAMETER DECLARATION
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//=============================================================================
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// Wires
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wire  [15:0] frame_data;
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wire         frame_data_ready;
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wire         frame_data_request;
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//============================================================================
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// 2) FRAME MEMORY ACCESS
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//============================================================================
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ogfx_backend_frame_fifo  ogfx_backend_frame_fifo_inst (
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// OUTPUTs
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    .frame_data_o                  ( frame_data                ),  // Frame data
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    .frame_data_ready_o            ( frame_data_ready          ),  // Frame data ready
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    .vid_ram_addr_o                ( vid_ram_addr_o            ),  // Video-RAM address
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    .vid_ram_cen_o                 ( vid_ram_cen_o             ),  // Video-RAM enable (active low)
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// INPUTs
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    .mclk                          ( mclk                      ),  // Main system clock
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    .puc_rst                       ( puc_rst                   ),  // Main system reset
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    .display_width_i               ( display_width_i           ),  // Display width
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    .display_height_i              ( display_height_i          ),  // Display height
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    .display_size_i                ( display_size_i            ),  // Display size (number of pixels)
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    .display_y_swap_i              ( display_y_swap_i          ),  // Display configuration: swap Y axis (horizontal symmetry)
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    .display_x_swap_i              ( display_x_swap_i          ),  // Display configuration: swap X axis (vertical symmetry)
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    .display_cl_swap_i             ( display_cl_swap_i         ),  // Display configuration: swap column/lines
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    .frame_data_request_i          ( frame_data_request        ),  // Request for next frame data
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    .gfx_mode_i                    ( gfx_mode_i                ),  // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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    .vid_ram_dout_i                ( vid_ram_dout_i            ),  // Video-RAM data output
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    .vid_ram_dout_rdy_nxt_i        ( vid_ram_dout_rdy_nxt_i    ),  // Video-RAM data output ready during next cycle
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    .refresh_active_i              ( refresh_active_i          ),  // Display refresh on going
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    .refresh_frame_base_addr_i     ( refresh_frame_base_addr_i )   // Refresh frame base address
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);
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//============================================================================
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// 3) LUT MEMORY ACCESS
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//============================================================================
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ogfx_backend_lut_fifo  ogfx_backend_lut_fifo_inst (
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// OUTPUTs
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    .frame_data_request_o          ( frame_data_request        ),  // Request for next frame data
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    .refresh_data_o                ( refresh_data_o            ),  // Display Refresh data
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    .refresh_data_ready_o          ( refresh_data_ready_o      ),  // Display Refresh data ready
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`ifdef WITH_PROGRAMMABLE_LUT
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    .lut_ram_addr_o                ( lut_ram_addr_o            ),  // LUT-RAM address
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    .lut_ram_cen_o                 ( lut_ram_cen_o             ),  // LUT-RAM enable (active low)
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`endif
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// INPUTs
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    .mclk                          ( mclk                      ),  // Main system clock
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    .puc_rst                       ( puc_rst                   ),  // Main system reset
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    .frame_data_i                  ( frame_data                ),  // Frame data
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    .frame_data_ready_i            ( frame_data_ready          ),  // Frame data ready
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    .gfx_mode_i                    ( gfx_mode_i                ),  // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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`ifdef WITH_PROGRAMMABLE_LUT
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    .lut_ram_dout_i                ( lut_ram_dout_i            ),  // LUT-RAM data output
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    .lut_ram_dout_rdy_nxt_i        ( lut_ram_dout_rdy_nxt_i    ),  // LUT-RAM data output ready during next cycle
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`endif
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    .refresh_active_i              ( refresh_active_i          ),  // Display refresh on going
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    .refresh_data_request_i        ( refresh_data_request_i    ),  // Request for next refresh data
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    .hw_lut_palette_sel_i          ( hw_lut_palette_sel_i      ),  // Hardware LUT palette configuration
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    .hw_lut_bgcolor_i              ( hw_lut_bgcolor_i          ),  // Hardware LUT background-color selection
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    .hw_lut_fgcolor_i              ( hw_lut_fgcolor_i          ),  // Hardware LUT foreground-color selection
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    .sw_lut_enable_i               ( sw_lut_enable_i           ),  // Refresh LUT-RAM enable
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    .sw_lut_bank_select_i          ( sw_lut_bank_select_i      )   // Refresh LUT-RAM bank selection
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);
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endmodule // ogfx_backend
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_undefines.v"
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`endif

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