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olivier.gi |
//----------------------------------------------------------------------------
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// Copyright (C) 2015 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: ogfx_backend_lut_fifo.v
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//
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// *Module Description:
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// Mini-cache memory for the LUT memory accesses.
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev$
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// $LastChangedBy$
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// $LastChangedDate$
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//----------------------------------------------------------------------------
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`ifdef OGFX_NO_INCLUDE
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`else
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`include "openGFX430_defines.v"
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`endif
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module ogfx_backend_lut_fifo (
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// OUTPUTs
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frame_data_request_o, // Request for next frame data
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refresh_data_o, // Display Refresh data
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refresh_data_ready_o, // Display Refresh data ready
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`ifdef WITH_PROGRAMMABLE_LUT
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lut_ram_addr_o, // LUT-RAM address
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lut_ram_cen_o, // LUT-RAM enable (active low)
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`endif
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// INPUTs
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mclk, // Main system clock
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puc_rst, // Main system reset
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frame_data_i, // Frame data
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frame_data_ready_i, // Frame data ready
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gfx_mode_i, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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`ifdef WITH_PROGRAMMABLE_LUT
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lut_ram_dout_i, // LUT-RAM data output
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lut_ram_dout_rdy_nxt_i, // LUT-RAM data output ready during next cycle
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`endif
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refresh_active_i, // Display refresh on going
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refresh_data_request_i, // Request for next refresh data
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refresh_lut_select_i // Refresh LUT bank selection
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);
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// OUTPUTs
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//=========
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output frame_data_request_o; // Request for next frame data
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output [15:0] refresh_data_o; // Display Refresh data
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output refresh_data_ready_o; // Display Refresh data ready
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`ifdef WITH_PROGRAMMABLE_LUT
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output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
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output lut_ram_cen_o; // LUT-RAM enable (active low)
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`endif
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// INPUTs
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//=========
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input mclk; // Main system clock
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input puc_rst; // Main system reset
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input [15:0] frame_data_i; // Frame data
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input frame_data_ready_i; // Frame data ready
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input [2:0] gfx_mode_i; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
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`ifdef WITH_PROGRAMMABLE_LUT
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input [15:0] lut_ram_dout_i; // LUT-RAM data output
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input lut_ram_dout_rdy_nxt_i; // LUT-RAM data output ready during next cycle
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`endif
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input refresh_active_i; // Display refresh on going
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input refresh_data_request_i; // Request for next refresh data
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input [1:0] refresh_lut_select_i; // Refresh LUT bank selection
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//=============================================================================
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// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
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//=============================================================================
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// State machine registers
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reg [1:0] lut_state;
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reg [1:0] lut_state_nxt;
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// State definition
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parameter STATE_IDLE = 0,
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STATE_FRAME_DATA = 1,
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STATE_LUT_DATA = 2,
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STATE_HOLD = 3;
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// Some parameter(s)
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parameter FIFO_EMPTY = 3'h0,
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FIFO_FULL = 3'h5;
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// Video modes decoding
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wire gfx_mode_1_bpp = (gfx_mode_i == 3'b000);
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wire gfx_mode_2_bpp = (gfx_mode_i == 3'b001);
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wire gfx_mode_4_bpp = (gfx_mode_i == 3'b010);
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wire gfx_mode_8_bpp = (gfx_mode_i == 3'b011);
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wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp |
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gfx_mode_2_bpp | gfx_mode_1_bpp);
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// Others
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reg [2:0] fifo_counter;
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wire [2:0] fifo_counter_nxt;
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//============================================================================
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// 2) HARD CODED LOOKUP TABLE
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//============================================================================
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wire [15:0] lut_hw_data_1_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[0] ==1'b0 }}) | // 1 bpp: Black
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({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[0] ==1'b1 }}) ; // White
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wire [15:0] lut_hw_data_2_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[1:0]==2'b00 }}) | // 2 bpp: Black
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({5'b01000, 6'b010000, 5'b01000} & {16{frame_data_i[1:0]==2'b01 }}) | // Dark Gray
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({5'b11000, 6'b110000, 5'b11000} & {16{frame_data_i[1:0]==2'b10 }}) | // Light Gray
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({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[1:0]==2'b11 }}) ; // White
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wire [15:0] lut_hw_data_4_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0000}}) | // 4 bpp: Black
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({5'b00000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0001}}) | // Dark Blue
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({5'b10000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0010}}) | // Dark Red
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({5'b10000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0011}}) | // Dark Magenta
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({5'b00000, 6'b100000, 5'b00000} & {16{frame_data_i[3:0]==4'b0100}}) | // Dark Green
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({5'b00000, 6'b100000, 5'b10000} & {16{frame_data_i[3:0]==4'b0101}}) | // Dark Cyan
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({5'b10000, 6'b100000, 5'b00000} & {16{frame_data_i[3:0]==4'b0110}}) | // Dark Yellow
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({5'b10000, 6'b100000, 5'b10000} & {16{frame_data_i[3:0]==4'b0111}}) | // Gray
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({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b1000}}) | // Black
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({5'b00000, 6'b000000, 5'b11111} & {16{frame_data_i[3:0]==4'b1001}}) | // Blue
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({5'b11111, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b1010}}) | // Red
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({5'b11111, 6'b000000, 5'b11111} & {16{frame_data_i[3:0]==4'b1011}}) | // Magenta
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({5'b00000, 6'b111111, 5'b00000} & {16{frame_data_i[3:0]==4'b1100}}) | // Green
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({5'b00000, 6'b111111, 5'b11111} & {16{frame_data_i[3:0]==4'b1101}}) | // Cyan
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({5'b11111, 6'b111111, 5'b00000} & {16{frame_data_i[3:0]==4'b1110}}) | // Yellow
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({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[3:0]==4'b1111}}); // White
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wire [15:0] lut_hw_data_8_bpp = {frame_data_i[7],frame_data_i[6],frame_data_i[5],frame_data_i[5],frame_data_i[5], // 8 bpp: R = D<7,6,5,5,5>
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frame_data_i[4],frame_data_i[3],frame_data_i[2],frame_data_i[2],frame_data_i[2],frame_data_i[2], // G = D<4,3,2,2,2,2>
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frame_data_i[1],frame_data_i[0],frame_data_i[0],frame_data_i[0],frame_data_i[0]}; // B = D<1,0,0,0,0>
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wire [15:0] lut_hw_data = (lut_hw_data_1_bpp & {16{gfx_mode_1_bpp}}) |
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(lut_hw_data_2_bpp & {16{gfx_mode_2_bpp}}) |
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(lut_hw_data_4_bpp & {16{gfx_mode_4_bpp}}) |
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(lut_hw_data_8_bpp & {16{gfx_mode_8_bpp}});
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wire lut_hw_enabled = ~gfx_mode_16_bpp & ~refresh_lut_select_i[0];
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wire lut_sw_enabled = ~gfx_mode_16_bpp & refresh_lut_select_i[0];
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//============================================================================
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// 3) STATE MACHINE
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//============================================================================
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//--------------------------------
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// States Transitions
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//--------------------------------
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always @(lut_state or refresh_active_i or frame_data_ready_i or
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`ifdef WITH_PROGRAMMABLE_LUT
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lut_sw_enabled or lut_ram_dout_rdy_nxt_i or
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`endif
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fifo_counter_nxt)
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case(lut_state)
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STATE_IDLE : lut_state_nxt = ~refresh_active_i ? STATE_IDLE : STATE_FRAME_DATA ;
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STATE_FRAME_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
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~frame_data_ready_i ? STATE_FRAME_DATA :
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`ifdef WITH_PROGRAMMABLE_LUT
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lut_sw_enabled ? STATE_LUT_DATA :
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`endif
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STATE_HOLD ;
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`ifdef WITH_PROGRAMMABLE_LUT
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STATE_LUT_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
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lut_ram_dout_rdy_nxt_i ? STATE_HOLD : STATE_LUT_DATA ;
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`endif
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STATE_HOLD : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
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(fifo_counter_nxt!=FIFO_FULL) ? STATE_FRAME_DATA : STATE_HOLD ;
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// pragma coverage off
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default : lut_state_nxt = STATE_IDLE;
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// pragma coverage on
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endcase
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//--------------------------------
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// State machine
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//--------------------------------
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) lut_state <= STATE_IDLE;
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else lut_state <= lut_state_nxt;
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// Request for the next frame data
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assign frame_data_request_o = (lut_state == STATE_FRAME_DATA);
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//============================================================================
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// 4) LUT MEMORY INTERFACE
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//============================================================================
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//--------------------------------
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// Enable
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//--------------------------------
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`ifdef WITH_PROGRAMMABLE_LUT
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assign lut_ram_cen_o = ~(lut_state == STATE_LUT_DATA);
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`endif
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//--------------------------------
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// Address
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//--------------------------------
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// Mask with chip enable to save power
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`ifdef WITH_PROGRAMMABLE_LUT
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`ifdef WITH_EXTRA_LUT_BANK
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// Allow LUT bank switching only when the refresh is not on going
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reg refresh_lut_bank_select_sync;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) refresh_lut_bank_select_sync <= 1'b0;
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else if (~refresh_active_i) refresh_lut_bank_select_sync <= refresh_lut_select_i[1];
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assign lut_ram_addr_o = {refresh_lut_bank_select_sync, frame_data_i[7:0]} & {9{~lut_ram_cen_o}};
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`else
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assign lut_ram_addr_o = frame_data_i[7:0] & {8{~lut_ram_cen_o}};
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`endif
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`endif
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//--------------------------------
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// Data Ready
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//--------------------------------
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// When filling the FIFO, the data is available on the bus
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// one cycle after the rdy_nxt signal
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reg lut_ram_dout_ready;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) lut_ram_dout_ready <= 1'b0;
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`ifdef WITH_PROGRAMMABLE_LUT
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else lut_ram_dout_ready <= lut_sw_enabled ? lut_ram_dout_rdy_nxt_i :
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(frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
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`else
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else lut_ram_dout_ready <= (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
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`endif
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//============================================================================
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// 5) FIFO COUNTER
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//============================================================================
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// Control signals
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wire fifo_push = lut_ram_dout_ready & (fifo_counter != FIFO_FULL);
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wire fifo_pop = refresh_data_request_i & (fifo_counter != FIFO_EMPTY);
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// Fifo counter
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assign fifo_counter_nxt = ~refresh_active_i ? FIFO_EMPTY : // Initialize
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(fifo_push & fifo_pop) ? fifo_counter : // Keep value (pop & push at the same time)
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fifo_push ? fifo_counter + 3'h1 : // Push
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fifo_pop ? fifo_counter - 3'h1 : // Pop
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fifo_counter; // Hold
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) fifo_counter <= FIFO_EMPTY;
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else fifo_counter <= fifo_counter_nxt;
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//============================================================================
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// 6) FIFO MEMORY & RD/WR POINTERS
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//============================================================================
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// Write pointer
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reg [2:0] wr_ptr;
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) wr_ptr <= 3'h0;
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else if (~refresh_active_i) wr_ptr <= 3'h0;
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else if (fifo_push)
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|
|
begin
|
305 |
|
|
if (wr_ptr==(FIFO_FULL-1)) wr_ptr <= 3'h0;
|
306 |
|
|
else wr_ptr <= wr_ptr + 3'h1;
|
307 |
|
|
end
|
308 |
|
|
|
309 |
|
|
// Memory
|
310 |
|
|
reg [15:0] fifo_mem [0:4];
|
311 |
|
|
always @(posedge mclk or posedge puc_rst)
|
312 |
|
|
if (puc_rst)
|
313 |
|
|
begin
|
314 |
|
|
fifo_mem[0] <= 16'h0000;
|
315 |
|
|
fifo_mem[1] <= 16'h0000;
|
316 |
|
|
fifo_mem[2] <= 16'h0000;
|
317 |
|
|
fifo_mem[3] <= 16'h0000;
|
318 |
|
|
fifo_mem[4] <= 16'h0000;
|
319 |
|
|
end
|
320 |
|
|
else if (fifo_push)
|
321 |
|
|
begin
|
322 |
|
|
fifo_mem[wr_ptr] <= lut_hw_enabled ? lut_hw_data :
|
323 |
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
324 |
|
|
lut_sw_enabled ? lut_ram_dout_i :
|
325 |
|
|
`endif
|
326 |
|
|
frame_data_i;
|
327 |
|
|
end
|
328 |
|
|
|
329 |
|
|
// Read pointer
|
330 |
|
|
reg [2:0] rd_ptr;
|
331 |
|
|
always @(posedge mclk or posedge puc_rst)
|
332 |
|
|
if (puc_rst) rd_ptr <= 3'h0;
|
333 |
|
|
else if (~refresh_active_i) rd_ptr <= 3'h0;
|
334 |
|
|
else if (fifo_pop)
|
335 |
|
|
begin
|
336 |
|
|
if (rd_ptr==(FIFO_FULL-1)) rd_ptr <= 3'h0;
|
337 |
|
|
else rd_ptr <= rd_ptr + 3'h1;
|
338 |
|
|
end
|
339 |
|
|
|
340 |
|
|
//============================================================================
|
341 |
|
|
// 7) REFRESH_DATA
|
342 |
|
|
//============================================================================
|
343 |
|
|
|
344 |
|
|
// Refresh Data is ready
|
345 |
|
|
reg refresh_data_ready_o;
|
346 |
|
|
always @(posedge mclk or posedge puc_rst)
|
347 |
|
|
if (puc_rst) refresh_data_ready_o <= 1'h0;
|
348 |
|
|
else if (~refresh_active_i) refresh_data_ready_o <= 1'h0;
|
349 |
|
|
else refresh_data_ready_o <= fifo_pop;
|
350 |
|
|
|
351 |
|
|
// Refresh Data
|
352 |
|
|
reg [15:0] refresh_data_o;
|
353 |
|
|
always @(posedge mclk or posedge puc_rst)
|
354 |
|
|
if (puc_rst) refresh_data_o <= 16'h0000;
|
355 |
|
|
else if (fifo_pop) refresh_data_o <= fifo_mem[rd_ptr];
|
356 |
|
|
|
357 |
|
|
|
358 |
|
|
endmodule // ogfx_backend_lut_fifo
|
359 |
|
|
|
360 |
|
|
`ifdef OGFX_NO_INCLUDE
|
361 |
|
|
`else
|
362 |
|
|
`include "openGFX430_undefines.v"
|
363 |
|
|
`endif
|