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[/] [openmsp430/] [trunk/] [fpga/] [altera_de0_nano_soc/] [software/] [apps/] [gfx_demo/] [main.c] - Blame information for rev 222

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Line No. Rev Author Line
1 221 olivier.gi
#include "omsp_system.h"
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#include "timerA.h"
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#include "gfx_controller.h"
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#include "demo.h"
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//---------------------------------------------------//
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// Watchdog interrupt                                //
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// Change Video Mode every 327ms * 15 = 4.2seconds   //
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//---------------------------------------------------//
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volatile unsigned char wdt_irq_cnt;
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volatile unsigned char move_to_next_mode;
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wakeup interrupt (WDT_VECTOR) INT_watchdog(void) {
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  if (wdt_irq_cnt<100) {
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    wdt_irq_cnt++;
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  } else {
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    wdt_irq_cnt       = 0;
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    move_to_next_mode = 1;
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  }
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}
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//---------------------------------------------------//
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// Graphic mode initialization                       //
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//---------------------------------------------------//
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void gfx_mode_init(uint16_t gfx_mode, uint16_t refresh_rate) {
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  //unsigned int idx;
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  // Initialize Graphic controller
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  init_gfx_ctrl(gfx_mode, refresh_rate);
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  // Initialize palette
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  //LUT_RAM_ADDR    = 0x0000;
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  //for( idx = 0; idx < 256; idx = idx + 1 ) {
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  //  LUT_RAM_DATA  = palette_64k[idx];
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  //}
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39 222 olivier.gi
  // LUT Configuration
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  LUT_CFG      = HW_LUT_BG_BLACK     |
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                 HW_LUT_FG_WHITE     |
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                 HW_LUT_PALETTE_0_HI |
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                 SW_LUT_BANK0_SELECT |
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                 SW_LUT_DISABLE;
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46 221 olivier.gi
  // Initialize Frame pointers
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  FRAME0_PTR   = PIX_ADDR(0, 0);
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  FRAME1_PTR   = PIX_ADDR(0, 0);
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  FRAME_SELECT = REFRESH_FRAME0_SELECT  |
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                 VID_RAM0_FRAME0_SELECT |
52 222 olivier.gi
                 VID_RAM1_FRAME0_SELECT;
53 221 olivier.gi
 
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  // Start Graphic controller
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  start_gfx_ctrl();
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}
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//---------------------------------------------------//
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// Main                                              //
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//---------------------------------------------------//
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int main(void) {
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  // Init global variables
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  wdt_irq_cnt       = 0;
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  move_to_next_mode = 0;
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  // Configure watchdog timer to generate an IRQ every 327ms
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  WDTCTL = WDTPW | WDTSSEL | WDTCNTCL | WDTTMSEL | WDTIS0;  // Select ACLK | Clear timer | Enable interval timer mode | div32768
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  IE1_set_wdtie();
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  eint();
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  while (1) {
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    gfx_mode_init(GFX_16_BPP, LT24_REFR_62_FPS);
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    demo_16bpp();
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    move_to_next_mode = 0;
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    gfx_mode_init(GFX_8_BPP,  LT24_REFR_1000_FPS);
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    demo_8bpp();
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    move_to_next_mode = 0;
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    gfx_mode_init(GFX_4_BPP,  LT24_REFR_1000_FPS);
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    demo_4bpp();
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    move_to_next_mode = 0;
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    gfx_mode_init(GFX_2_BPP,  LT24_REFR_1000_FPS);
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    demo_2bpp();
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    move_to_next_mode = 0;
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    gfx_mode_init(GFX_1_BPP,  LT24_REFR_1000_FPS);
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    demo_1bpp();
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    move_to_next_mode = 0;
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  };
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  return 0;
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}

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