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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [openmsp430/] [openMSP430_undefines.v] - Blame information for rev 202

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Line No. Rev Author Line
1 157 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2009 , Olivier Girard
3
//
4
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15
//
16
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27
//
28
//----------------------------------------------------------------------------
29 202 olivier.gi
//
30 157 olivier.gi
// *File Name: openMSP430_undefines.v
31 202 olivier.gi
//
32 157 olivier.gi
// *Module Description:
33
//                      openMSP430 Verilog `undef file
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39
// $Rev: 23 $
40
// $LastChangedBy: olivier.girard $
41
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
42
//----------------------------------------------------------------------------
43
 
44
//----------------------------------------------------------------------------
45
// BASIC SYSTEM CONFIGURATION
46
//----------------------------------------------------------------------------
47
 
48
// Program Memory sizes
49
`ifdef PMEM_SIZE_CUSTOM
50
`undef PMEM_SIZE_CUSTOM
51
`endif
52
`ifdef PMEM_SIZE_59_KB
53
`undef PMEM_SIZE_59_KB
54
`endif
55
`ifdef PMEM_SIZE_55_KB
56
`undef PMEM_SIZE_55_KB
57
`endif
58
`ifdef PMEM_SIZE_54_KB
59
`undef PMEM_SIZE_54_KB
60
`endif
61
`ifdef PMEM_SIZE_51_KB
62
`undef PMEM_SIZE_51_KB
63
`endif
64
`ifdef PMEM_SIZE_48_KB
65
`undef PMEM_SIZE_48_KB
66
`endif
67
`ifdef PMEM_SIZE_41_KB
68
`undef PMEM_SIZE_41_KB
69
`endif
70
`ifdef PMEM_SIZE_32_KB
71
`undef PMEM_SIZE_32_KB
72
`endif
73
`ifdef PMEM_SIZE_24_KB
74
`undef PMEM_SIZE_24_KB
75
`endif
76
`ifdef PMEM_SIZE_16_KB
77
`undef PMEM_SIZE_16_KB
78
`endif
79
`ifdef PMEM_SIZE_12_KB
80
`undef PMEM_SIZE_12_KB
81
`endif
82
`ifdef PMEM_SIZE_8_KB
83
`undef PMEM_SIZE_8_KB
84
`endif
85
`ifdef PMEM_SIZE_4_KB
86
`undef PMEM_SIZE_4_KB
87
`endif
88
`ifdef PMEM_SIZE_2_KB
89
`undef PMEM_SIZE_2_KB
90
`endif
91
`ifdef PMEM_SIZE_1_KB
92
`undef PMEM_SIZE_1_KB
93
`endif
94
 
95
// Data Memory sizes
96
`ifdef DMEM_SIZE_CUSTOM
97
`undef DMEM_SIZE_CUSTOM
98
`endif
99
`ifdef DMEM_SIZE_32_KB
100
`undef DMEM_SIZE_32_KB
101
`endif
102
`ifdef DMEM_SIZE_24_KB
103
`undef DMEM_SIZE_24_KB
104
`endif
105
`ifdef DMEM_SIZE_16_KB
106
`undef DMEM_SIZE_16_KB
107
`endif
108
`ifdef DMEM_SIZE_10_KB
109
`undef DMEM_SIZE_10_KB
110
`endif
111
`ifdef DMEM_SIZE_8_KB
112
`undef DMEM_SIZE_8_KB
113
`endif
114
`ifdef DMEM_SIZE_5_KB
115
`undef DMEM_SIZE_5_KB
116
`endif
117
`ifdef DMEM_SIZE_4_KB
118
`undef DMEM_SIZE_4_KB
119
`endif
120
`ifdef DMEM_SIZE_2p5_KB
121
`undef DMEM_SIZE_2p5_KB
122
`endif
123
`ifdef DMEM_SIZE_2_KB
124
`undef DMEM_SIZE_2_KB
125
`endif
126
`ifdef DMEM_SIZE_1_KB
127
`undef DMEM_SIZE_1_KB
128
`endif
129
`ifdef DMEM_SIZE_512_B
130
`undef DMEM_SIZE_512_B
131
`endif
132
`ifdef DMEM_SIZE_256_B
133
`undef DMEM_SIZE_256_B
134
`endif
135
`ifdef DMEM_SIZE_128_B
136
`undef DMEM_SIZE_128_B
137
`endif
138
 
139
// Include/Exclude Hardware Multiplier
140
`ifdef MULTIPLIER
141
`undef MULTIPLIER
142
`endif
143
 
144
// Include Debug interface
145
`ifdef DBG_EN
146
`undef DBG_EN
147
`endif
148
 
149
 
150
//----------------------------------------------------------------------------
151
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
152
//----------------------------------------------------------------------------
153
 
154
// Custom user version number
155
`ifdef USER_VERSION
156
`undef USER_VERSION
157
`endif
158
 
159
// Include/Exclude Watchdog timer
160
`ifdef WATCHDOG
161
`undef WATCHDOG
162
`endif
163
 
164 202 olivier.gi
// Include/Exclude DMA interface support
165
`ifdef DMA_IF_EN
166
`undef DMA_IF_EN
167
`endif
168
 
169 157 olivier.gi
// Include/Exclude Non-Maskable-Interrupt support
170
`ifdef NMI
171
`undef NMI
172
`endif
173
 
174 193 olivier.gi
// Number of available IRQs
175
`ifdef IRQ_16
176
`undef IRQ_16
177
`endif
178
`ifdef IRQ_32
179
`undef IRQ_32
180
`endif
181
`ifdef IRQ_64
182
`undef IRQ_64
183
`endif
184
 
185 157 olivier.gi
// Input synchronizers
186
`ifdef SYNC_NMI
187
`undef SYNC_NMI
188
`endif
189
`ifdef SYNC_CPU_EN
190
`undef SYNC_CPU_EN
191
`endif
192
`ifdef SYNC_DBG_EN
193
`undef SYNC_DBG_EN
194
`endif
195
 
196
// Peripheral Memory Space:
197
`ifdef PER_SIZE_CUSTOM
198
`undef PER_SIZE_CUSTOM
199
`endif
200
`ifdef PER_SIZE_32_KB
201
`undef PER_SIZE_32_KB
202
`endif
203
`ifdef PER_SIZE_16_KB
204
`undef PER_SIZE_16_KB
205
`endif
206
`ifdef PER_SIZE_8_KB
207
`undef PER_SIZE_8_KB
208
`endif
209
`ifdef PER_SIZE_4_KB
210
`undef PER_SIZE_4_KB
211
`endif
212
`ifdef PER_SIZE_2_KB
213
`undef PER_SIZE_2_KB
214
`endif
215
`ifdef PER_SIZE_1_KB
216
`undef PER_SIZE_1_KB
217
`endif
218
`ifdef PER_SIZE_512_B
219
`undef PER_SIZE_512_B
220
`endif
221
 
222
// Let the CPU break after a PUC occurrence by default
223
`ifdef DBG_RST_BRK_EN
224
`undef DBG_RST_BRK_EN
225
`endif
226
 
227
 
228
//----------------------------------------------------------------------------
229
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
230
//----------------------------------------------------------------------------
231
 
232
// Serial Debug interface protocol
233
`ifdef DBG_UART
234
`undef DBG_UART
235
`endif
236
`ifdef DBG_I2C
237
`undef DBG_I2C
238
`endif
239
 
240
// Enable the I2C broadcast address
241
`ifdef DBG_I2C_BROADCAST
242
`undef DBG_I2C_BROADCAST
243
`endif
244
 
245
// Number of hardware breakpoint units
246
`ifdef DBG_HWBRK_0
247
`undef DBG_HWBRK_0
248
`endif
249
`ifdef DBG_HWBRK_1
250
`undef DBG_HWBRK_1
251
`endif
252
`ifdef DBG_HWBRK_2
253
`undef DBG_HWBRK_2
254
`endif
255
`ifdef DBG_HWBRK_3
256
`undef DBG_HWBRK_3
257
`endif
258
 
259
// Enable/Disable the hardware breakpoint RANGE mode
260
`ifdef DBG_HWBRK_RANGE
261
`undef DBG_HWBRK_RANGE
262
`endif
263
 
264
// Custom Program/Data and Peripheral Memory Spaces
265
`undef PMEM_CUSTOM_AWIDTH
266
`undef PMEM_CUSTOM_SIZE
267
`undef DMEM_CUSTOM_AWIDTH
268
`undef DMEM_CUSTOM_SIZE
269
`undef PER_CUSTOM_AWIDTH
270
`undef PER_CUSTOM_SIZE
271
 
272
// ASIC version
273
`ifdef ASIC
274
`undef ASIC
275
`endif
276
 
277
 
278
//----------------------------------------------------------------------------
279
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
280
//----------------------------------------------------------------------------
281
 
282 181 olivier.gi
// ASIC/FPGA-like clocking
283
`ifdef ASIC_CLOCKING
284
`undef ASIC_CLOCKING
285
`endif
286
 
287 157 olivier.gi
// Fine grained clock gating
288
`ifdef CLOCK_GATING
289
`undef CLOCK_GATING
290
`endif
291
 
292
// LFXT clock domain
293
`ifdef LFXT_DOMAIN
294
`undef LFXT_DOMAIN
295
`endif
296
 
297
// MCLK: Clock Mux
298
`ifdef MCLK_MUX
299
`undef MCLK_MUX
300
`endif
301
 
302
// SMCLK: Clock Mux
303
`ifdef SMCLK_MUX
304
`undef SMCLK_MUX
305
`endif
306
 
307
// WATCHDOG: Clock Mux
308
`ifdef WATCHDOG_MUX
309
`undef WATCHDOG_MUX
310
`endif
311
`ifdef WATCHDOG_NOMUX_ACLK
312
`undef WATCHDOG_NOMUX_ACLK
313
`endif
314
 
315
// MCLK: Clock divider
316
`ifdef MCLK_DIVIDER
317
`undef MCLK_DIVIDER
318
`endif
319
 
320
// SMCLK: Clock divider (/1/2/4/8)
321
`ifdef SMCLK_DIVIDER
322
`undef SMCLK_DIVIDER
323
`endif
324
 
325
// ACLK: Clock divider (/1/2/4/8)
326
`ifdef ACLK_DIVIDER
327
`undef ACLK_DIVIDER
328
`endif
329
 
330
// LOW POWER MODE: CPUOFF
331
`ifdef CPUOFF_EN
332
`undef CPUOFF_EN
333
`endif
334
 
335
// LOW POWER MODE: SCG0
336
`ifdef SCG0_EN
337
`undef SCG0_EN
338
`endif
339
 
340
// LOW POWER MODE: SCG1
341
`ifdef SCG1_EN
342
`undef SCG1_EN
343
`endif
344
 
345
// LOW POWER MODE: OSCOFF
346
`ifdef OSCOFF_EN
347
`undef OSCOFF_EN
348
`endif
349
 
350
 
351
//==========================================================================//
352
//==========================================================================//
353
//==========================================================================//
354
//==========================================================================//
355
//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
356
//==========================================================================//
357
//==========================================================================//
358
//==========================================================================//
359
//==========================================================================//
360
 
361
// Program Memory Size
362
`ifdef PMEM_AWIDTH
363
`undef PMEM_AWIDTH
364
`endif
365
`ifdef PMEM_SIZE
366
`undef PMEM_SIZE
367
`endif
368
 
369
// Data Memory Size
370
`ifdef DMEM_AWIDTH
371
`undef DMEM_AWIDTH
372
`endif
373
`ifdef DMEM_SIZE
374
`undef DMEM_SIZE
375
`endif
376
 
377
// Peripheral Memory Size
378
`ifdef PER_AWIDTH
379
`undef PER_AWIDTH
380
`endif
381
`ifdef PER_SIZE
382
`undef PER_SIZE
383
`endif
384
 
385
// Data Memory Base Adresses
386
`ifdef DMEM_BASE
387
`undef DMEM_BASE
388
`endif
389
 
390
// Program & Data Memory most significant address bit (for 16 bit words)
391
`ifdef PMEM_MSB
392
`undef PMEM_MSB
393
`endif
394
`ifdef DMEM_MSB
395
`undef DMEM_MSB
396
`endif
397
`ifdef PER_MSB
398
`undef PER_MSB
399
`endif
400
 
401 193 olivier.gi
// Number of available IRQs
402
`ifdef IRQ_NR
403
`undef IRQ_NR
404
`endif
405
`ifdef IRQ_NR_GE_32
406
`undef IRQ_NR_GE_32
407
`endif
408
 
409 157 olivier.gi
// Instructions type
410
`ifdef INST_SO
411
`undef INST_SO
412
`endif
413
`ifdef INST_JMP
414
`undef INST_JMP
415
`endif
416
`ifdef INST_TO
417
`undef INST_TO
418
`endif
419
 
420
// Single-operand arithmetic
421
`ifdef RRC
422
`undef RRC
423
`endif
424
`ifdef SWPB
425
`undef SWPB
426
`endif
427
`ifdef RRA
428
`undef RRA
429
`endif
430
`ifdef SXT
431
`undef SXT
432
`endif
433
`ifdef PUSH
434
`undef PUSH
435
`endif
436
`ifdef CALL
437
`undef CALL
438
`endif
439
`ifdef RETI
440
`undef RETI
441
`endif
442
`ifdef IRQ
443
`undef IRQ
444
`endif
445
 
446
// Conditional jump
447
`ifdef JNE
448
`undef JNE
449
`endif
450
`ifdef JEQ
451
`undef JEQ
452
`endif
453
`ifdef JNC
454
`undef JNC
455
`endif
456
`ifdef JC
457
`undef JC
458
`endif
459
`ifdef JN
460
`undef JN
461
`endif
462
`ifdef JGE
463
`undef JGE
464
`endif
465
`ifdef JL
466
`undef JL
467
`endif
468
`ifdef JMP
469
`undef JMP
470
`endif
471
 
472
// Two-operand arithmetic
473
`ifdef MOV
474
`undef MOV
475
`endif
476
`ifdef ADD
477
`undef ADD
478
`endif
479
`ifdef ADDC
480
`undef ADDC
481
`endif
482
`ifdef SUBC
483
`undef SUBC
484
`endif
485
`ifdef SUB
486
`undef SUB
487
`endif
488
`ifdef CMP
489
`undef CMP
490
`endif
491
`ifdef DADD
492
`undef DADD
493
`endif
494
`ifdef BIT
495
`undef BIT
496
`endif
497
`ifdef BIC
498
`undef BIC
499
`endif
500
`ifdef BIS
501
`undef BIS
502
`endif
503
`ifdef XOR
504
`undef XOR
505
`endif
506
`ifdef AND
507
`undef AND
508
`endif
509
 
510
// Addressing modes
511
`ifdef DIR
512
`undef DIR
513
`endif
514
`ifdef IDX
515
`undef IDX
516
`endif
517
`ifdef INDIR
518
`undef INDIR
519
`endif
520
`ifdef INDIR_I
521
`undef INDIR_I
522
`endif
523
`ifdef SYMB
524
`undef SYMB
525
`endif
526
`ifdef IMM
527
`undef IMM
528
`endif
529
`ifdef ABS
530
`undef ABS
531
`endif
532
`ifdef CONST
533
`undef CONST
534
`endif
535
 
536
// Instruction state machine
537
`ifdef I_IRQ_FETCH
538
`undef I_IRQ_FETCH
539
`endif
540
`ifdef I_IRQ_DONE
541
`undef I_IRQ_DONE
542
`endif
543
`ifdef I_DEC
544
`undef I_DEC
545
`endif
546
`ifdef I_EXT1
547
`undef I_EXT1
548
`endif
549
`ifdef I_EXT2
550
`undef I_EXT2
551
`endif
552
`ifdef I_IDLE
553
`undef I_IDLE
554
`endif
555
 
556
// Execution state machine
557
`ifdef E_IRQ_0
558
`undef E_IRQ_0
559
`endif
560
`ifdef E_IRQ_1
561
`undef E_IRQ_1
562
`endif
563
`ifdef E_IRQ_2
564
`undef E_IRQ_2
565
`endif
566
`ifdef E_IRQ_3
567
`undef E_IRQ_3
568
`endif
569
`ifdef E_IRQ_4
570
`undef E_IRQ_4
571
`endif
572
`ifdef E_SRC_AD
573
`undef E_SRC_AD
574
`endif
575
`ifdef E_SRC_RD
576
`undef E_SRC_RD
577
`endif
578
`ifdef E_SRC_WR
579
`undef E_SRC_WR
580
`endif
581
`ifdef E_DST_AD
582
`undef E_DST_AD
583
`endif
584
`ifdef E_DST_RD
585
`undef E_DST_RD
586
`endif
587
`ifdef E_DST_WR
588
`undef E_DST_WR
589
`endif
590
`ifdef E_EXEC
591
`undef E_EXEC
592
`endif
593
`ifdef E_JUMP
594
`undef E_JUMP
595
`endif
596
`ifdef E_IDLE
597
`undef E_IDLE
598
`endif
599
 
600
// ALU control signals
601
`ifdef ALU_SRC_INV
602
`undef ALU_SRC_INV
603
`endif
604
`ifdef ALU_INC
605
`undef ALU_INC
606
`endif
607
`ifdef ALU_INC_C
608
`undef ALU_INC_C
609
`endif
610
`ifdef ALU_ADD
611
`undef ALU_ADD
612
`endif
613
`ifdef ALU_AND
614
`undef ALU_AND
615
`endif
616
`ifdef ALU_OR
617
`undef ALU_OR
618
`endif
619
`ifdef ALU_XOR
620
`undef ALU_XOR
621
`endif
622
`ifdef ALU_DADD
623
`undef ALU_DADD
624
`endif
625
`ifdef ALU_STAT_7
626
`undef ALU_STAT_7
627
`endif
628
`ifdef ALU_STAT_F
629
`undef ALU_STAT_F
630
`endif
631
`ifdef ALU_SHIFT
632
`undef ALU_SHIFT
633
`endif
634
`ifdef EXEC_NO_WR
635
`undef EXEC_NO_WR
636
`endif
637
 
638
// Debug interface
639
`ifdef DBG_UART_WR
640
`undef DBG_UART_WR
641
`endif
642
`ifdef DBG_UART_BW
643
`undef DBG_UART_BW
644
`endif
645
`ifdef DBG_UART_ADDR
646
`undef DBG_UART_ADDR
647
`endif
648
 
649
// Debug interface CPU_CTL register
650
`ifdef HALT
651
`undef HALT
652
`endif
653
`ifdef RUN
654
`undef RUN
655
`endif
656
`ifdef ISTEP
657
`undef ISTEP
658
`endif
659
`ifdef SW_BRK_EN
660
`undef SW_BRK_EN
661
`endif
662
`ifdef FRZ_BRK_EN
663
`undef FRZ_BRK_EN
664
`endif
665
`ifdef RST_BRK_EN
666
`undef RST_BRK_EN
667
`endif
668
`ifdef CPU_RST
669
`undef CPU_RST
670
`endif
671
 
672
// Debug interface CPU_STAT register
673
`ifdef HALT_RUN
674
`undef HALT_RUN
675
`endif
676
`ifdef PUC_PND
677
`undef PUC_PND
678
`endif
679
`ifdef SWBRK_PND
680
`undef SWBRK_PND
681
`endif
682
`ifdef HWBRK0_PND
683
`undef HWBRK0_PND
684
`endif
685
`ifdef HWBRK1_PND
686
`undef HWBRK1_PND
687
`endif
688
 
689
// Debug interface BRKx_CTL register
690
`ifdef BRK_MODE_RD
691
`undef BRK_MODE_RD
692
`endif
693
`ifdef BRK_MODE_WR
694
`undef BRK_MODE_WR
695
`endif
696
`ifdef BRK_MODE
697
`undef BRK_MODE
698
`endif
699
`ifdef BRK_EN
700
`undef BRK_EN
701
`endif
702
`ifdef BRK_I_EN
703
`undef BRK_I_EN
704
`endif
705
`ifdef BRK_RANGE
706
`undef BRK_RANGE
707
`endif
708
 
709
// Basic clock module: BCSCTL1 Control Register
710
`ifdef DIVAx
711
`undef DIVAx
712
`endif
713 202 olivier.gi
`ifdef DMA_CPUOFF
714
`undef DMA_CPUOFF
715
`endif
716
`ifdef DMA_SCG0
717
`undef DMA_SCG0
718
`endif
719
`ifdef DMA_SCG1
720
`undef DMA_SCG1
721
`endif
722
`ifdef DMA_OSCOFF
723
`undef DMA_OSCOFF
724
`endif
725 157 olivier.gi
 
726
// Basic clock module: BCSCTL2 Control Register
727
`ifdef SELMx
728
`undef SELMx
729
`endif
730
`ifdef DIVMx
731
`undef DIVMx
732
`endif
733
`ifdef SELS
734
`undef SELS
735
`endif
736
`ifdef DIVSx
737
`undef DIVSx
738
`endif
739
 
740
// MCLK Clock gate
741
`ifdef MCLK_CGATE
742
`undef MCLK_CGATE
743
`endif
744
 
745
// SMCLK Clock gate
746
`ifdef SMCLK_CGATE
747
`undef SMCLK_CGATE
748
`endif
749
 
750
//
751
// DEBUG INTERFACE EXTRA CONFIGURATION
752
//======================================
753
 
754
// Debug interface: CPU version
755
`ifdef CPU_VERSION
756
`undef CPU_VERSION
757
`endif
758
 
759
// Debug interface: Software breakpoint opcode
760
`ifdef DBG_SWBRK_OP
761
`undef DBG_SWBRK_OP
762
`endif
763
 
764
// Debug UART interface auto data synchronization
765
`ifdef DBG_UART_AUTO_SYNC
766
`undef DBG_UART_AUTO_SYNC
767
`endif
768
 
769
// Debug UART interface data rate
770
`ifdef DBG_UART_BAUD
771
`undef DBG_UART_BAUD
772
`endif
773
`ifdef DBG_DCO_FREQ
774
`undef DBG_DCO_FREQ
775
`endif
776
`ifdef DBG_UART_CNT
777
`undef DBG_UART_CNT
778
`endif
779
 
780
// Debug interface input synchronizer
781
`ifdef SYNC_DBG_UART_RXD
782
`undef SYNC_DBG_UART_RXD
783
`endif
784
 
785
// Enable/Disable the hardware breakpoint RANGE mode
786
`ifdef HWBRK_RANGE
787
`undef HWBRK_RANGE
788
`endif
789
 
790
// Counter width for the debug interface UART
791
`ifdef DBG_UART_XFER_CNT_W
792
`undef DBG_UART_XFER_CNT_W
793
`endif
794
 
795
//
796
// MULTIPLIER CONFIGURATION
797
//======================================
798
 
799
`ifdef MPY_16x16
800
`undef MPY_16x16
801
`endif

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