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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Blame information for rev 94

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//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
// 
// *File Name: tb_openMSP430_fpga.v
// 
// *Module Description:
//                      openMSP430 FPGA testbench
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 94 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-02-24 21:33:35 +0100 (Thu, 24 Feb 2011) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
 
module  tb_openMSP430_fpga;
 
//
// Wire & Register definition
//------------------------------
 
// Clock & Reset
reg               CLK_50MHz;
reg               RESET;
 
// Slide Switches
reg               SW7;
reg               SW6;
reg               SW5;
reg               SW4;
reg               SW3;
reg               SW2;
reg               SW1;
reg               SW0;
 
// Push Button Switches
reg               BTN2;
reg               BTN1;
reg               BTN0;
 
// LEDs
wire              LED7;
wire              LED6;
wire              LED5;
wire              LED4;
wire              LED3;
wire              LED2;
wire              LED1;
wire              LED0;
 
// Four-Sigit, Seven-Segment LED Display
wire              SEG_A;
wire              SEG_B;
wire              SEG_C;
wire              SEG_D;
wire              SEG_E;
wire              SEG_F;
wire              SEG_G;
wire              SEG_DP;
wire              SEG_AN0;
wire              SEG_AN1;
wire              SEG_AN2;
wire              SEG_AN3;
 
// UART
reg               UART_RXD;
wire              UART_TXD;
 
// Core debug signals
wire   [8*32-1:0] i_state;
wire   [8*32-1:0] e_state;
wire       [31:0] inst_cycle;
wire   [8*32-1:0] inst_full;
wire       [31:0] inst_number;
wire       [15:0] inst_pc;
wire   [8*32-1:0] inst_short;
 
// Testbench variables
integer           i;
integer           error;
reg               stimulus_done;
 
 
//
// Include files
//------------------------------
 
// CPU & Memory registers
`include "registers.v"
 
// Verilog stimulus
`include "stimulus.v"
 
//
// Initialize Program Memory
//------------------------------
 
initial
   begin
      // Read memory file
      #10 $readmemh("./pmem.mem", pmem);
 
      // Update Xilinx memory banks
      for (i=0; i<2048; i=i+1)
        begin
           dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];
           dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];
        end
  end
 
//
// Generate Clock & Reset
//------------------------------
initial
  begin
     CLK_50MHz = 1'b0;
     forever #10 CLK_50MHz <= ~CLK_50MHz; // 50 MHz
  end
 
initial
  begin
     RESET         = 1'b0;
     #100 RESET    = 1'b1;
     #600 RESET    = 1'b0;
  end
 
//
// Global initialization
//------------------------------
initial
  begin
     error         = 0;
     stimulus_done = 1;
     SW7           = 1'b0;  // Slide Switches
     SW6           = 1'b0;
     SW5           = 1'b0;
     SW4           = 1'b0;
     SW3           = 1'b0;
     SW2           = 1'b0;
     SW1           = 1'b0;
     SW0           = 1'b0;
     BTN2          = 1'b0;  // Push Button Switches
     BTN1          = 1'b0;
     BTN0          = 1'b0;
     UART_RXD      = 1'b0;  // UART
  end
 
//
// openMSP430 FPGA Instance
//----------------------------------
 
openMSP430_fpga dut (
 
// Clock Sources
    .CLK_50MHz    (CLK_50MHz),
    .CLK_SOCKET   (1'b0),
 
// Slide Switches
    .SW7          (SW7),
    .SW6          (SW6),
    .SW5          (SW5),
    .SW4          (SW4),
    .SW3          (SW3),
    .SW2          (SW2),
    .SW1          (SW1),
    .SW0          (SW0),
 
// Push Button Switches
    .BTN3         (RESET),
    .BTN2         (BTN2),
    .BTN1         (BTN1),
    .BTN0         (BTN0),
 
// LEDs
    .LED7         (LED7),
    .LED6         (LED6),
    .LED5         (LED5),
    .LED4         (LED4),
    .LED3         (LED3),
    .LED2         (LED2),
    .LED1         (LED1),
    .LED0         (LED0),
 
// Four-Sigit, Seven-Segment LED Display
    .SEG_A        (SEG_A),
    .SEG_B        (SEG_B),
    .SEG_C        (SEG_C),
    .SEG_D        (SEG_D),
    .SEG_E        (SEG_E),
    .SEG_F        (SEG_F),
    .SEG_G        (SEG_G),
    .SEG_DP       (SEG_DP),
    .SEG_AN0      (SEG_AN0),
    .SEG_AN1      (SEG_AN1),
    .SEG_AN2      (SEG_AN2),
    .SEG_AN3      (SEG_AN3),
 
// RS-232 Port
    .UART_RXD     (UART_RXD),
    .UART_TXD     (UART_TXD),
    .UART_RXD_A   (1'b0),
    .UART_TXD_A   (UART_TXD_A),
 
// PS/2 Mouse/Keyboard Port
    .PS2_D        (PS2_D),
    .PS2_C        (PS2_C),
 
// Fast, Asynchronous SRAM
    .SRAM_A17     (SRAM_A17),     // Address Bus Connections
    .SRAM_A16     (SRAM_A16),
    .SRAM_A15     (SRAM_A15),
    .SRAM_A14     (SRAM_A14),
    .SRAM_A13     (SRAM_A13),
    .SRAM_A12     (SRAM_A12),
    .SRAM_A11     (SRAM_A11),
    .SRAM_A10     (SRAM_A10),
    .SRAM_A9      (SRAM_A9),
    .SRAM_A8      (SRAM_A8),
    .SRAM_A7      (SRAM_A7),
    .SRAM_A6      (SRAM_A6),
    .SRAM_A5      (SRAM_A5),
    .SRAM_A4      (SRAM_A4),
    .SRAM_A3      (SRAM_A3),
    .SRAM_A2      (SRAM_A2),
    .SRAM_A1      (SRAM_A1),
    .SRAM_A0      (SRAM_A0),
    .SRAM_OE      (SRAM_OE),       // Write enable and output enable control signals
    .SRAM_WE      (SRAM_WE),
    .SRAM0_IO15   (SRAM0_IO15),    // SRAM Data signals, chip enables, and byte enables
    .SRAM0_IO14   (SRAM0_IO14),
    .SRAM0_IO13   (SRAM0_IO13),
    .SRAM0_IO12   (SRAM0_IO12),
    .SRAM0_IO11   (SRAM0_IO11),
    .SRAM0_IO10   (SRAM0_IO10),
    .SRAM0_IO9    (SRAM0_IO9),
    .SRAM0_IO8    (SRAM0_IO8),
    .SRAM0_IO7    (SRAM0_IO7),
    .SRAM0_IO6    (SRAM0_IO6),
    .SRAM0_IO5    (SRAM0_IO5),
    .SRAM0_IO4    (SRAM0_IO4),
    .SRAM0_IO3    (SRAM0_IO3),
    .SRAM0_IO2    (SRAM0_IO2),
    .SRAM0_IO1    (SRAM0_IO1),
    .SRAM0_IO0    (SRAM0_IO0),
    .SRAM0_CE1    (SRAM0_CE1),
    .SRAM0_UB1    (SRAM0_UB1),
    .SRAM0_LB1    (SRAM0_LB1),
    .SRAM1_IO15   (SRAM1_IO15),
    .SRAM1_IO14   (SRAM1_IO14),
    .SRAM1_IO13   (SRAM1_IO13),
    .SRAM1_IO12   (SRAM1_IO12),
    .SRAM1_IO11   (SRAM1_IO11),
    .SRAM1_IO10   (SRAM1_IO10),
    .SRAM1_IO9    (SRAM1_IO9),
    .SRAM1_IO8    (SRAM1_IO8),
    .SRAM1_IO7    (SRAM1_IO7),
    .SRAM1_IO6    (SRAM1_IO6),
    .SRAM1_IO5    (SRAM1_IO5),
    .SRAM1_IO4    (SRAM1_IO4),
    .SRAM1_IO3    (SRAM1_IO3),
    .SRAM1_IO2    (SRAM1_IO2),
    .SRAM1_IO1    (SRAM1_IO1),
    .SRAM1_IO0    (SRAM1_IO0),
    .SRAM1_CE2    (SRAM1_CE2),
    .SRAM1_UB2    (SRAM1_UB2),
    .SRAM1_LB2    (SRAM1_LB2),
 
// VGA Port
    .VGA_R        (VGA_R),
    .VGA_G        (VGA_G),
    .VGA_B        (VGA_B),
    .VGA_HS       (VGA_HS),
    .VGA_VS       (VGA_VS)
);
 
 
//
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_0 (
 
// OUTPUTs
    .e_state      (e_state),       // Execution state
    .i_state      (i_state),       // Instruction fetch state
    .inst_cycle   (inst_cycle),    // Cycle number within current instruction
    .inst_full    (inst_full),     // Currently executed instruction (full version)
    .inst_number  (inst_number),   // Instruction number since last system reset
    .inst_pc      (inst_pc),       // Instruction Program counter
    .inst_short   (inst_short),    // Currently executed instruction (short version)
 
// INPUTs
    .mclk         (mclk),          // Main system clock
    .puc          (puc)            // Main system reset
);
 
//
// Generate Waveform
//----------------------------------------
initial
  begin
   `ifdef VPD_FILE
     $vcdplusfile("tb_openMSP430_fpga.vpd");
     $vcdpluson();
   `else
     $dumpfile("tb_openMSP430_fpga.vcd");
     $dumpvars(0, tb_openMSP430_fpga);
   `endif
  end
 
//
// End of simulation
//----------------------------------------
 
initial // Timeout
  begin
     #500000;
     $display(" ===============================================");
     $display("|               SIMULATION FAILED               |");
     $display("|              (simulation Timeout)             |");
     $display(" ===============================================");
     $finish;
  end
 
initial // Normal end of test
  begin
     @(inst_pc===16'hffff)
     $display(" ===============================================");
     if (error!=0)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (some verilog stimulus checks failed)     |");
       end
     else if (~stimulus_done)
       begin
          $display("|               SIMULATION FAILED               |");
          $display("|     (the verilog stimulus didn't complete)    |");
       end
     else
       begin
          $display("|               SIMULATION PASSED               |");
       end
     $display(" ===============================================");
     $finish;
  end
 
 
//
// Tasks Definition
//------------------------------
 
   task tb_error;
      input [65*8:0] error_string;
      begin
         $display("ERROR: %s %t", error_string, $time);
         error = error+1;
      end
   endtask
 
 
endmodule

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Blame information for rev 94

Line No.	Rev	Author	Line
1	2	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2001 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: tb_openMSP430_fpga.v`
26			`//`
27			`// *Module Description:`
28			`// openMSP430 FPGA testbench`
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34	16	olivier.gi	`// $Rev: 94 $`
35			`// $LastChangedBy: olivier.girard $`
36			`// $LastChangedDate: 2011-02-24 21:33:35 +0100 (Thu, 24 Feb 2011) $`
37			`//----------------------------------------------------------------------------`
38	23	olivier.gi	`include "timescale.v"
39			`include "openMSP430_defines.v"
40	2	olivier.gi
41			`module tb_openMSP430_fpga;`
42
43			`//`
44			`// Wire & Register definition`
45			`//------------------------------`
46
47			`// Clock & Reset`
48			`reg CLK_50MHz;`
49			`reg RESET;`
50
51			`// Slide Switches`
52			`reg SW7;`
53			`reg SW6;`
54			`reg SW5;`
55			`reg SW4;`
56			`reg SW3;`
57			`reg SW2;`
58			`reg SW1;`
59			`reg SW0;`
60
61			`// Push Button Switches`
62			`reg BTN2;`
63			`reg BTN1;`
64			`reg BTN0;`
65
66			`// LEDs`
67			`wire LED7;`
68			`wire LED6;`
69			`wire LED5;`
70			`wire LED4;`
71			`wire LED3;`
72			`wire LED2;`
73			`wire LED1;`
74			`wire LED0;`
75
76			`// Four-Sigit, Seven-Segment LED Display`
77			`wire SEG_A;`
78			`wire SEG_B;`
79			`wire SEG_C;`
80			`wire SEG_D;`
81			`wire SEG_E;`
82			`wire SEG_F;`
83			`wire SEG_G;`
84			`wire SEG_DP;`
85			`wire SEG_AN0;`
86			`wire SEG_AN1;`
87			`wire SEG_AN2;`
88			`wire SEG_AN3;`
89
90			`// UART`
91			`reg UART_RXD;`
92			`wire UART_TXD;`
93
94			`// Core debug signals`
95			`wire [8*32-1:0] i_state;`
96			`wire [8*32-1:0] e_state;`
97			`wire [31:0] inst_cycle;`
98			`wire [8*32-1:0] inst_full;`
99			`wire [31:0] inst_number;`
100			`wire [15:0] inst_pc;`
101			`wire [8*32-1:0] inst_short;`
102
103			`// Testbench variables`
104			`integer i;`
105			`integer error;`
106			`reg stimulus_done;`
107
108
109			`//`
110			`// Include files`
111			`//------------------------------`
112
113			`// CPU & Memory registers`
114			`include "registers.v"
115
116			`// Verilog stimulus`
117			`include "stimulus.v"
118
119			`//`
120	37	olivier.gi	`// Initialize Program Memory`
121	2	olivier.gi	`//------------------------------`
122
123			`initial`
124			`begin`
125			`// Read memory file`
126	94	olivier.gi	`#10 $readmemh("./pmem.mem", pmem);`
127	2	olivier.gi
128			`// Update Xilinx memory banks`
129			`for (i=0; i<2048; i=i+1)`
130			`begin`
131	37	olivier.gi	`dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];`
132			`dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];`
133	2	olivier.gi	`end`
134			`end`
135
136			`//`
137			`// Generate Clock & Reset`
138			`//------------------------------`
139			`initial`
140			`begin`
141			`CLK_50MHz = 1'b0;`
142			`forever #10 CLK_50MHz <= ~CLK_50MHz; // 50 MHz`
143			`end`
144
145			`initial`
146			`begin`
147			`RESET = 1'b0;`
148			`#100 RESET = 1'b1;`
149			`#600 RESET = 1'b0;`
150			`end`
151
152			`//`
153			`// Global initialization`
154			`//------------------------------`
155			`initial`
156			`begin`
157			`error = 0;`
158			`stimulus_done = 1;`
159			`SW7 = 1'b0; // Slide Switches`
160			`SW6 = 1'b0;`
161			`SW5 = 1'b0;`
162			`SW4 = 1'b0;`
163			`SW3 = 1'b0;`
164			`SW2 = 1'b0;`
165			`SW1 = 1'b0;`
166			`SW0 = 1'b0;`
167			`BTN2 = 1'b0; // Push Button Switches`
168			`BTN1 = 1'b0;`
169			`BTN0 = 1'b0;`
170			`UART_RXD = 1'b0; // UART`
171			`end`
172
173			`//`
174			`// openMSP430 FPGA Instance`
175			`//----------------------------------`
176
177			`openMSP430_fpga dut (`
178
179			`// Clock Sources`
180			`.CLK_50MHz (CLK_50MHz),`
181			`.CLK_SOCKET (1'b0),`
182
183			`// Slide Switches`
184			`.SW7 (SW7),`
185			`.SW6 (SW6),`
186			`.SW5 (SW5),`
187			`.SW4 (SW4),`
188			`.SW3 (SW3),`
189			`.SW2 (SW2),`
190			`.SW1 (SW1),`
191			`.SW0 (SW0),`
192
193			`// Push Button Switches`
194			`.BTN3 (RESET),`
195			`.BTN2 (BTN2),`
196			`.BTN1 (BTN1),`
197			`.BTN0 (BTN0),`
198
199			`// LEDs`
200			`.LED7 (LED7),`
201			`.LED6 (LED6),`
202			`.LED5 (LED5),`
203			`.LED4 (LED4),`
204			`.LED3 (LED3),`
205			`.LED2 (LED2),`
206			`.LED1 (LED1),`
207			`.LED0 (LED0),`
208
209			`// Four-Sigit, Seven-Segment LED Display`
210			`.SEG_A (SEG_A),`
211			`.SEG_B (SEG_B),`
212			`.SEG_C (SEG_C),`
213			`.SEG_D (SEG_D),`
214			`.SEG_E (SEG_E),`
215			`.SEG_F (SEG_F),`
216			`.SEG_G (SEG_G),`
217			`.SEG_DP (SEG_DP),`
218			`.SEG_AN0 (SEG_AN0),`
219			`.SEG_AN1 (SEG_AN1),`
220			`.SEG_AN2 (SEG_AN2),`
221			`.SEG_AN3 (SEG_AN3),`
222
223			`// RS-232 Port`
224			`.UART_RXD (UART_RXD),`
225			`.UART_TXD (UART_TXD),`
226			`.UART_RXD_A (1'b0),`
227			`.UART_TXD_A (UART_TXD_A),`
228
229			`// PS/2 Mouse/Keyboard Port`
230			`.PS2_D (PS2_D),`
231			`.PS2_C (PS2_C),`
232
233			`// Fast, Asynchronous SRAM`
234			`.SRAM_A17 (SRAM_A17), // Address Bus Connections`
235			`.SRAM_A16 (SRAM_A16),`
236			`.SRAM_A15 (SRAM_A15),`
237			`.SRAM_A14 (SRAM_A14),`
238			`.SRAM_A13 (SRAM_A13),`
239			`.SRAM_A12 (SRAM_A12),`
240			`.SRAM_A11 (SRAM_A11),`
241			`.SRAM_A10 (SRAM_A10),`
242			`.SRAM_A9 (SRAM_A9),`
243			`.SRAM_A8 (SRAM_A8),`
244			`.SRAM_A7 (SRAM_A7),`
245			`.SRAM_A6 (SRAM_A6),`
246			`.SRAM_A5 (SRAM_A5),`
247			`.SRAM_A4 (SRAM_A4),`
248			`.SRAM_A3 (SRAM_A3),`
249			`.SRAM_A2 (SRAM_A2),`
250			`.SRAM_A1 (SRAM_A1),`
251			`.SRAM_A0 (SRAM_A0),`
252			`.SRAM_OE (SRAM_OE), // Write enable and output enable control signals`
253			`.SRAM_WE (SRAM_WE),`
254			`.SRAM0_IO15 (SRAM0_IO15), // SRAM Data signals, chip enables, and byte enables`
255			`.SRAM0_IO14 (SRAM0_IO14),`
256			`.SRAM0_IO13 (SRAM0_IO13),`
257			`.SRAM0_IO12 (SRAM0_IO12),`
258			`.SRAM0_IO11 (SRAM0_IO11),`
259			`.SRAM0_IO10 (SRAM0_IO10),`
260			`.SRAM0_IO9 (SRAM0_IO9),`
261			`.SRAM0_IO8 (SRAM0_IO8),`
262			`.SRAM0_IO7 (SRAM0_IO7),`
263			`.SRAM0_IO6 (SRAM0_IO6),`
264			`.SRAM0_IO5 (SRAM0_IO5),`
265			`.SRAM0_IO4 (SRAM0_IO4),`
266			`.SRAM0_IO3 (SRAM0_IO3),`
267			`.SRAM0_IO2 (SRAM0_IO2),`
268			`.SRAM0_IO1 (SRAM0_IO1),`
269			`.SRAM0_IO0 (SRAM0_IO0),`
270			`.SRAM0_CE1 (SRAM0_CE1),`
271			`.SRAM0_UB1 (SRAM0_UB1),`
272			`.SRAM0_LB1 (SRAM0_LB1),`
273			`.SRAM1_IO15 (SRAM1_IO15),`
274			`.SRAM1_IO14 (SRAM1_IO14),`
275			`.SRAM1_IO13 (SRAM1_IO13),`
276			`.SRAM1_IO12 (SRAM1_IO12),`
277			`.SRAM1_IO11 (SRAM1_IO11),`
278			`.SRAM1_IO10 (SRAM1_IO10),`
279			`.SRAM1_IO9 (SRAM1_IO9),`
280			`.SRAM1_IO8 (SRAM1_IO8),`
281			`.SRAM1_IO7 (SRAM1_IO7),`
282			`.SRAM1_IO6 (SRAM1_IO6),`
283			`.SRAM1_IO5 (SRAM1_IO5),`
284			`.SRAM1_IO4 (SRAM1_IO4),`
285			`.SRAM1_IO3 (SRAM1_IO3),`
286			`.SRAM1_IO2 (SRAM1_IO2),`
287			`.SRAM1_IO1 (SRAM1_IO1),`
288			`.SRAM1_IO0 (SRAM1_IO0),`
289			`.SRAM1_CE2 (SRAM1_CE2),`
290			`.SRAM1_UB2 (SRAM1_UB2),`
291			`.SRAM1_LB2 (SRAM1_LB2),`
292
293			`// VGA Port`
294			`.VGA_R (VGA_R),`
295			`.VGA_G (VGA_G),`
296			`.VGA_B (VGA_B),`
297			`.VGA_HS (VGA_HS),`
298			`.VGA_VS (VGA_VS)`
299			`);`
300
301
302			`//`
303			`// Debug utility signals`
304			`//----------------------------------------`
305			`msp_debug msp_debug_0 (`
306
307			`// OUTPUTs`
308			`.e_state (e_state), // Execution state`
309			`.i_state (i_state), // Instruction fetch state`
310			`.inst_cycle (inst_cycle), // Cycle number within current instruction`
311			`.inst_full (inst_full), // Currently executed instruction (full version)`
312			`.inst_number (inst_number), // Instruction number since last system reset`
313			`.inst_pc (inst_pc), // Instruction Program counter`
314			`.inst_short (inst_short), // Currently executed instruction (short version)`
315
316			`// INPUTs`
317			`.mclk (mclk), // Main system clock`
318			`.puc (puc) // Main system reset`
319			`);`
320
321			`//`
322			`// Generate Waveform`
323			`//----------------------------------------`
324			`initial`
325			`begin`
326			`ifdef VPD_FILE
327			`$vcdplusfile("tb_openMSP430_fpga.vpd");`
328			`$vcdpluson();`
329			`else
330			`$dumpfile("tb_openMSP430_fpga.vcd");`
331			`$dumpvars(0, tb_openMSP430_fpga);`
332			`endif
333			`end`
334
335			`//`
336			`// End of simulation`
337			`//----------------------------------------`
338
339			`initial // Timeout`
340			`begin`
341			`#500000;`
342			`$display(" ===============================================");`
343			`$display("\| SIMULATION FAILED \|");`
344			`$display("\| (simulation Timeout) \|");`
345			`$display(" ===============================================");`
346			`$finish;`
347			`end`
348
349			`initial // Normal end of test`
350			`begin`
351			`@(inst_pc===16'hffff)`
352			`$display(" ===============================================");`
353			`if (error!=0)`
354			`begin`
355			`$display("\| SIMULATION FAILED \|");`
356			`$display("\| (some verilog stimulus checks failed) \|");`
357			`end`
358			`else if (~stimulus_done)`
359			`begin`
360			`$display("\| SIMULATION FAILED \|");`
361			`$display("\| (the verilog stimulus didn't complete) \|");`
362			`end`
363			`else`
364			`begin`
365			`$display("\| SIMULATION PASSED \|");`
366			`end`
367			`$display(" ===============================================");`
368			`$finish;`
369			`end`
370
371
372			`//`
373			`// Tasks Definition`
374			`//------------------------------`
375
376			`task tb_error;`
377			`input [65*8:0] error_string;`
378			`begin`
379			`$display("ERROR: %s %t", error_string, $time);`
380			`error = error+1;`
381			`end`
382			`endtask`
383
384
385			`endmodule`