OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [ram.ld] - Blame information for rev 375

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 140 julius
 
2 246 julius
 
3 2 marcus.erl
MEMORY
4
        {
5
        vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
6 375 julius
        /* Use all RAM */
7
        /* Put all sections into ram */
8
        /*
9 246 julius
        ram     : ORIGIN = 0x00002000, LENGTH = 0x02000000 - 0x00002000
10 375 julius
        */
11
        /* Uncomment the following to work around bad pages in a flash mem */
12
        /* Put all sections except data, rodata into ram2 */
13
        /* On ORSoC dev board devices, for pages 132-134 (256Byte pages) */
14
        ram     : ORIGIN = 0x00001200, LENGTH = 0x8400 - 0x1200
15
        ram2     : ORIGIN = 0x8700, LENGTH = 0x02000000 - 0x8700
16 246 julius
 
17
        /* Uncomment the following to work around bad pages in a flash mem */
18 375 julius
        /* Put all sections except data, rodata into ram2 */
19
        /* On ORSoC dev board devices, for pages 180-182 (256Byte pages) */
20 246 julius
        /*
21 140 julius
        ram     : ORIGIN = 0x00001200, LENGTH = 0xB400 - 0x1200
22
        ram2     : ORIGIN = 0xb700, LENGTH = 0x02000000 - 0xb700
23 246 julius
        */
24 140 julius
        /*flash   : ORIGIN = 0xf0000000, LENGTH = 0x04000000*/
25 2 marcus.erl
        }
26
 
27 140 julius
 
28
 
29 2 marcus.erl
SECTIONS
30
{
31
        .vectors :
32
        {
33
        *(.crc)
34
        *(.vectors)
35
        } > vectors
36
 
37
        .text :
38
        {
39
        _text_begin = .;
40
        *(.text)
41
        _text_end = .;
42 375 julius
        } > ram2
43 2 marcus.erl
 
44
        .data :
45 140 julius
/*      AT ( ADDR (.text) + SIZEOF(.text) + SIZEOF(.mytext))*/
46 2 marcus.erl
        {
47
        *(.data)
48
        } > ram
49
 
50
        .rodata :
51
        {
52
        *(.rodata)
53
        *(.rodata.*)
54
        } > ram
55
 
56
        .bss :
57
        {
58
        *(.bss)
59 375 julius
        } > ram2
60 2 marcus.erl
 
61
        .stack :
62
        {
63
        *(.stack)
64 353 julius
        _src_addr = .;
65 375 julius
        } > ram2
66 140 julius
/*
67
        .monitor :
68
        {
69
        *(.monitor)
70
        } > ram
71
*/
72 2 marcus.erl
 
73 140 julius
/*
74
        . += 0x100000;
75
 
76
// This section was in cmds/load.c, but we don't need it -jb
77
        .config :
78
        {
79
        _cfg_start = .;
80
        *(.config)
81
        _cfg_end = .;
82
        } > ram
83
*/
84
/*
85 2 marcus.erl
        . = 0xf0000100;
86
 
87
        .monitor ALIGN(0x40000) :
88
        {
89
        *(.monitor)
90
        } > flash
91
 
92
        . += 0x100000;
93
 
94
        .config ALIGN(0x40000) :
95
        {
96
        _cfg_start = .;
97
        *(.config)
98
        _cfg_end = .;
99
        } > flash
100 140 julius
*/
101 2 marcus.erl
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.