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#include "spr-defs.h"
#include "board.h"
#include "mc.h"
 
        .extern _src_beg
        .extern _dst_beg
        .extern _dst_end
        .extern int_main
        .extern int_error
        .extern tick_interrupt
        .extern _crc32
 
        .global _align
        .global _calc_mycrc32
        .global _mycrc32
        .global _mysize
 
        .section .stack, "aw", @nobits
.space  STACK_SIZE
_stack:
        .section .crc
_mycrc32:
        .word   0xcccccccc
_mysize:
        .word 0xdddddddd
 
.if SELF_CHECK
_calc_mycrc32:
        l.addi  r3,r0,0
        l.movhi r4,hi(_calc_mycrc32)
        l.ori   r4,r4,lo(_calc_mycrc32)
        l.movhi r5,hi(_mysize)
        l.ori   r5,r5,lo(_mysize)
        l.lwz   r5,0(r5)
        l.addi  r1,r1,-4
        l.sw    0(r1),r9
 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
        l.jal           _crc32
        l.nop
 
        l.movhi r3,hi(_mycrc32)
        l.ori   r3,r3,lo(_mycrc32)
        l.lwz   r3,0(r3)
 
        l.xor     r11,r3,r11
        l.lwz   r9,0(r1)
        l.jr    r9
        l.addi  r1,r1,4
.endif
 
        .org 0x100
 
.if IN_FLASH
        .section .reset, "ax"
.else
        .section .vectors, "ax"
.endif
 
_reset:
.if IN_FLASH
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,MC_BA_MASK
        l.addi  r5,r0,0x00
        l.sw    0(r3),r5
.endif
        l.movhi r0, 0
        /* Clear status register, set supervisor mode */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Jump to start routine */
        l.movhi r3,hi(_start)
        l.ori   r3,r3,lo(_start)
        l.jr    r3
        l.nop
 
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x200
.else
        .org (0x200 - 0x100 + _reset)
.endif
_buserr:
.if 0
        /* Just trap */
        l.trap 0
.endif
.if 0
        l.nop 0x1
        l.j 0
        l.nop
.endif
        l.j _int_error
        l.ori r3, r0, 0x2
 
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x500
.else
        .org (0x500 - 0x100 + _reset)
.endif
_tickint:
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
        /* Simply load timer_ticks variable and increment */
        .extern _timer_ticks
        l.addi  r1, r1, -8
        l.sw    0(r1), r25
        l.sw    4(r1), r26
        l.movhi r25, hi(timestamp)
        l.ori   r25, r25, lo(timestamp)
        l.lwz   r26, 0(r25)                     /* Load variable addr.*/
        l.addi  r26, r26, 1                     /* Increment variable */
        l.sw    0(r25), r26                     /* Store variable */
        l.movhi r25, hi(TIMER_RELOAD_VALUE)     /* Load timer value */
        l.ori   r25, r25, lo(TIMER_RELOAD_VALUE)
        l.mtspr r0, r25, SPR_TTMR               /* Reset timer */
        l.lwz   r25, 0(r1)
        l.lwz   r26, 4(r1)
        l.addi  r1, r1, 8
        l.rfe
 
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x600
.else
        .org (0x600 - 0x100 + _reset)
.endif
_alignerr:
.if 0
        l.trap 0
.endif
.if 0
        l.nop 0x1
        l.j 0
        l.nop
.endif
        l.j _int_error
        l.ori r3, r0, 0x6
 
.if IN_FLASH
        .org 0x700
.else
        .org (0x700 - 0x100 + _reset)
.endif
_illinsn:
.if 0
        /* Just trap */
        l.trap 0
.endif
.if 0
        l.nop 0x1
        l.j 0
        l.nop
.endif
        l.j _int_error
        l.ori r3, r0, 0x7
 
.if IN_FLASH
        .org 0x800
.else
        .org (0x800 - 0x100 + _reset)
.endif
_userint:
        l.addi  r1,r1,-128
        l.sw    0x0(r1),r2
        l.addi  r2, r1, 128
        l.sw    0x4(r1), r3
        l.movhi r3,hi(_int_wrapper)
        l.ori   r3,r3,lo(_int_wrapper)
        l.jr    r3
        l.nop
 
        .section .text
_start:
.if IN_FLASH
/*        l.jal   _init_mc
        l.nop
*/
        /* Wait for SDRAM */
        l.addi  r3,r0,0x1000
1:      l.sfeqi r3,0
        l.bnf   1b
        l.addi  r3,r3,-1
.endif
        /* Copy form flash to sram */
.if IN_FLASH
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_vec_start)
        l.ori   r4,r4,lo(_vec_start)
        l.movhi r5,hi(_vec_end)
        l.ori   r5,r5,lo(_vec_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
2:
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
1:      l.sfgeu r4,r5
        l.bf    1f
        l.nop
        l.lwz   r8,0(r3)
        l.sw    0(r4),r8
        l.addi  r3,r3,4
        l.bnf   1b
        l.addi  r4,r4,4
1:
        l.addi  r3,r0,0
        l.addi  r4,r0,0
3:
.endif
 
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
 
.L10:
        /* Set up stack */
        l.movhi r1,hi(_stack-4)
        l.ori   r1,r1,lo(_stack-4)
        l.addi  r2,r0,-3
        l.and   r1,r1,r2
/*      l.or    r2, r1, r1 - remove this helped with odd UART output problem?!*/
 
        l.movhi r3,hi(main)
        l.ori   r3,r3,lo(main)
        l.jr    r3
        l.nop
 
_int_wrapper:
 
        l.sw    0x8(r1), r4
        l.sw    0xc(r1), r5
        l.sw    0x10(r1), r6
        l.sw    0x14(r1), r7
        l.sw    0x18(r1), r8
        l.sw    0x1c(r1), r9
        l.sw    0x20(r1), r10
        l.sw    0x24(r1), r11
        l.sw    0x28(r1), r12
        l.sw    0x2c(r1), r13
        l.sw    0x30(r1), r14
        l.sw    0x34(r1), r15
        l.sw    0x38(r1), r16
        l.sw    0x3c(r1), r17
        l.sw    0x40(r1), r18
        l.sw    0x44(r1), r19
        l.sw    0x48(r1), r20
        l.sw    0x4c(r1), r21
        l.sw    0x50(r1), r22
        l.sw    0x54(r1), r23
        l.sw    0x58(r1), r24
        l.sw    0x5c(r1), r25
        l.sw    0x60(r1), r26
        l.sw    0x64(r1), r27
        l.sw    0x68(r1), r28
        l.sw    0x6c(r1), r29
        l.sw    0x70(r1), r30
        l.sw    0x74(r1), r31
 
        l.movhi r3,hi(int_main)
        l.ori   r3,r3,lo(int_main)
        l.jalr  r3
        l.nop
 
        l.lwz   r3,0x4(r1)
        l.lwz   r4,0x8(r1)
        l.lwz   r5,0xc(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
 
        l.lwz   r2, 0x0(r1)
        l.addi  r1,r1,128
        l.rfe
        l.nop
 
 
_align:
        l.sw    0x0c(r1),r3
        l.sw    0x10(r1),r4
        l.sw    0x14(r1),r5
        l.sw    0x18(r1),r6
        l.sw    0x1c(r1),r7
        l.sw    0x20(r1),r8
        l.sw    0x24(r1),r9
        l.sw    0x28(r1),r10
        l.sw    0x2c(r1),r11
        l.sw    0x30(r1),r12
        l.sw    0x34(r1),r13
        l.sw    0x38(r1),r14
        l.sw    0x3c(r1),r15
        l.sw    0x40(r1),r16
        l.sw    0x44(r1),r17
        l.sw    0x48(r1),r18
        l.sw    0x4c(r1),r19
        l.sw    0x50(r1),r20
        l.sw    0x54(r1),r21
        l.sw    0x58(r1),r22
        l.sw    0x5c(r1),r23
        l.sw    0x60(r1),r24
        l.sw    0x64(r1),r25
        l.sw    0x68(r1),r26
        l.sw    0x6c(r1),r27
        l.sw    0x70(r1),r28
        l.sw    0x74(r1),r29
        l.sw    0x78(r1),r30
        l.sw    0x7c(r1),r31
 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
 
        l.lwz   r3,0(r5)    /* Load insn */
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
        l.bf    jmp
        l.sfeqi r4,0x01
        l.bf    jmp
        l.sfeqi r4,0x03
        l.bf    jmp
        l.sfeqi r4,0x04
        l.bf    jmp
        l.sfeqi r4,0x11
        l.bf    jr
        l.sfeqi r4,0x12
        l.bf    jr
        l.nop
        l.j     1f
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
 
jmp:
        l.slli  r4,r3,6     /* Get the signed extended jump length */
        l.srai  r4,r4,4
 
        l.lwz   r3,4(r5)      /* Load the real load/store insn */
 
        l.add   r5,r5,r4      /* Calculate jump target address */
 
        l.j     1f
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
jr:
        l.slli  r4,r3,9     /* Shift to get the reg nb */
        l.andi  r4,r4,0x7c
 
        l.lwz   r3,4(r5)    /* Load the real load/store insn */
 
        l.add   r4,r4,r1    /* Load the jump register value from the stack */
        l.lwz   r5,0(r4)
 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
 
        l.sfeqi r4,0x26
        l.bf    lhs
        l.sfeqi r4,0x25
        l.bf    lhz
        l.sfeqi r4,0x22
        l.bf    lws
        l.sfeqi r4,0x21
        l.bf    lwz
        l.sfeqi r4,0x37
        l.bf    sh
        l.sfeqi r4,0x35
        l.bf    sw
        l.nop
 
1:      l.j     1b      /* I don't know what to do */
        l.nop
 
lhs:    l.lbs   r5,0(r2)
        l.slli  r5,r5,8
        l.lbz   r6,1(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
lhz:    l.lbz   r5,0(r2)
        l.slli  r5,r5,8
        l.lbz   r6,1(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
lws:    l.lbs   r5,0(r2)
        l.slli  r5,r5,24
        l.lbz   r6,1(r2)
        l.slli  r6,r6,16
        l.or    r5,r5,r6
        l.lbz   r6,2(r2)
        l.slli  r6,r6,8
        l.or    r5,r5,r6
        l.lbz   r6,3(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
lwz:    l.lbz   r5,0(r2)
        l.slli  r5,r5,24
        l.lbz   r6,1(r2)
        l.slli  r6,r6,16
        l.or    r5,r5,r6
        l.lbz   r6,2(r2)
        l.slli  r6,r6,8
        l.or    r5,r5,r6
        l.lbz   r6,3(r2)
        l.or    r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.j     align_end
        l.sw    0(r4),r5
 
sh:
        l.srli  r4,r3,9
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.lwz   r5,0(r4)
        l.sb    1(r2),r5
        l.srli  r5,r5,8
        l.j     align_end
        l.sb    0(r2),r5
 
sw:
        l.srli  r4,r3,9
        l.andi  r4,r4,0x7c
        l.add   r4,r4,r1
        l.lwz   r5,0(r4)
        l.sb    3(r2),r5
        l.srli  r5,r5,8
        l.sb    2(r2),r5
        l.srli  r5,r5,8
        l.sb    1(r2),r5
        l.srli  r5,r5,8
        l.j     align_end
        l.sb    0(r2),r5
 
align_end:
        l.lwz   r2,0x08(r1)
        l.lwz   r3,0x0c(r1)
        l.lwz   r4,0x10(r1)
        l.lwz   r5,0x14(r1)
        l.lwz   r6,0x18(r1)
        l.lwz   r7,0x1c(r1)
        l.lwz   r8,0x20(r1)
        l.lwz   r9,0x24(r1)
        l.lwz   r10,0x28(r1)
        l.lwz   r11,0x2c(r1)
        l.lwz   r12,0x30(r1)
        l.lwz   r13,0x34(r1)
        l.lwz   r14,0x38(r1)
        l.lwz   r15,0x3c(r1)
        l.lwz   r16,0x40(r1)
        l.lwz   r17,0x44(r1)
        l.lwz   r18,0x48(r1)
        l.lwz   r19,0x4c(r1)
        l.lwz   r20,0x50(r1)
        l.lwz   r21,0x54(r1)
        l.lwz   r22,0x58(r1)
        l.lwz   r23,0x5c(r1)
        l.lwz   r24,0x60(r1)
        l.lwz   r25,0x64(r1)
        l.lwz   r26,0x68(r1)
        l.lwz   r27,0x6c(r1)
        l.lwz   r28,0x70(r1)
        l.lwz   r29,0x74(r1)
        l.lwz   r30,0x78(r1)
        l.mfspr r31,r0,0x40
        l.lwz   r31,0x7c(r1)
        l.addi  r1,r1,128
        l.rfe
 
 
        /* Jump to error function. Clobber r2 */
_int_error:
        l.movhi r2,hi(int_error)
        l.ori   r2,r2,lo(int_error)
        l.jr  r2
        l.nop

Line No.	Rev	Author	Line
1	246	julius	`#include "spr-defs.h"`
2	2	marcus.erl	`#include "board.h"`
3			`#include "mc.h"`
4
5			`.extern _src_beg`
6			`.extern _dst_beg`
7			`.extern _dst_end`
8	375	julius	`.extern int_main`
9	406	julius	`.extern int_error`
10	375	julius	`.extern tick_interrupt`
11	2	marcus.erl	`.extern _crc32`
12
13			`.global _align`
14			`.global _calc_mycrc32`
15			`.global _mycrc32`
16			`.global _mysize`
17
18			`.section .stack, "aw", @nobits`
19			`.space STACK_SIZE`
20			`_stack:`
21			`.section .crc`
22			`_mycrc32:`
23			`.word 0xcccccccc`
24			`_mysize:`
25			`.word 0xdddddddd`
26
27			`.if SELF_CHECK`
28			`_calc_mycrc32:`
29			`l.addi r3,r0,0`
30			`l.movhi r4,hi(_calc_mycrc32)`
31			`l.ori r4,r4,lo(_calc_mycrc32)`
32			`l.movhi r5,hi(_mysize)`
33			`l.ori r5,r5,lo(_mysize)`
34			`l.lwz r5,0(r5)`
35			`l.addi r1,r1,-4`
36			`l.sw 0(r1),r9`
37
38			`/* unsigned long crc32 (unsigned long crc, const unsigned char buf, unsigned long len); /`
39			`l.jal _crc32`
40			`l.nop`
41
42			`l.movhi r3,hi(_mycrc32)`
43			`l.ori r3,r3,lo(_mycrc32)`
44			`l.lwz r3,0(r3)`
45
46			`l.xor r11,r3,r11`
47			`l.lwz r9,0(r1)`
48			`l.jr r9`
49			`l.addi r1,r1,4`
50			`.endif`
51
52			`.org 0x100`
53	140	julius
54	2	marcus.erl	`.if IN_FLASH`
55			`.section .reset, "ax"`
56			`.else`
57			`.section .vectors, "ax"`
58			`.endif`
59
60			`_reset:`
61			`.if IN_FLASH`
62			`l.movhi r3,hi(MC_BASE_ADDR)`
63			`l.ori r3,r3,MC_BA_MASK`
64			`l.addi r5,r0,0x00`
65			`l.sw 0(r3),r5`
66			`.endif`
67	246	julius	`l.movhi r0, 0`
68			`/* Clear status register, set supervisor mode */`
69			`l.ori r1, r0, SPR_SR_SM`
70			`l.mtspr r0, r1, SPR_SR`
71			`/* Clear timer */`
72			`l.mtspr r0, r0, SPR_TTMR`
73			`/* Jump to start routine */`
74	2	marcus.erl	`l.movhi r3,hi(_start)`
75			`l.ori r3,r3,lo(_start)`
76			`l.jr r3`
77			`l.nop`
78
79			`.if IN_FLASH`
80			`.section .vectors, "ax"`
81	140	julius	`.org 0x200`
82			`.else`
83			`.org (0x200 - 0x100 + _reset)`
84			`.endif`
85			`_buserr:`
86	246	julius	`.if 0`
87			`/* Just trap */`
88	140	julius	`l.trap 0`
89	246	julius	`.endif`
90	406	julius	`.if 0`
91	246	julius	`l.nop 0x1`
92	140	julius	`l.j 0`
93			`l.nop`
94	406	julius	`.endif`
95			`l.j _int_error`
96			`l.ori r3, r0, 0x2`
97	140	julius
98			`.if IN_FLASH`
99			`.section .vectors, "ax"`
100	2	marcus.erl	`.org 0x500`
101			`.else`
102			`.org (0x500 - 0x100 + _reset)`
103			`.endif`
104	355	julius	`_tickint:`
105			`#define TIMER_RELOAD_VALUE (SPR_TTMR_IE \| SPR_TTMR_RT \| ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))`
106			`/* Simply load timer_ticks variable and increment */`
107			`.extern _timer_ticks`
108			`l.addi r1, r1, -8`
109			`l.sw 0(r1), r25`
110			`l.sw 4(r1), r26`
111	375	julius	`l.movhi r25, hi(timestamp)`
112			`l.ori r25, r25, lo(timestamp)`
113	355	julius	`l.lwz r26, 0(r25) /* Load variable addr.*/`
114			`l.addi r26, r26, 1 /* Increment variable */`
115			`l.sw 0(r25), r26 /* Store variable */`
116			`l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */`
117			`l.ori r25, r25, lo(TIMER_RELOAD_VALUE)`
118			`l.mtspr r0, r25, SPR_TTMR /* Reset timer */`
119			`l.lwz r25, 0(r1)`
120			`l.lwz r26, 4(r1)`
121			`l.addi r1, r1, 8`
122			`l.rfe`
123	375	julius
124	2	marcus.erl	`.if IN_FLASH`
125			`.section .vectors, "ax"`
126			`.org 0x600`
127			`.else`
128			`.org (0x600 - 0x100 + _reset)`
129			`.endif`
130	140	julius	`_alignerr:`
131	246	julius	`.if 0`
132	140	julius	`l.trap 0`
133	246	julius	`.endif`
134	406	julius	`.if 0`
135	246	julius	`l.nop 0x1`
136	140	julius	`l.j 0`
137			`l.nop`
138	406	julius	`.endif`
139			`l.j _int_error`
140			`l.ori r3, r0, 0x6`
141	140	julius
142			`.if IN_FLASH`
143			`.org 0x700`
144			`.else`
145			`.org (0x700 - 0x100 + _reset)`
146			`.endif`
147	246	julius	`_illinsn:`
148			`.if 0`
149	140	julius	`/* Just trap */`
150			`l.trap 0`
151	246	julius	`.endif`
152	406	julius	`.if 0`
153	246	julius	`l.nop 0x1`
154	140	julius	`l.j 0`
155			`l.nop`
156	406	julius	`.endif`
157			`l.j _int_error`
158			`l.ori r3, r0, 0x7`
159	2	marcus.erl
160			`.if IN_FLASH`
161			`.org 0x800`
162			`.else`
163			`.org (0x800 - 0x100 + _reset)`
164			`.endif`
165	140	julius	`_userint:`
166	2	marcus.erl	`l.addi r1,r1,-128`
167	246	julius	`l.sw 0x0(r1),r2`
168			`l.addi r2, r1, 128`
169			`l.sw 0x4(r1), r3`
170			`l.movhi r3,hi(_int_wrapper)`
171			`l.ori r3,r3,lo(_int_wrapper)`
172			`l.jr r3`
173	2	marcus.erl	`l.nop`
174
175			`.section .text`
176			`_start:`
177			`.if IN_FLASH`
178	140	julius	`/* l.jal _init_mc`
179	2	marcus.erl	`l.nop`
180	140	julius	`*/`
181	2	marcus.erl	`/* Wait for SDRAM */`
182			`l.addi r3,r0,0x1000`
183			`1: l.sfeqi r3,0`
184			`l.bnf 1b`
185			`l.addi r3,r3,-1`
186			`.endif`
187			`/* Copy form flash to sram */`
188			`.if IN_FLASH`
189			`l.movhi r3,hi(_src_beg)`
190			`l.ori r3,r3,lo(_src_beg)`
191			`l.movhi r4,hi(_vec_start)`
192			`l.ori r4,r4,lo(_vec_start)`
193			`l.movhi r5,hi(_vec_end)`
194			`l.ori r5,r5,lo(_vec_end)`
195			`l.sub r5,r5,r4`
196			`l.sfeqi r5,0`
197			`l.bf 2f`
198			`l.nop`
199			`1: l.lwz r6,0(r3)`
200			`l.sw 0(r4),r6`
201			`l.addi r3,r3,4`
202			`l.addi r4,r4,4`
203			`l.addi r5,r5,-4`
204			`l.sfgtsi r5,0`
205			`l.bf 1b`
206			`l.nop`
207			`2:`
208			`l.movhi r4,hi(_dst_beg)`
209			`l.ori r4,r4,lo(_dst_beg)`
210			`l.movhi r5,hi(_dst_end)`
211			`l.ori r5,r5,lo(_dst_end)`
212			`1: l.sfgeu r4,r5`
213			`l.bf 1f`
214			`l.nop`
215			`l.lwz r8,0(r3)`
216			`l.sw 0(r4),r8`
217			`l.addi r3,r3,4`
218			`l.bnf 1b`
219			`l.addi r4,r4,4`
220			`1:`
221			`l.addi r3,r0,0`
222			`l.addi r4,r0,0`
223			`3:`
224			`.endif`
225
226	246	julius
227			`/* Instruction cache enable */`
228			`/* Check if IC present and skip enabling otherwise */`
229			`l.mfspr r24,r0,SPR_UPR`
230			`l.andi r26,r24,SPR_UPR_ICP`
231			`l.sfeq r26,r0`
232			`l.bf .L8`
233			`l.nop`
234
235			`/* Disable IC */`
236			`l.mfspr r6,r0,SPR_SR`
237			`l.addi r5,r0,-1`
238			`l.xori r5,r5,SPR_SR_ICE`
239			`l.and r5,r6,r5`
240			`l.mtspr r0,r5,SPR_SR`
241
242			`/* Establish cache block size`
243			`If BS=0, 16;`
244			`If BS=1, 32;`
245			`r14 contain block size`
246			`*/`
247			`l.mfspr r24,r0,SPR_ICCFGR`
248			`l.andi r26,r24,SPR_ICCFGR_CBS`
249			`l.srli r28,r26,7`
250			`l.ori r30,r0,16`
251			`l.sll r14,r30,r28`
252
253			`/* Establish number of cache sets`
254			`r16 contains number of cache sets`
255			`r28 contains log(# of cache sets)`
256			`*/`
257			`l.andi r26,r24,SPR_ICCFGR_NCS`
258			`l.srli r28,r26,3`
259			`l.ori r30,r0,1`
260			`l.sll r16,r30,r28`
261
262			`/* Invalidate IC */`
263			`l.addi r6,r0,0`
264			`l.sll r5,r14,r28`
265
266			`.L7:`
267			`l.mtspr r0,r6,SPR_ICBIR`
268			`l.sfne r6,r5`
269			`l.bf .L7`
270			`l.add r6,r6,r14`
271
272			`/* Enable IC */`
273			`l.mfspr r6,r0,SPR_SR`
274			`l.ori r6,r6,SPR_SR_ICE`
275			`l.mtspr r0,r6,SPR_SR`
276			`l.nop`
277			`l.nop`
278			`l.nop`
279			`l.nop`
280			`l.nop`
281			`l.nop`
282			`l.nop`
283			`l.nop`
284
285			`.L8:`
286			`/* Data cache enable */`
287			`/* Check if DC present and skip enabling otherwise */`
288			`l.mfspr r24,r0,SPR_UPR`
289			`l.andi r26,r24,SPR_UPR_DCP`
290			`l.sfeq r26,r0`
291			`l.bf .L10`
292	2	marcus.erl	`l.nop`
293	246	julius	`/* Disable DC */`
294			`l.mfspr r6,r0,SPR_SR`
295			`l.addi r5,r0,-1`
296			`l.xori r5,r5,SPR_SR_DCE`
297			`l.and r5,r6,r5`
298			`l.mtspr r0,r5,SPR_SR`
299			`/* Establish cache block size`
300			`If BS=0, 16;`
301			`If BS=1, 32;`
302			`r14 contain block size`
303			`*/`
304			`l.mfspr r24,r0,SPR_DCCFGR`
305			`l.andi r26,r24,SPR_DCCFGR_CBS`
306			`l.srli r28,r26,7`
307			`l.ori r30,r0,16`
308			`l.sll r14,r30,r28`
309			`/* Establish number of cache sets`
310			`r16 contains number of cache sets`
311			`r28 contains log(# of cache sets)`
312			`*/`
313			`l.andi r26,r24,SPR_DCCFGR_NCS`
314			`l.srli r28,r26,3`
315			`l.ori r30,r0,1`
316			`l.sll r16,r30,r28`
317			`/* Invalidate DC */`
318			`l.addi r6,r0,0`
319			`l.sll r5,r14,r28`
320			`.L9:`
321			`l.mtspr r0,r6,SPR_DCBIR`
322			`l.sfne r6,r5`
323			`l.bf .L9`
324			`l.add r6,r6,r14`
325			`/* Enable DC */`
326			`l.mfspr r6,r0,SPR_SR`
327			`l.ori r6,r6,SPR_SR_DCE`
328			`l.mtspr r0,r6,SPR_SR`
329	2	marcus.erl
330	246	julius	`.L10:`
331			`/* Set up stack */`
332	2	marcus.erl	`l.movhi r1,hi(_stack-4)`
333			`l.ori r1,r1,lo(_stack-4)`
334			`l.addi r2,r0,-3`
335			`l.and r1,r1,r2`
336	246	julius	`/* l.or r2, r1, r1 - remove this helped with odd UART output problem?!*/`
337	140	julius
338	375	julius	`l.movhi r3,hi(main)`
339			`l.ori r3,r3,lo(main)`
340	246	julius	`l.jr r3`
341			`l.nop`
342	140	julius
343	2	marcus.erl	`_int_wrapper:`
344
345	246	julius	`l.sw 0x8(r1), r4`
346			`l.sw 0xc(r1), r5`
347			`l.sw 0x10(r1), r6`
348			`l.sw 0x14(r1), r7`
349			`l.sw 0x18(r1), r8`
350			`l.sw 0x1c(r1), r9`
351			`l.sw 0x20(r1), r10`
352			`l.sw 0x24(r1), r11`
353			`l.sw 0x28(r1), r12`
354			`l.sw 0x2c(r1), r13`
355			`l.sw 0x30(r1), r14`
356			`l.sw 0x34(r1), r15`
357			`l.sw 0x38(r1), r16`
358			`l.sw 0x3c(r1), r17`
359			`l.sw 0x40(r1), r18`
360			`l.sw 0x44(r1), r19`
361			`l.sw 0x48(r1), r20`
362			`l.sw 0x4c(r1), r21`
363			`l.sw 0x50(r1), r22`
364			`l.sw 0x54(r1), r23`
365			`l.sw 0x58(r1), r24`
366			`l.sw 0x5c(r1), r25`
367			`l.sw 0x60(r1), r26`
368			`l.sw 0x64(r1), r27`
369			`l.sw 0x68(r1), r28`
370			`l.sw 0x6c(r1), r29`
371			`l.sw 0x70(r1), r30`
372			`l.sw 0x74(r1), r31`
373
374	375	julius	`l.movhi r3,hi(int_main)`
375			`l.ori r3,r3,lo(int_main)`
376	2	marcus.erl	`l.jalr r3`
377			`l.nop`
378
379	246	julius	`l.lwz r3,0x4(r1)`
380	2	marcus.erl	`l.lwz r4,0x8(r1)`
381			`l.lwz r5,0xc(r1)`
382			`l.lwz r6,0x10(r1)`
383			`l.lwz r7,0x14(r1)`
384			`l.lwz r8,0x18(r1)`
385			`l.lwz r9,0x1c(r1)`
386			`l.lwz r10,0x20(r1)`
387			`l.lwz r11,0x24(r1)`
388			`l.lwz r12,0x28(r1)`
389			`l.lwz r13,0x2c(r1)`
390			`l.lwz r14,0x30(r1)`
391			`l.lwz r15,0x34(r1)`
392			`l.lwz r16,0x38(r1)`
393			`l.lwz r17,0x3c(r1)`
394			`l.lwz r18,0x40(r1)`
395			`l.lwz r19,0x44(r1)`
396			`l.lwz r20,0x48(r1)`
397			`l.lwz r21,0x4c(r1)`
398			`l.lwz r22,0x50(r1)`
399			`l.lwz r23,0x54(r1)`
400			`l.lwz r24,0x58(r1)`
401			`l.lwz r25,0x5c(r1)`
402			`l.lwz r26,0x60(r1)`
403			`l.lwz r27,0x64(r1)`
404			`l.lwz r28,0x68(r1)`
405			`l.lwz r29,0x6c(r1)`
406			`l.lwz r30,0x70(r1)`
407	246	julius	`l.lwz r31,0x74(r1)`
408	2	marcus.erl
409	246	julius	`l.lwz r2, 0x0(r1)`
410	2	marcus.erl	`l.addi r1,r1,128`
411			`l.rfe`
412			`l.nop`
413	246	julius
414	2	marcus.erl
415			`_align:`
416			`l.sw 0x0c(r1),r3`
417			`l.sw 0x10(r1),r4`
418			`l.sw 0x14(r1),r5`
419			`l.sw 0x18(r1),r6`
420			`l.sw 0x1c(r1),r7`
421			`l.sw 0x20(r1),r8`
422			`l.sw 0x24(r1),r9`
423			`l.sw 0x28(r1),r10`
424			`l.sw 0x2c(r1),r11`
425			`l.sw 0x30(r1),r12`
426			`l.sw 0x34(r1),r13`
427			`l.sw 0x38(r1),r14`
428			`l.sw 0x3c(r1),r15`
429			`l.sw 0x40(r1),r16`
430			`l.sw 0x44(r1),r17`
431			`l.sw 0x48(r1),r18`
432			`l.sw 0x4c(r1),r19`
433			`l.sw 0x50(r1),r20`
434			`l.sw 0x54(r1),r21`
435			`l.sw 0x58(r1),r22`
436			`l.sw 0x5c(r1),r23`
437			`l.sw 0x60(r1),r24`
438			`l.sw 0x64(r1),r25`
439			`l.sw 0x68(r1),r26`
440			`l.sw 0x6c(r1),r27`
441			`l.sw 0x70(r1),r28`
442			`l.sw 0x74(r1),r29`
443			`l.sw 0x78(r1),r30`
444			`l.sw 0x7c(r1),r31`
445
446			`l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */`
447			`l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */`
448
449			`l.lwz r3,0(r5) /* Load insn */`
450			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
451
452			`l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */`
453			`l.bf jmp`
454			`l.sfeqi r4,0x01`
455			`l.bf jmp`
456			`l.sfeqi r4,0x03`
457			`l.bf jmp`
458			`l.sfeqi r4,0x04`
459			`l.bf jmp`
460			`l.sfeqi r4,0x11`
461			`l.bf jr`
462			`l.sfeqi r4,0x12`
463			`l.bf jr`
464			`l.nop`
465			`l.j 1f`
466			`l.addi r5,r5,4 /* Increment PC to get return insn address */`
467
468			`jmp:`
469			`l.slli r4,r3,6 /* Get the signed extended jump length */`
470			`l.srai r4,r4,4`
471
472			`l.lwz r3,4(r5) /* Load the real load/store insn */`
473
474			`l.add r5,r5,r4 /* Calculate jump target address */`
475
476			`l.j 1f`
477			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
478
479			`jr:`
480			`l.slli r4,r3,9 /* Shift to get the reg nb */`
481			`l.andi r4,r4,0x7c`
482
483			`l.lwz r3,4(r5) /* Load the real load/store insn */`
484
485			`l.add r4,r4,r1 /* Load the jump register value from the stack */`
486			`l.lwz r5,0(r4)`
487
488			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
489
490
491			`1: l.mtspr r0,r5,SPR_EPCR_BASE`
492
493			`l.sfeqi r4,0x26`
494			`l.bf lhs`
495			`l.sfeqi r4,0x25`
496			`l.bf lhz`
497			`l.sfeqi r4,0x22`
498			`l.bf lws`
499			`l.sfeqi r4,0x21`
500			`l.bf lwz`

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