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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Blame information for rev 353

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Instruction decode                                 ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Majority of instruction decoding is performed here.         ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
//
45 141 marcus.erl
// $Log: or1200_ctrl.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49 10 unneback
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55 185 julius
module or1200_ctrl
56
  (
57
   // Clock and reset
58
   clk, rst,
59
 
60
   // Internal i/f
61
   except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
62
   wb_flushpipe,
63
   id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
64
   id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
65
   rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op,
66
   rf_addrw, rfwb_op, fpu_op,
67
   wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
68
   sel_b, id_lsu_op,
69
   cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
70 258 julius
   multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
71 185 julius
   force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
72
   ex_spr_write,
73 258 julius
   id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal, dc_no_writethrough
74 185 julius
   );
75 10 unneback
 
76
//
77
// I/O
78
//
79
input                                   clk;
80
input                                   rst;
81
input                                   id_freeze;
82 353 julius
input                                   ex_freeze /* verilator public */;
83
input                                   wb_freeze /* verilator public */;
84 141 marcus.erl
output                                  if_flushpipe;
85
output                                  id_flushpipe;
86
output                                  ex_flushpipe;
87
output                                  wb_flushpipe;
88
input                                   extend_flush;
89
input                                   except_flushpipe;
90
input                           abort_mvspr ;
91
input   [31:0]                   if_insn;
92
output  [31:0]                   id_insn;
93 353 julius
output  [31:0]                   ex_insn /* verilator public */;
94 141 marcus.erl
output  [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
95
output  [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
96
input                                           ex_branch_taken;
97 10 unneback
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
98
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
99
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
100
output                                  rf_rda;
101
output                                  rf_rdb;
102
output  [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
103
output  [`OR1200_MACOP_WIDTH-1:0]                mac_op;
104
output  [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
105
output  [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
106 258 julius
output  [`OR1200_FPUOP_WIDTH-1:0]                fpu_op;
107 141 marcus.erl
input                                   pc_we;
108 10 unneback
output  [31:0]                           wb_insn;
109 141 marcus.erl
output  [31:2]                          id_branch_addrtarget;
110
output  [31:2]                          ex_branch_addrtarget;
111 10 unneback
output  [`OR1200_SEL_WIDTH-1:0]          sel_a;
112
output  [`OR1200_SEL_WIDTH-1:0]          sel_b;
113 141 marcus.erl
output  [`OR1200_LSUOP_WIDTH-1:0]                id_lsu_op;
114 10 unneback
output  [`OR1200_COMPOP_WIDTH-1:0]               comp_op;
115
output  [`OR1200_MULTICYCLE_WIDTH-1:0]           multicycle;
116 258 julius
output  [`OR1200_WAIT_ON_WIDTH-1:0]              wait_on;
117 10 unneback
output  [4:0]                            cust5_op;
118
output  [5:0]                            cust5_limm;
119 141 marcus.erl
input   [31:0]                          id_pc;
120
input   [31:0]                          ex_pc;
121
output  [31:0]                           id_simm;
122
output  [31:0]                           ex_simm;
123 10 unneback
input                                   wbforw_valid;
124
input                                   du_hwbkpt;
125
output                                  sig_syscall;
126
output                                  sig_trap;
127
output                                  force_dslot_fetch;
128
output                                  no_more_dslot;
129 141 marcus.erl
output                                  id_void;
130 10 unneback
output                                  ex_void;
131 141 marcus.erl
output                                  ex_spr_read;
132
output                                  ex_spr_write;
133
output  [`OR1200_MACOP_WIDTH-1:0]        id_mac_op;
134 10 unneback
output                                  id_macrc_op;
135
output                                  ex_macrc_op;
136
output                                  rfe;
137
output                                  except_illegal;
138 258 julius
output                                  dc_no_writethrough;
139
 
140
 
141 10 unneback
//
142
// Internal wires and regs
143
//
144 141 marcus.erl
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
145
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
146 10 unneback
reg     [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
147 141 marcus.erl
wire                                    if_maci_op;
148 10 unneback
`ifdef OR1200_MAC_IMPLEMENTED
149 141 marcus.erl
reg     [`OR1200_MACOP_WIDTH-1:0]                ex_mac_op;
150
reg     [`OR1200_MACOP_WIDTH-1:0]                id_mac_op;
151
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
152 10 unneback
reg                                     ex_macrc_op;
153
`else
154
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
155
wire                                    ex_macrc_op;
156
`endif
157
reg     [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
158 353 julius
reg     [31:0]                           id_insn /* verilator public */;
159
reg     [31:0]                           ex_insn /* verilator public */;
160
reg     [31:0]                           wb_insn /* verilator public */;
161 10 unneback
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
162
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
163
reg     [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
164
reg     [`OR1200_SEL_WIDTH-1:0]          sel_a;
165
reg     [`OR1200_SEL_WIDTH-1:0]          sel_b;
166
reg                                     sel_imm;
167 141 marcus.erl
reg     [`OR1200_LSUOP_WIDTH-1:0]                id_lsu_op;
168 10 unneback
reg     [`OR1200_COMPOP_WIDTH-1:0]               comp_op;
169
reg     [`OR1200_MULTICYCLE_WIDTH-1:0]           multicycle;
170 258 julius
reg     [`OR1200_WAIT_ON_WIDTH-1:0]              wait_on;
171 141 marcus.erl
reg     [31:0]                           id_simm;
172
reg     [31:0]                           ex_simm;
173 10 unneback
reg                                     sig_syscall;
174
reg                                     sig_trap;
175
reg                                     except_illegal;
176
wire                                    id_void;
177 141 marcus.erl
wire                                    ex_void;
178
wire                                    wb_void;
179
reg                                     ex_delayslot_dsi;
180
reg                                     ex_delayslot_nop;
181
reg                                     spr_read;
182
reg                                     spr_write;
183
reg     [31:2]                          ex_branch_addrtarget;
184 258 julius
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
185
reg                                     dc_no_writethrough;
186
`endif
187
 
188 10 unneback
//
189
// Register file read addresses
190
//
191
assign rf_addra = if_insn[20:16];
192
assign rf_addrb = if_insn[15:11];
193 141 marcus.erl
assign rf_rda = if_insn[31] || if_maci_op;
194 10 unneback
assign rf_rdb = if_insn[30];
195
 
196
//
197
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
198
// instructions
199
//
200
assign force_dslot_fetch = 1'b0;
201 141 marcus.erl
assign no_more_dslot = (|ex_branch_op & !id_void & ex_branch_taken) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
202
 
203 10 unneback
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
204
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
205 141 marcus.erl
assign wb_void = (wb_insn[31:26] == `OR1200_OR32_NOP) & wb_insn[16];
206 10 unneback
 
207 141 marcus.erl
assign ex_spr_write = spr_write && !abort_mvspr;
208
assign ex_spr_read = spr_read && !abort_mvspr;
209
 
210 10 unneback
//
211 141 marcus.erl
// ex_delayslot_dsi: delay slot insn is in EX stage
212
// ex_delayslot_nop: (filler) nop insn is in EX stage (before nops jump/branch was executed)
213 10 unneback
//
214 141 marcus.erl
//  ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
215
//  !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage, 
216
//       next different is DS insn, previous different was Jump/Branch
217
//  !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
218
//
219
always @(posedge clk or posedge rst) begin
220
        if (rst) begin
221 258 julius
                ex_delayslot_nop <=  1'b0;
222
                ex_delayslot_dsi <=  1'b0;
223 141 marcus.erl
        end
224
        else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
225 258 julius
                ex_delayslot_nop <=  id_void;
226
                ex_delayslot_dsi <=  !id_void;
227 141 marcus.erl
        end
228
        else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
229 258 julius
                ex_delayslot_nop <=  1'b0;
230
                ex_delayslot_dsi <=  1'b0;
231 141 marcus.erl
        end
232
        else if (!ex_freeze) begin
233 258 julius
                ex_delayslot_nop <=  id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
234 141 marcus.erl
                                                                (ex_branch_op != `OR1200_BRANCHOP_RFE);
235 258 julius
                ex_delayslot_dsi <=  !id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
236 141 marcus.erl
                                                                 (ex_branch_op != `OR1200_BRANCHOP_RFE);
237
        end
238
end
239 10 unneback
 
240
//
241 141 marcus.erl
// Flush pipeline
242 10 unneback
//
243 141 marcus.erl
assign if_flushpipe = except_flushpipe | pc_we | extend_flush;
244
assign id_flushpipe = except_flushpipe | pc_we | extend_flush;
245
assign ex_flushpipe = except_flushpipe | pc_we | extend_flush;
246
assign wb_flushpipe = except_flushpipe | pc_we | extend_flush;
247 10 unneback
 
248
//
249 141 marcus.erl
// EX Sign/Zero extension of immediates
250
//
251
always @(posedge clk or posedge rst) begin
252
        if (rst)
253 258 julius
                ex_simm <=  32'h0000_0000;
254 141 marcus.erl
        else if (!ex_freeze) begin
255 258 julius
                ex_simm <=  id_simm;
256 141 marcus.erl
        end
257
end
258
 
259
//
260
// ID Sign/Zero extension of immediate
261
//
262
always @(id_insn) begin
263
        case (id_insn[31:26])     // synopsys parallel_case
264
 
265
        // l.addi
266
        `OR1200_OR32_ADDI:
267
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
268
 
269
        // l.addic
270
        `OR1200_OR32_ADDIC:
271
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
272
 
273
        // l.lxx (load instructions)
274
        `OR1200_OR32_LWZ, `OR1200_OR32_LBZ, `OR1200_OR32_LBS, `OR1200_OR32_LHZ, `OR1200_OR32_LHS:
275
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
276
 
277
        // l.muli
278
        `ifdef OR1200_MULT_IMPLEMENTED
279
        `OR1200_OR32_MULI:
280
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
281
        `endif
282
 
283
        // l.maci
284
        `ifdef OR1200_MAC_IMPLEMENTED
285
        `OR1200_OR32_MACI:
286
                id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
287
        `endif
288
 
289
        // l.mtspr
290
        `OR1200_OR32_MTSPR:
291
                id_simm = {16'b0, id_insn[25:21], id_insn[10:0]};
292
 
293
        // l.sxx (store instructions)
294
        `OR1200_OR32_SW, `OR1200_OR32_SH, `OR1200_OR32_SB:
295
                id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
296
 
297
        // l.xori
298
        `OR1200_OR32_XORI:
299
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
300
 
301
        // l.sfxxi (SFXX with immediate)
302
        `OR1200_OR32_SFXXI:
303
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
304
 
305
        // Instructions with no or zero extended immediate
306
        default:
307
                id_simm = {{16'b0}, id_insn[15:0]};
308
 
309
        endcase
310
end
311
 
312
//
313
// ID Sign extension of branch offset
314
//
315
assign id_branch_addrtarget = {{4{id_insn[25]}}, id_insn[25:0]} + id_pc[31:2];
316
 
317
//
318
// EX Sign extension of branch offset
319
//
320
 
321
// pipeline ID and EX branch target address 
322
always @(posedge clk or posedge rst) begin
323
        if (rst)
324 258 julius
                ex_branch_addrtarget <=  32'h00000000;
325 141 marcus.erl
        else if (!ex_freeze)
326 258 julius
                ex_branch_addrtarget <=  id_branch_addrtarget;
327 141 marcus.erl
end
328
// not pipelined
329
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
330
 
331
//
332
// l.maci in IF stage
333
//
334
`ifdef OR1200_MAC_IMPLEMENTED
335
assign if_maci_op = (if_insn[31:26] == `OR1200_OR32_MACI);
336
`else
337
assign if_maci_op = 1'b0;
338
`endif
339
 
340
//
341 10 unneback
// l.macrc in ID stage
342
//
343
`ifdef OR1200_MAC_IMPLEMENTED
344
assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
345
`else
346
assign id_macrc_op = 1'b0;
347
`endif
348
 
349
//
350 141 marcus.erl
// l.macrc in EX stage
351
//
352
`ifdef OR1200_MAC_IMPLEMENTED
353
always @(posedge clk or posedge rst) begin
354
        if (rst)
355 258 julius
                ex_macrc_op <=  1'b0;
356 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
357 258 julius
                ex_macrc_op <=  1'b0;
358 141 marcus.erl
        else if (!ex_freeze)
359 258 julius
                ex_macrc_op <=  id_macrc_op;
360 141 marcus.erl
end
361
`else
362
assign ex_macrc_op = 1'b0;
363
`endif
364
 
365
//
366 10 unneback
// cust5_op, cust5_limm (L immediate)
367
//
368
assign cust5_op = ex_insn[4:0];
369
assign cust5_limm = ex_insn[10:5];
370
 
371
//
372
//
373
//
374 141 marcus.erl
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
375 10 unneback
 
376 353 julius
 
377
`ifdef verilator
378
   // Function to access wb_insn (for Verilator). Have to hide this from
379
   // simulator, since functions with no inputs are not allowed in IEEE
380
   // 1364-2001.
381
   function [31:0] get_wb_insn;
382
      // verilator public
383
      get_wb_insn = wb_insn;
384
   endfunction // get_wb_insn
385
 
386
   // Function to access id_insn (for Verilator). Have to hide this from
387
   // simulator, since functions with no inputs are not allowed in IEEE
388
   // 1364-2001.
389
   function [31:0] get_id_insn;
390
      // verilator public
391
      get_id_insn = id_insn;
392
   endfunction // get_id_insn
393
 
394
   // Function to access ex_insn (for Verilator). Have to hide this from
395
   // simulator, since functions with no inputs are not allowed in IEEE
396
   // 1364-2001.
397
   function [31:0] get_ex_insn;
398
      // verilator public
399
      get_ex_insn = ex_insn;
400
   endfunction // get_ex_insn
401
 
402
`endif
403
 
404
 
405 10 unneback
//
406
// Generation of sel_a
407
//
408
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
409
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
410
                sel_a = `OR1200_SEL_EX_FORW;
411
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
412
                sel_a = `OR1200_SEL_WB_FORW;
413
        else
414
                sel_a = `OR1200_SEL_RF;
415
 
416
//
417
// Generation of sel_b
418
//
419
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
420
        if (sel_imm)
421
                sel_b = `OR1200_SEL_IMM;
422
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
423
                sel_b = `OR1200_SEL_EX_FORW;
424
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
425
                sel_b = `OR1200_SEL_WB_FORW;
426
        else
427
                sel_b = `OR1200_SEL_RF;
428
 
429
//
430
// Decode of multicycle
431
//
432
always @(id_insn) begin
433
  case (id_insn[31:26])         // synopsys parallel_case
434
`ifdef UNUSED
435
    // l.lwz
436
    `OR1200_OR32_LWZ:
437
      multicycle = `OR1200_TWO_CYCLES;
438
 
439
    // l.lbz
440
    `OR1200_OR32_LBZ:
441
      multicycle = `OR1200_TWO_CYCLES;
442
 
443
    // l.lbs
444
    `OR1200_OR32_LBS:
445
      multicycle = `OR1200_TWO_CYCLES;
446
 
447
    // l.lhz
448
    `OR1200_OR32_LHZ:
449
      multicycle = `OR1200_TWO_CYCLES;
450
 
451
    // l.lhs
452
    `OR1200_OR32_LHS:
453
      multicycle = `OR1200_TWO_CYCLES;
454
 
455
    // l.sw
456
    `OR1200_OR32_SW:
457
      multicycle = `OR1200_TWO_CYCLES;
458
 
459
    // l.sb
460
    `OR1200_OR32_SB:
461
      multicycle = `OR1200_TWO_CYCLES;
462
 
463
    // l.sh
464
    `OR1200_OR32_SH:
465
      multicycle = `OR1200_TWO_CYCLES;
466
`endif
467 141 marcus.erl
    // l.mfspr
468
    `OR1200_OR32_MFSPR:
469
      multicycle = `OR1200_TWO_CYCLES;  // to read from ITLB/DTLB (sync RAMs)
470
 
471 10 unneback
    // ALU instructions except the one with immediate
472
    `OR1200_OR32_ALU:
473 141 marcus.erl
        case (id_insn[3:0]) // synopsys parallel_case
474
        4'h6: multicycle = 2'b11; // l.mul
475
        4'h9: multicycle = 2'b10; // l.div
476
        4'hA: multicycle = 2'b10; // l.divu
477
        4'hB: multicycle = 2'b11; // l.mulu
478
        default: multicycle = 2'b00;
479
        endcase
480 10 unneback
 
481 141 marcus.erl
    `OR1200_OR32_MULI:
482
      multicycle = 2'h3;
483
 
484 10 unneback
    // Single cycle instructions
485
    default: begin
486
      multicycle = `OR1200_ONE_CYCLE;
487 258 julius
    end
488 10 unneback
  endcase
489 258 julius
end // always @ (id_insn)
490 10 unneback
 
491
//
492 258 julius
// Encode wait_on signal
493
//    
494
always @(id_insn) begin
495
   case (id_insn[31:26])                // synopsys parallel_case
496
`ifdef OR1200_FPU_IMPLEMENTED
497
       `OR1200_OR32_FLOAT: begin
498
         wait_on = id_insn[`OR1200_FPUOP_DOUBLE_BIT] ? 0 : `OR1200_WAIT_ON_FPU;
499
       end
500
`endif
501
`ifndef OR1200_DC_WRITHROUGH
502
     // l.mtspr
503
     `OR1200_OR32_MTSPR: begin
504
        wait_on = `OR1200_WAIT_ON_MTSPR;
505
     end
506
`endif
507
     default: begin
508
        wait_on = 0;
509
     end
510
   endcase // case (id_insn[31:26])
511
end // always @ (id_insn)
512
 
513
 
514
 
515
 
516
//
517 10 unneback
// Register file write address
518
//
519
always @(posedge clk or posedge rst) begin
520
        if (rst)
521 258 julius
                rf_addrw <=  5'd0;
522 10 unneback
        else if (!ex_freeze & id_freeze)
523 258 julius
                rf_addrw <=  5'd00;
524 10 unneback
        else if (!ex_freeze)
525 141 marcus.erl
                case (id_insn[31:26])   // synopsys parallel_case
526
                        `OR1200_OR32_JAL, `OR1200_OR32_JALR:
527 258 julius
                                rf_addrw <=  5'd09;     // link register r9
528 10 unneback
                        default:
529 258 julius
                                rf_addrw <=  id_insn[25:21];
530 10 unneback
                endcase
531
end
532
 
533
//
534
// rf_addrw in wb stage (used in forwarding logic)
535
//
536
always @(posedge clk or posedge rst) begin
537
        if (rst)
538 258 julius
                wb_rfaddrw <=  5'd0;
539 10 unneback
        else if (!wb_freeze)
540 258 julius
                wb_rfaddrw <=  rf_addrw;
541 10 unneback
end
542
 
543
//
544
// Instruction latch in id_insn
545
//
546
always @(posedge clk or posedge rst) begin
547
        if (rst)
548 258 julius
                id_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
549 141 marcus.erl
        else if (id_flushpipe)
550 258 julius
                id_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};        // NOP -> id_insn[16] must be 1
551 10 unneback
        else if (!id_freeze) begin
552 258 julius
                id_insn <=  if_insn;
553 10 unneback
`ifdef OR1200_VERBOSE
554
// synopsys translate_off
555
                $display("%t: id_insn <= %h", $time, if_insn);
556
// synopsys translate_on
557
`endif
558
        end
559
end
560
 
561
//
562
// Instruction latch in ex_insn
563
//
564
always @(posedge clk or posedge rst) begin
565
        if (rst)
566 258 julius
                ex_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
567 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
568 258 julius
                ex_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};   // NOP -> ex_insn[16] must be 1
569 10 unneback
        else if (!ex_freeze) begin
570 258 julius
                ex_insn <=  id_insn;
571 10 unneback
`ifdef OR1200_VERBOSE
572
// synopsys translate_off
573
                $display("%t: ex_insn <= %h", $time, id_insn);
574
// synopsys translate_on
575
`endif
576
        end
577
end
578 258 julius
 
579 10 unneback
//
580
// Instruction latch in wb_insn
581
//
582
always @(posedge clk or posedge rst) begin
583
        if (rst)
584 258 julius
                wb_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
585 141 marcus.erl
        // wb_insn should not be changed by exceptions due to correct 
586
        // recording of display_arch_state in the or1200_monitor! 
587
        // wb_insn changed by exception is not used elsewhere! 
588 10 unneback
        else if (!wb_freeze) begin
589 258 julius
                wb_insn <=  ex_insn;
590 10 unneback
        end
591
end
592
 
593
//
594
// Decode of sel_imm
595
//
596
always @(posedge clk or posedge rst) begin
597
        if (rst)
598 258 julius
                sel_imm <=  1'b0;
599 10 unneback
        else if (!id_freeze) begin
600
          case (if_insn[31:26])         // synopsys parallel_case
601
 
602
            // j.jalr
603
            `OR1200_OR32_JALR:
604 258 julius
              sel_imm <=  1'b0;
605 10 unneback
 
606
            // l.jr
607
            `OR1200_OR32_JR:
608 258 julius
              sel_imm <=  1'b0;
609 10 unneback
 
610
            // l.rfe
611
            `OR1200_OR32_RFE:
612 258 julius
              sel_imm <=  1'b0;
613 10 unneback
 
614
            // l.mfspr
615
            `OR1200_OR32_MFSPR:
616 258 julius
              sel_imm <=  1'b0;
617 10 unneback
 
618
            // l.mtspr
619
            `OR1200_OR32_MTSPR:
620 258 julius
              sel_imm <=  1'b0;
621 10 unneback
 
622
            // l.sys, l.brk and all three sync insns
623
            `OR1200_OR32_XSYNC:
624 258 julius
              sel_imm <=  1'b0;
625 10 unneback
 
626
            // l.mac/l.msb
627
`ifdef OR1200_MAC_IMPLEMENTED
628
            `OR1200_OR32_MACMSB:
629 258 julius
              sel_imm <=  1'b0;
630 10 unneback
`endif
631
 
632
            // l.sw
633
            `OR1200_OR32_SW:
634 258 julius
              sel_imm <=  1'b0;
635 10 unneback
 
636
            // l.sb
637
            `OR1200_OR32_SB:
638 258 julius
              sel_imm <=  1'b0;
639 10 unneback
 
640
            // l.sh
641
            `OR1200_OR32_SH:
642 258 julius
              sel_imm <=  1'b0;
643 10 unneback
 
644
            // ALU instructions except the one with immediate
645
            `OR1200_OR32_ALU:
646 258 julius
              sel_imm <=  1'b0;
647 10 unneback
 
648
            // SFXX instructions
649
            `OR1200_OR32_SFXX:
650 258 julius
              sel_imm <=  1'b0;
651 10 unneback
 
652
`ifdef OR1200_OR32_CUST5
653
            // l.cust5 instructions
654
            `OR1200_OR32_CUST5:
655 258 julius
              sel_imm <=  1'b0;
656 10 unneback
`endif
657 185 julius
`ifdef OR1200_FPU_IMPLEMENTED
658
            // FPU instructions
659
            `OR1200_OR32_FLOAT:
660 258 julius
              sel_imm <=  1'b0;
661 185 julius
`endif
662 10 unneback
            // l.nop
663
            `OR1200_OR32_NOP:
664 258 julius
              sel_imm <=  1'b0;
665 10 unneback
 
666
            // All instructions with immediates
667
            default: begin
668 258 julius
              sel_imm <=  1'b1;
669 10 unneback
            end
670
 
671
          endcase
672
 
673
        end
674
end
675
 
676
//
677
// Decode of except_illegal
678
//
679
always @(posedge clk or posedge rst) begin
680
        if (rst)
681 258 julius
                except_illegal <=  1'b0;
682 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
683 258 julius
                except_illegal <=  1'b0;
684 10 unneback
        else if (!ex_freeze) begin
685 141 marcus.erl
                case (id_insn[31:26])           // synopsys parallel_case
686 10 unneback
 
687 141 marcus.erl
                `OR1200_OR32_J,
688
                `OR1200_OR32_JAL,
689
                `OR1200_OR32_JALR,
690
                `OR1200_OR32_JR,
691
                `OR1200_OR32_BNF,
692
                `OR1200_OR32_BF,
693
                `OR1200_OR32_RFE,
694
                `OR1200_OR32_MOVHI,
695
                `OR1200_OR32_MFSPR,
696
                `OR1200_OR32_XSYNC,
697 10 unneback
`ifdef OR1200_MAC_IMPLEMENTED
698 141 marcus.erl
                `OR1200_OR32_MACI,
699 10 unneback
`endif
700 141 marcus.erl
                `OR1200_OR32_LWZ,
701
                `OR1200_OR32_LBZ,
702
                `OR1200_OR32_LBS,
703
                `OR1200_OR32_LHZ,
704
                `OR1200_OR32_LHS,
705
                `OR1200_OR32_ADDI,
706
                `OR1200_OR32_ADDIC,
707
                `OR1200_OR32_ANDI,
708
                `OR1200_OR32_ORI,
709
                `OR1200_OR32_XORI,
710 10 unneback
`ifdef OR1200_MULT_IMPLEMENTED
711 141 marcus.erl
                `OR1200_OR32_MULI,
712 10 unneback
`endif
713 141 marcus.erl
                `OR1200_OR32_SH_ROTI,
714
                `OR1200_OR32_SFXXI,
715
                `OR1200_OR32_MTSPR,
716 10 unneback
`ifdef OR1200_MAC_IMPLEMENTED
717 141 marcus.erl
                `OR1200_OR32_MACMSB,
718 10 unneback
`endif
719 141 marcus.erl
                `OR1200_OR32_SW,
720
                `OR1200_OR32_SB,
721
                `OR1200_OR32_SH,
722
                `OR1200_OR32_SFXX,
723 10 unneback
`ifdef OR1200_OR32_CUST5
724 141 marcus.erl
                `OR1200_OR32_CUST5,
725 10 unneback
`endif
726 141 marcus.erl
        `OR1200_OR32_NOP:
727 258 julius
                        except_illegal <=  1'b0;
728 185 julius
`ifdef OR1200_FPU_IMPLEMENTED
729
            `OR1200_OR32_FLOAT:
730
                        // Check it's not a double precision instruction
731 258 julius
                        except_illegal <=  id_insn[`OR1200_FPUOP_DOUBLE_BIT];
732 185 julius
`endif
733 10 unneback
 
734 141 marcus.erl
        `OR1200_OR32_ALU:
735 258 julius
                        except_illegal <=  1'b0
736 10 unneback
 
737 141 marcus.erl
`ifdef OR1200_MULT_IMPLEMENTED
738 258 julius
`ifdef OR1200_DIV_IMPLEMENTED
739 141 marcus.erl
`else
740
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
741
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
742
`endif
743
`else
744
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
745
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
746
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_MUL)
747
`endif
748
 
749
`ifdef OR1200_IMPL_ADDC
750
`else
751
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_ADDC)
752
`endif
753
 
754
`ifdef OR1200_IMPL_ALU_ROTATE
755
`else
756
                                | (({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SHROT) && (id_insn[7:6] == `OR1200_SHROTOP_ROR))
757
`endif
758
 
759
`ifdef OR1200_IMPL_SUB
760
`else
761
                                | ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SUB)
762
`endif
763
                                ;
764
 
765
                // Illegal and OR1200 unsupported instructions
766
                default:
767 258 julius
                        except_illegal <=  1'b1;
768 141 marcus.erl
 
769
                endcase
770 10 unneback
 
771
        end
772
end
773
 
774
//
775
// Decode of alu_op
776
//
777
always @(posedge clk or posedge rst) begin
778
        if (rst)
779 258 julius
                alu_op <=  `OR1200_ALUOP_NOP;
780 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
781 258 julius
                alu_op <=  `OR1200_ALUOP_NOP;
782 10 unneback
        else if (!ex_freeze) begin
783
          case (id_insn[31:26])         // synopsys parallel_case
784
 
785
            // l.movhi
786
            `OR1200_OR32_MOVHI:
787 258 julius
              alu_op <=  `OR1200_ALUOP_MOVHI;
788 10 unneback
 
789
            // l.addi
790
            `OR1200_OR32_ADDI:
791 258 julius
              alu_op <=  `OR1200_ALUOP_ADD;
792 10 unneback
 
793
            // l.addic
794
            `OR1200_OR32_ADDIC:
795 258 julius
              alu_op <=  `OR1200_ALUOP_ADDC;
796 10 unneback
 
797
            // l.andi
798
            `OR1200_OR32_ANDI:
799 258 julius
              alu_op <=  `OR1200_ALUOP_AND;
800 10 unneback
 
801
            // l.ori
802
            `OR1200_OR32_ORI:
803 258 julius
              alu_op <=  `OR1200_ALUOP_OR;
804 10 unneback
 
805
            // l.xori
806
            `OR1200_OR32_XORI:
807 258 julius
              alu_op <=  `OR1200_ALUOP_XOR;
808 10 unneback
 
809
            // l.muli
810
`ifdef OR1200_MULT_IMPLEMENTED
811
            `OR1200_OR32_MULI:
812 258 julius
              alu_op <=  `OR1200_ALUOP_MUL;
813 10 unneback
`endif
814
 
815
            // Shift and rotate insns with immediate
816
            `OR1200_OR32_SH_ROTI:
817 258 julius
              alu_op <=  `OR1200_ALUOP_SHROT;
818 10 unneback
 
819
            // SFXX insns with immediate
820
            `OR1200_OR32_SFXXI:
821 258 julius
              alu_op <=  `OR1200_ALUOP_COMP;
822 10 unneback
 
823
            // ALU instructions except the one with immediate
824
            `OR1200_OR32_ALU:
825 258 julius
              alu_op <=  id_insn[3:0];
826 10 unneback
 
827
            // SFXX instructions
828
            `OR1200_OR32_SFXX:
829 258 julius
              alu_op <=  `OR1200_ALUOP_COMP;
830 10 unneback
 
831
`ifdef OR1200_OR32_CUST5
832
            // l.cust5 instructions
833
            `OR1200_OR32_CUST5:
834 258 julius
              alu_op <=  `OR1200_ALUOP_CUST5;
835 10 unneback
`endif
836
 
837
            // Default
838
            default: begin
839 258 julius
              alu_op <=  `OR1200_ALUOP_NOP;
840 10 unneback
            end
841
 
842
          endcase
843
 
844
        end
845
end
846
 
847
//
848 141 marcus.erl
// Decode of spr_read, spr_write
849
//
850
always @(posedge clk or posedge rst) begin
851
        if (rst) begin
852 258 julius
                spr_read <=  1'b0;
853
                spr_write <=  1'b0;
854 141 marcus.erl
        end
855
        else if (!ex_freeze & id_freeze | ex_flushpipe) begin
856 258 julius
                spr_read <=  1'b0;
857
                spr_write <=  1'b0;
858 141 marcus.erl
        end
859
        else if (!ex_freeze) begin
860
                case (id_insn[31:26])     // synopsys parallel_case
861
 
862
                // l.mfspr
863
                `OR1200_OR32_MFSPR: begin
864 258 julius
                        spr_read <=  1'b1;
865
                        spr_write <=  1'b0;
866 141 marcus.erl
                end
867
 
868
                // l.mtspr
869
                `OR1200_OR32_MTSPR: begin
870 258 julius
                        spr_read <=  1'b0;
871
                        spr_write <=  1'b1;
872 141 marcus.erl
                end
873
 
874
                // Default
875
                default: begin
876 258 julius
                        spr_read <=  1'b0;
877
                        spr_write <=  1'b0;
878 141 marcus.erl
                end
879
 
880
                endcase
881
        end
882
end
883
 
884
//
885 10 unneback
// Decode of mac_op
886
//
887
`ifdef OR1200_MAC_IMPLEMENTED
888 141 marcus.erl
always @(id_insn) begin
889
        case (id_insn[31:26])           // synopsys parallel_case
890 10 unneback
 
891 141 marcus.erl
        // l.maci
892
        `OR1200_OR32_MACI:
893 353 julius
                id_mac_op =  `OR1200_MACOP_MAC;
894 10 unneback
 
895 141 marcus.erl
        // l.mac, l.msb
896
        `OR1200_OR32_MACMSB:
897 353 julius
                id_mac_op =  id_insn[2:0];
898 10 unneback
 
899 141 marcus.erl
        // Illegal and OR1200 unsupported instructions
900
        default:
901 353 julius
                id_mac_op =  `OR1200_MACOP_NOP;
902 10 unneback
 
903 141 marcus.erl
        endcase
904 10 unneback
end
905 141 marcus.erl
 
906
always @(posedge clk or posedge rst) begin
907
        if (rst)
908 258 julius
                ex_mac_op <=  `OR1200_MACOP_NOP;
909 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
910 258 julius
                ex_mac_op <=  `OR1200_MACOP_NOP;
911 141 marcus.erl
        else if (!ex_freeze)
912 258 julius
                ex_mac_op <=  id_mac_op;
913 141 marcus.erl
end
914
 
915
assign mac_op = abort_mvspr ? `OR1200_MACOP_NOP : ex_mac_op;
916 10 unneback
`else
917 141 marcus.erl
assign id_mac_op = `OR1200_MACOP_NOP;
918 10 unneback
assign mac_op = `OR1200_MACOP_NOP;
919
`endif
920
 
921
//
922
// Decode of shrot_op
923
//
924
always @(posedge clk or posedge rst) begin
925
        if (rst)
926 258 julius
                shrot_op <=  `OR1200_SHROTOP_NOP;
927 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
928 258 julius
                shrot_op <=  `OR1200_SHROTOP_NOP;
929 10 unneback
        else if (!ex_freeze) begin
930 258 julius
                shrot_op <=  id_insn[`OR1200_SHROTOP_POS];
931 10 unneback
        end
932
end
933
 
934
//
935
// Decode of rfwb_op
936
//
937
always @(posedge clk or posedge rst) begin
938
        if (rst)
939 258 julius
                rfwb_op <=  `OR1200_RFWBOP_NOP;
940 141 marcus.erl
        else  if (!ex_freeze & id_freeze | ex_flushpipe)
941 258 julius
                rfwb_op <=  `OR1200_RFWBOP_NOP;
942 10 unneback
        else  if (!ex_freeze) begin
943
                case (id_insn[31:26])           // synopsys parallel_case
944
 
945 141 marcus.erl
                // j.jal
946
                `OR1200_OR32_JAL:
947 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_LR, 1'b1};
948 10 unneback
 
949 141 marcus.erl
                // j.jalr
950
                `OR1200_OR32_JALR:
951 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_LR, 1'b1};
952 10 unneback
 
953 141 marcus.erl
                // l.movhi
954
                `OR1200_OR32_MOVHI:
955 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
956 10 unneback
 
957 141 marcus.erl
                // l.mfspr
958
                `OR1200_OR32_MFSPR:
959 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_SPRS, 1'b1};
960 10 unneback
 
961 141 marcus.erl
                // l.lwz
962
                `OR1200_OR32_LWZ:
963 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
964 10 unneback
 
965 141 marcus.erl
                // l.lbz
966
                `OR1200_OR32_LBZ:
967 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
968 10 unneback
 
969 141 marcus.erl
                // l.lbs
970
                `OR1200_OR32_LBS:
971 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
972 10 unneback
 
973 141 marcus.erl
                // l.lhz
974
                `OR1200_OR32_LHZ:
975 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
976 10 unneback
 
977 141 marcus.erl
                // l.lhs
978
                `OR1200_OR32_LHS:
979 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
980 10 unneback
 
981 141 marcus.erl
                // l.addi
982
                `OR1200_OR32_ADDI:
983 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
984 10 unneback
 
985 141 marcus.erl
                // l.addic
986
                `OR1200_OR32_ADDIC:
987 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
988 10 unneback
 
989 141 marcus.erl
                // l.andi
990
                `OR1200_OR32_ANDI:
991 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
992 10 unneback
 
993 141 marcus.erl
                // l.ori
994
                `OR1200_OR32_ORI:
995 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
996 10 unneback
 
997 141 marcus.erl
                // l.xori
998
                `OR1200_OR32_XORI:
999 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1000 10 unneback
 
1001 141 marcus.erl
                // l.muli
1002 10 unneback
`ifdef OR1200_MULT_IMPLEMENTED
1003 141 marcus.erl
                `OR1200_OR32_MULI:
1004 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1005 10 unneback
`endif
1006
 
1007 141 marcus.erl
                // Shift and rotate insns with immediate
1008
                `OR1200_OR32_SH_ROTI:
1009 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1010 10 unneback
 
1011 141 marcus.erl
                // ALU instructions except the one with immediate
1012
                `OR1200_OR32_ALU:
1013 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1014 10 unneback
 
1015
`ifdef OR1200_OR32_CUST5
1016 141 marcus.erl
                // l.cust5 instructions
1017
                `OR1200_OR32_CUST5:
1018 258 julius
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1019 10 unneback
`endif
1020 185 julius
`ifdef OR1200_FPU_IMPLEMENTED
1021
                  // FPU instructions, lf.XXX.s, except sfxx
1022
                  `OR1200_OR32_FLOAT:
1023 258 julius
                    rfwb_op <=  {`OR1200_RFWBOP_FPU,!id_insn[3]};
1024 185 julius
`endif
1025 141 marcus.erl
                // Instructions w/o register-file write-back
1026
                default:
1027 258 julius
                        rfwb_op <=  `OR1200_RFWBOP_NOP;
1028 10 unneback
 
1029 141 marcus.erl
 
1030 10 unneback
                endcase
1031
        end
1032
end
1033
 
1034
//
1035 141 marcus.erl
// Decode of id_branch_op
1036 10 unneback
//
1037
always @(posedge clk or posedge rst) begin
1038
        if (rst)
1039 258 julius
                id_branch_op <=  `OR1200_BRANCHOP_NOP;
1040 141 marcus.erl
        else if (id_flushpipe)
1041 258 julius
                id_branch_op <=  `OR1200_BRANCHOP_NOP;
1042 10 unneback
        else if (!id_freeze) begin
1043
                case (if_insn[31:26])           // synopsys parallel_case
1044 141 marcus.erl
 
1045
                // l.j
1046
                `OR1200_OR32_J:
1047 258 julius
                        id_branch_op <=  `OR1200_BRANCHOP_J;
1048 10 unneback
 
1049 141 marcus.erl
                // j.jal
1050
                `OR1200_OR32_JAL:
1051 258 julius
                        id_branch_op <=  `OR1200_BRANCHOP_J;
1052 10 unneback
 
1053 141 marcus.erl
                // j.jalr
1054
                `OR1200_OR32_JALR:
1055 258 julius
                        id_branch_op <=  `OR1200_BRANCHOP_JR;
1056 10 unneback
 
1057 141 marcus.erl
                // l.jr
1058
                `OR1200_OR32_JR:
1059 258 julius
                        id_branch_op <=  `OR1200_BRANCHOP_JR;
1060 10 unneback
 
1061 141 marcus.erl
                // l.bnf
1062
                `OR1200_OR32_BNF:
1063 258 julius
                        id_branch_op <=  `OR1200_BRANCHOP_BNF;
1064 10 unneback
 
1065 141 marcus.erl
                // l.bf
1066
                `OR1200_OR32_BF:
1067 258 julius
                        id_branch_op <=  `OR1200_BRANCHOP_BF;
1068 10 unneback
 
1069 141 marcus.erl
                // l.rfe
1070
                `OR1200_OR32_RFE:
1071 258 julius
                        id_branch_op <=  `OR1200_BRANCHOP_RFE;
1072 10 unneback
 
1073 141 marcus.erl
                // Non branch instructions
1074
                default:
1075 258 julius
                        id_branch_op <=  `OR1200_BRANCHOP_NOP;
1076 141 marcus.erl
 
1077 10 unneback
                endcase
1078
        end
1079
end
1080
 
1081
//
1082 141 marcus.erl
// Generation of ex_branch_op
1083 10 unneback
//
1084
always @(posedge clk or posedge rst)
1085
        if (rst)
1086 258 julius
                ex_branch_op <=  `OR1200_BRANCHOP_NOP;
1087 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1088 258 julius
                ex_branch_op <=  `OR1200_BRANCHOP_NOP;
1089 10 unneback
        else if (!ex_freeze)
1090 258 julius
                ex_branch_op <=  id_branch_op;
1091 10 unneback
 
1092
//
1093 141 marcus.erl
// Decode of id_lsu_op
1094 10 unneback
//
1095 141 marcus.erl
always @(id_insn) begin
1096
        case (id_insn[31:26])           // synopsys parallel_case
1097
 
1098
        // l.lwz
1099
        `OR1200_OR32_LWZ:
1100 353 julius
                id_lsu_op =  `OR1200_LSUOP_LWZ;
1101 141 marcus.erl
 
1102
        // l.lbz
1103
        `OR1200_OR32_LBZ:
1104 353 julius
                id_lsu_op =  `OR1200_LSUOP_LBZ;
1105 141 marcus.erl
 
1106
        // l.lbs
1107
        `OR1200_OR32_LBS:
1108 353 julius
                id_lsu_op =  `OR1200_LSUOP_LBS;
1109 141 marcus.erl
 
1110
        // l.lhz
1111
        `OR1200_OR32_LHZ:
1112 353 julius
                id_lsu_op =  `OR1200_LSUOP_LHZ;
1113 141 marcus.erl
 
1114
        // l.lhs
1115
        `OR1200_OR32_LHS:
1116 353 julius
                id_lsu_op =  `OR1200_LSUOP_LHS;
1117 141 marcus.erl
 
1118
        // l.sw
1119
        `OR1200_OR32_SW:
1120 353 julius
                id_lsu_op =  `OR1200_LSUOP_SW;
1121 141 marcus.erl
 
1122
        // l.sb
1123
        `OR1200_OR32_SB:
1124 353 julius
                id_lsu_op =  `OR1200_LSUOP_SB;
1125 141 marcus.erl
 
1126
        // l.sh
1127
        `OR1200_OR32_SH:
1128 353 julius
                id_lsu_op =  `OR1200_LSUOP_SH;
1129 141 marcus.erl
 
1130
        // Non load/store instructions
1131
        default:
1132 353 julius
                id_lsu_op =  `OR1200_LSUOP_NOP;
1133 141 marcus.erl
 
1134
        endcase
1135 10 unneback
end
1136
 
1137
//
1138
// Decode of comp_op
1139
//
1140
always @(posedge clk or posedge rst) begin
1141
        if (rst) begin
1142 258 julius
                comp_op <=  4'd0;
1143 141 marcus.erl
        end else if (!ex_freeze & id_freeze | ex_flushpipe)
1144 258 julius
                comp_op <=  4'd0;
1145 10 unneback
        else if (!ex_freeze)
1146 258 julius
                comp_op <=  id_insn[24:21];
1147 10 unneback
end
1148
 
1149 185 julius
`ifdef OR1200_FPU_IMPLEMENTED
1150 10 unneback
//
1151 185 julius
// Decode of FPU ops
1152
//
1153 258 julius
   assign fpu_op = {(id_insn[31:26] == `OR1200_OR32_FLOAT),
1154
                    id_insn[`OR1200_FPUOP_WIDTH-2:0]};
1155 185 julius
`else
1156
   assign fpu_op = {`OR1200_FPUOP_WIDTH{1'b0}};
1157
`endif
1158
 
1159
 
1160
//
1161 10 unneback
// Decode of l.sys
1162
//
1163
always @(posedge clk or posedge rst) begin
1164
        if (rst)
1165 258 julius
                sig_syscall <=  1'b0;
1166 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1167 258 julius
                sig_syscall <=  1'b0;
1168 10 unneback
        else if (!ex_freeze) begin
1169
`ifdef OR1200_VERBOSE
1170
// synopsys translate_off
1171
                if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
1172
                        $display("Generating sig_syscall");
1173
// synopsys translate_on
1174
`endif
1175 258 julius
                sig_syscall <=  (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
1176 10 unneback
        end
1177
end
1178
 
1179
//
1180
// Decode of l.trap
1181
//
1182
always @(posedge clk or posedge rst) begin
1183
        if (rst)
1184 258 julius
                sig_trap <=  1'b0;
1185 141 marcus.erl
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1186 258 julius
                sig_trap <=  1'b0;
1187 10 unneback
        else if (!ex_freeze) begin
1188
`ifdef OR1200_VERBOSE
1189
// synopsys translate_off
1190
                if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
1191
                        $display("Generating sig_trap");
1192
// synopsys translate_on
1193
`endif
1194 258 julius
                sig_trap <=  (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
1195 10 unneback
                        | du_hwbkpt;
1196
        end
1197
end
1198
 
1199 258 julius
// Decode destination register address for data cache to check if store ops
1200
// are being done from the stack register (r1) or frame pointer register (r2)
1201
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
1202
always @(posedge clk or posedge rst) begin
1203
   if (rst)
1204
     dc_no_writethrough <= 0;
1205
   else if (!ex_freeze)
1206
     dc_no_writethrough <= (id_insn[20:16] == 5'd1) | (id_insn[20:16] == 5'd2);
1207
end
1208
`else
1209
 
1210
   assign dc_no_writethrough = 0;
1211
 
1212
`endif
1213
 
1214 10 unneback
endmodule

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