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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_fsm.v] - Blame information for rev 846

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's DC FSM                                             ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 258 julius
////  http://opencores.org/project,or1k                           ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Data cache state machine                                    ////
10
////                                                              ////
11
////  To Do:                                                      ////
12 258 julius
////   - Test error during line read or write                     ////
13 10 unneback
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16 258 julius
////      - Julius Baxter, julius@opencores.org                   ////
17 10 unneback
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20 258 julius
//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG           ////
21 10 unneback
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45 141 marcus.erl
// $Log: or1200_dc_fsm.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Minor update: 
48
// Bugs fixed. 
49
//
50 10 unneback
 
51
// synopsys translate_off
52
`include "timescale.v"
53
// synopsys translate_on
54
`include "or1200_defines.v"
55
 
56
`define OR1200_DCFSM_IDLE       3'd0
57 258 julius
`define OR1200_DCFSM_CLOADSTORE 3'd1
58
`define OR1200_DCFSM_LOOP2      3'd2
59
`define OR1200_DCFSM_LOOP3      3'd3
60
`define OR1200_DCFSM_LOOP4      3'd4
61
`define OR1200_DCFSM_FLUSH5     3'd5
62
`define OR1200_DCFSM_INV6       3'd6
63
`define OR1200_DCFSM_WAITSPRCS7 3'd7
64 10 unneback
 
65 258 julius
 
66
 
67 10 unneback
//
68
// Data cache FSM for cache line of 16 bytes (4x singleword)
69
//
70
 
71 258 julius
module or1200_dc_fsm
72
  (
73
   // Clock and reset
74
   clk, rst,
75
 
76
   // Internal i/f to top level DC
77
   dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
78
   tagcomp_miss, biudata_valid, biudata_error, lsu_addr,
79
   dcram_we, biu_read, biu_write, biu_do_sel, dcram_di_sel, first_hit_ack,
80
   first_miss_ack, first_miss_err, burst, tag_we, tag_valid, dc_addr,
81
   dc_no_writethrough, tag_dirty, dirty, tag, tag_v, dc_block_flush,
82
   dc_block_writeback, spr_dat_i, mtspr_dc_done, spr_cswe
83
   );
84 10 unneback
 
85 258 julius
   //
86
   // I/O
87
   //
88
   input                                clk;
89
   input                                rst;
90
   input                                dc_en;
91
   input                                dcqmem_cycstb_i;
92
   input                                dcqmem_ci_i;
93
   input                                dcqmem_we_i;
94
   input [3:0]                           dcqmem_sel_i;
95
   input                                tagcomp_miss;
96
   input                                biudata_valid;
97
   input                                biudata_error;
98
   input [31:0]                  lsu_addr;
99
   output [3:0]                  dcram_we;
100
   output                               biu_read;
101
   output                               biu_write;
102
   output                               dcram_di_sel;
103
   output                               biu_do_sel;
104
   output                               first_hit_ack;
105
   output                               first_miss_ack;
106
   output                               first_miss_err;
107
   output                               burst;
108
   output                               tag_we;
109
   output                               tag_valid;
110
   output [31:0]                         dc_addr;
111
   input                                dc_no_writethrough;
112
   output                               tag_dirty;
113
   input                                dirty;
114
   input [`OR1200_DCTAG_W-2:0]           tag;
115
   input                                tag_v;
116
   input                                dc_block_flush;
117
   input                                dc_block_writeback;
118
   input [31:0]                  spr_dat_i;
119
   output                               mtspr_dc_done;
120
   input                                spr_cswe;
121
 
122
 
123
   //
124
   // Internal wires and regs
125
   //
126
   reg [31:0]                            addr_r;
127
   reg [2:0]                             state;
128 481 julius
   reg [`OR1200_DCLS-1:0]                cnt;
129 258 julius
   reg                                  hitmiss_eval;
130
   reg                                  store;
131
   reg                                  load;
132
   reg                                  cache_inhibit;
133
   reg                                  cache_miss;
134
   reg                                  cache_dirty_needs_writeback;
135
   reg                                  did_early_load_ack;
136
   reg                                  cache_spr_block_flush;
137
   reg                                  cache_spr_block_writeback;
138
   reg                                  cache_wb;
139
   wire                                 load_hit_ack;
140
   wire                                 load_miss_ack;
141
   wire                                 load_inhibit_ack;
142
   wire                                 store_hit_ack;
143
   wire                                 store_hit_writethrough_ack;
144
   wire                                 store_miss_writethrough_ack;
145
   wire                                 store_inhibit_ack;
146
   wire                                 store_miss_ack;
147
   wire                                 dcram_we_after_line_load;
148
   wire                                 dcram_we_during_line_load;
149
   wire                                 tagram_we_end_of_loadstore_loop;
150
   wire                                 tagram_dirty_bit_set;
151
   wire                                 writethrough;
152
   wire                                 cache_inhibit_with_eval;
153 481 julius
   wire [(`OR1200_DCLS-1)-2:0]           next_addr_word;
154 10 unneback
 
155 258 julius
   //
156
   // Cache inhibit
157
   //
158
 
159
   // Indicates whether cache is inhibited, during hitmiss_eval and after
160
   assign cache_inhibit_with_eval = (hitmiss_eval & dcqmem_ci_i) |
161
                                    (!hitmiss_eval & cache_inhibit);
162
 
163
   //
164
   // Generate of DCRAM write enables
165
   //
166 10 unneback
 
167 258 julius
   // WE when non-writethrough, and had to wait for a line to load.
168
   assign dcram_we_after_line_load = (state == `OR1200_DCFSM_LOOP3) &
169
                                    dcqmem_we_i & !cache_dirty_needs_writeback &
170
                                     !did_early_load_ack;
171 10 unneback
 
172 258 julius
   // WE when receiving the data cache line
173
   assign dcram_we_during_line_load = (state == `OR1200_DCFSM_LOOP2) & load &
174
                                      biudata_valid;
175
 
176
   assign dcram_we =(// Write when hit - make sure it is only when hit - could
177
                     // maybe be doing write through and don't want to corrupt
178
                     // cache lines corresponding to the writethrough addr_r.
179
                     ({4{store_hit_ack | store_hit_writethrough_ack}} |
180
                     // Write after load of line
181
                     {4{dcram_we_after_line_load}}) &
182
                     dcqmem_sel_i                ) |
183
                    // Write during load
184
                    {4{dcram_we_during_line_load}};
185 10 unneback
 
186 258 julius
   //
187
   // Tag RAM signals
188
   //
189
 
190
   // WE to tag RAM when we finish loading a line.
191
   assign tagram_we_end_of_loadstore_loop = ((state==`OR1200_DCFSM_LOOP2) &
192
                                             biudata_valid & !(|cnt));
193
 
194
`ifndef OR1200_DC_WRITETHROUGH
195
   // No writethrough, so mark a line dirty whenever we write to it
196
   assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
197 10 unneback
 
198 258 julius
   // Generate done signal for MTSPR instructions that may block execution
199
   assign mtspr_dc_done = // Either DC disabled or we're not selected, or
200
                          !dc_en | !spr_cswe |
201
                          // Requested address not valid or writeback and !dirty
202
                          ((state==`OR1200_DCFSM_FLUSH5) &
203
                           (!tag_v | (cache_spr_block_writeback & !dirty))) |
204
                          // Writeback or flush is finished
205
                          ((state==`OR1200_DCFSM_LOOP3) &
206
                           (cache_spr_block_flush | cache_spr_block_writeback))|
207
                          // Invalidate of clean line finished
208
                          ((state==`OR1200_DCFSM_INV6) & cache_spr_block_flush);
209
 
210
 
211
`else
212
 `ifdef OR1200_DC_NOSTACKWRITETHROUGH
213
   // For dirty bit setting when having writethrough but not for stack
214
   assign tagram_dirty_bit_set = store_hit_ack | store_miss_ack;
215
 `else
216
   // Lines will never be dirty if always writethrough
217
   assign tagram_dirty_bit_set = 0;
218
 `endif
219
 
220
   assign mtspr_dc_done = 1'b1;
221
 
222
`endif
223 10 unneback
 
224 258 julius
   assign tag_dirty = tagram_dirty_bit_set;
225
 
226
   // WE to tag RAM
227
   assign tag_we = tagram_we_end_of_loadstore_loop |
228
                    tagram_dirty_bit_set | (state == `OR1200_DCFSM_INV6);
229
 
230 10 unneback
 
231 258 julius
   // Valid bit
232
   // Set valid when end of line load, or marking dirty (is still valid)
233
   assign tag_valid = ( tagram_we_end_of_loadstore_loop &
234
                        (load | (store & cache_spr_block_writeback)) ) |
235
                      tagram_dirty_bit_set;
236 10 unneback
 
237 258 julius
 
238
 
239
   //
240
   // BIU read and write
241
   //
242
 
243
   assign biu_read = // Bus read request when:
244
                     // 1) Have a miss and not dirty or a load with inhibit
245
                     ((state == `OR1200_DCFSM_CLOADSTORE) &
246
                      (((hitmiss_eval & tagcomp_miss & !dirty &
247
                         !(store & writethrough)) |
248
                        (load & cache_inhibit_with_eval)) & dcqmem_cycstb_i)) |
249
                     // 2) In the loop and loading
250
                     ((state == `OR1200_DCFSM_LOOP2) & load);
251
 
252
 
253
   assign biu_write = // Bus write request when:
254
                      // 1) Have a miss and dirty or store with inhibit
255
                      ((state == `OR1200_DCFSM_CLOADSTORE) &
256
                       (((hitmiss_eval & tagcomp_miss & dirty) |
257
                         (store & writethrough)) |
258
                        (store & cache_inhibit_with_eval)) & dcqmem_cycstb_i) |
259
                      // 2) In the loop and storing
260
                      ((state == `OR1200_DCFSM_LOOP2) & store);
261
 
262
   //
263
   // Select for data to actual cache RAM (from LSU or BIU)
264
   //
265
   // Data to DCRAM - from external bus when loading (from IU when store)
266
   assign dcram_di_sel = load;
267
   // Data to external bus - always from IU except in case of bursting back
268
   //                        the line to memory. (1 selects DCRAM)
269
   assign biu_do_sel = (state == `OR1200_DCFSM_LOOP2) & store;
270
 
271 481 julius
   // 3-bit wire for calculating next word of burst write, depending on
272
   // line size of data cache.
273
   assign next_addr_word =  addr_r[`OR1200_DCLS-1:2] + 1;
274 258 julius
 
275
   // Address to cache RAM (tag address also derived from this)   
276
   assign dc_addr =
277
                   // First check if we've got a block flush or WB op
278
                   ((dc_block_flush & !cache_spr_block_flush) |
279
                   (dc_block_writeback & !cache_spr_block_writeback)) ?
280
                   spr_dat_i :
281
                   (state==`OR1200_DCFSM_FLUSH5) ? addr_r:
282
                    // If no SPR action, then always put out address from LSU
283
                    (state==`OR1200_DCFSM_IDLE | hitmiss_eval) ? lsu_addr :
284
                    // Next, if in writeback loop, when ACKed must immediately
285
                    // output next word address (the RAM address takes a cycle
286
                    // to increment, but it's needed immediately for burst)
287
                    // otherwise, output our registered address.
288
                    (state==`OR1200_DCFSM_LOOP2 & biudata_valid & store ) ?
289 481 julius
                    {addr_r[31:`OR1200_DCLS], next_addr_word, 2'b00} : addr_r;
290 258 julius
 
291
`ifdef OR1200_DC_WRITETHROUGH
292
 `ifdef OR1200_DC_NOSTACKWRITETHROUGH
293
   assign writethrough = !dc_no_writethrough;
294
 `else
295
   assign writethrough = 1;
296
 `endif
297
`else
298
   assign writethrough = 0;
299
`endif
300
 
301
   //
302
   // ACK generation for LSU
303
   //
304
 
305
   // ACK for when it's a cache hit
306
   assign first_hit_ack = load_hit_ack | store_hit_ack |
307
                          store_hit_writethrough_ack |
308
                          store_miss_writethrough_ack |
309
                          store_inhibit_ack | store_miss_ack ;
310
 
311
   // ACK for when it's a cache miss - load only, is used in MUX for data back
312
   //                                  LSU straight off external data bus. In
313
   //                                  this was is also used for cache inhibit
314
   //                                  loads.
315 846 stekern
   // first_hit_ack takes precedence over first_miss_ack
316
   assign first_miss_ack = ~first_hit_ack & (load_miss_ack | load_inhibit_ack);
317 258 julius
 
318
   // ACK cache hit on load
319
   assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
320
                         hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i & load;
321
 
322
   // ACK cache hit on store, no writethrough
323
   assign store_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
324
                          hitmiss_eval  & !tagcomp_miss & !dcqmem_ci_i &
325
                          store & !writethrough;
326
 
327
   // ACK cache hit on store with writethrough
328
   assign store_hit_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
329
                                       !cache_miss & !cache_inhibit &
330
                                       store & writethrough & biudata_valid;
331
 
332
   // ACK cache miss on store with writethrough
333
   assign store_miss_writethrough_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
334
                                        cache_miss & !cache_inhibit &
335
                                        store & writethrough & biudata_valid;
336
 
337
   // ACK store when cacheinhibit
338
   assign store_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
339
                              store & cache_inhibit & biudata_valid;
340
 
341
 
342
   // Get the _early_ ack on first ACK back from wishbone during load only
343
   // Condition is that we're in the loop - that it's the first ack we get (can
344
   // tell from value of cnt), and we're loading a line to read from it (not
345
   // loading to write to it, in the case of a write without writethrough.)
346
   assign load_miss_ack =  ((state== `OR1200_DCFSM_LOOP2) & load &
347 481 julius
                            (cnt==((1 << `OR1200_DCLS) - 4)) & biudata_valid &
348 258 julius
                            !(dcqmem_we_i & !writethrough));
349 481 julius
 
350 258 julius
   assign load_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
351
                             load & cache_inhibit & biudata_valid;
352
 
353
   // This will be case of write through disabled, and had to load a line.
354
   assign store_miss_ack = dcram_we_after_line_load;
355
 
356
   assign first_miss_err = biudata_error & dcqmem_cycstb_i;
357
 
358
   // Signal burst when in the load/store loop. We will always try to burst.
359
   assign burst = (state == `OR1200_DCFSM_LOOP2);
360
 
361
   //
362
   // Main DC FSM
363
   //
364 358 julius
   always @(posedge clk or `OR1200_RST_EVENT rst) begin
365
      if (rst == `OR1200_RST_VALUE) begin
366 258 julius
         state <=  `OR1200_DCFSM_IDLE;
367 481 julius
         addr_r <=  32'd0;
368 258 julius
         hitmiss_eval <=  1'b0;
369
         store <=  1'b0;
370
         load <=  1'b0;
371 481 julius
         cnt <=  `OR1200_DCLS'd0;
372 258 julius
         cache_miss <=  1'b0;
373
         cache_dirty_needs_writeback <= 1'b0;
374
         cache_inhibit <=  1'b0;
375
         did_early_load_ack <= 1'b0;
376
         cache_spr_block_flush <= 1'b0;
377
         cache_spr_block_writeback <= 1'b0;
378
      end
379
      else
380 10 unneback
        case (state)    // synopsys parallel_case
381 258 julius
 
382
          `OR1200_DCFSM_IDLE : begin
383
             if (dc_en & (dc_block_flush | dc_block_writeback))
384
               begin
385
                  cache_spr_block_flush <= dc_block_flush;
386
                  cache_spr_block_writeback <= dc_block_writeback;
387
                  hitmiss_eval <= 1'b1;
388
                  state <= `OR1200_DCFSM_FLUSH5;
389
                  addr_r <=  spr_dat_i;
390
               end
391
             else if (dc_en & dcqmem_cycstb_i)
392
               begin
393
                  state <= `OR1200_DCFSM_CLOADSTORE;
394
                  hitmiss_eval <=  1'b1;
395
                  store <=  dcqmem_we_i;
396
                  load <=  !dcqmem_we_i;
397
               end
398
 
399
 
400
          end // case: `OR1200_DCFSM_IDLE
401
 
402
          `OR1200_DCFSM_CLOADSTORE: begin
403
             hitmiss_eval <=  1'b0;
404
             if (hitmiss_eval) begin
405
                cache_inhibit <=  dcqmem_ci_i; // Check for cache inhibit here
406
                cache_miss <=  tagcomp_miss;
407
                cache_dirty_needs_writeback <= dirty;
408
                addr_r <=  lsu_addr;
409
             end
410
 
411
             // Evaluate any cache line load/stores in first cycle:
412
                             //
413
             if (hitmiss_eval & tagcomp_miss & !(store & writethrough) &
414
                 !dcqmem_ci_i)
415
               begin
416
                  // Miss - first either:
417
                  //  1) write back dirty line 
418
                  if (dirty) begin
419
                     // Address for writeback
420
                     addr_r <=  {tag, lsu_addr[`OR1200_DCINDXH:2],2'd0};
421
                     load <= 1'b0;
422
                     store <= 1'b1;
423
`ifdef OR1200_VERBOSE
424
                     $display("%t: dcache miss and dirty", $time);
425 10 unneback
`endif
426 258 julius
                  end
427
                  //  2) load requested line
428
                  else begin
429
                     addr_r <=  lsu_addr;
430
                     load <= 1'b1;
431
                     store <= 1'b0;
432
                  end // else: !if(dirty)
433
                  state <= `OR1200_DCFSM_LOOP2;
434
                  // Set the counter for the burst accesses
435 481 julius
                  cnt <=  ((1 << `OR1200_DCLS) - 4);
436 258 julius
               end
437
             else if (// Strobe goes low
438
                      !dcqmem_cycstb_i |
439
                      // Cycle finishes
440
                      (!hitmiss_eval & (biudata_valid | biudata_error)) |
441
                      // Cache hit in first cycle....
442
                      (hitmiss_eval & !tagcomp_miss & !dcqmem_ci_i &
443
                      // .. and you're not doing a writethrough store..
444
                      !(store & writethrough))) begin
445
                state <=  `OR1200_DCFSM_IDLE;
446
                load <=  1'b0;
447
                store <= 1'b0;
448
                cache_inhibit <= 1'b0;
449
                cache_dirty_needs_writeback <= 1'b0;
450
             end
451
          end // case: `OR1200_DCFSM_CLOADSTORE   
452
 
453
          `OR1200_DCFSM_LOOP2 : begin // loop/abort          
454
             if (!dc_en| biudata_error) begin
455
                state <=  `OR1200_DCFSM_IDLE;
456
                load <=  1'b0;
457
                store <= 1'b0;
458 481 julius
                cnt <= `OR1200_DCLS'd0;
459 258 julius
             end
460
             if (biudata_valid & (|cnt)) begin
461 481 julius
                cnt <=  cnt - 4;
462
                addr_r[`OR1200_DCLS-1:2] <=  addr_r[`OR1200_DCLS-1:2] + 1;
463 258 julius
             end
464
             else if (biudata_valid & !(|cnt)) begin
465
                state <= `OR1200_DCFSM_LOOP3;
466
                addr_r <=  lsu_addr;
467
                load <= 1'b0;
468
                store <= 1'b0;
469
             end
470
 
471
             // Track if we did an early ack during a load
472
             if (load_miss_ack)
473
               did_early_load_ack <= 1'b1;
474
 
475
 
476
          end // case: `OR1200_DCFSM_LOOP2
477
 
478
          `OR1200_DCFSM_LOOP3: begin // figure out next step
479
             if (cache_dirty_needs_writeback) begin
480
                // Just did store of the dirty line so now load new one
481
                load <= 1'b1;
482
                // Set the counter for the burst accesses
483 481 julius
                cnt <=  ((1 << `OR1200_DCLS) - 4);
484 258 julius
                // Address of line to be loaded
485
                addr_r <=  lsu_addr;
486
                cache_dirty_needs_writeback <= 1'b0;
487
                state <= `OR1200_DCFSM_LOOP2;
488
             end // if (cache_dirty_needs_writeback)
489
             else if (cache_spr_block_flush | cache_spr_block_writeback) begin
490
                // Just wrote back the line to memory, we're finished.
491
                cache_spr_block_flush <= 1'b0;
492
                cache_spr_block_writeback <= 1'b0;
493
                state <= `OR1200_DCFSM_WAITSPRCS7;
494
             end
495
             else begin
496
                // Just loaded a new line, finish up
497
                did_early_load_ack <= 1'b0;
498
                state <= `OR1200_DCFSM_LOOP4;
499
             end
500
          end // case: `OR1200_DCFSM_LOOP3
501
 
502
          `OR1200_DCFSM_LOOP4: begin
503
             state <=  `OR1200_DCFSM_IDLE;
504
          end
505
 
506
          `OR1200_DCFSM_FLUSH5: begin
507
             hitmiss_eval <= 1'b0;
508
             if (hitmiss_eval & !tag_v)
509
               begin
510
                  // Not even cached, just ignore
511
                  cache_spr_block_flush <= 1'b0;
512
                  cache_spr_block_writeback <= 1'b0;
513
                  state <=  `OR1200_DCFSM_WAITSPRCS7;
514
               end
515
             else if (hitmiss_eval & tag_v)
516
               begin
517
                  // Tag is valid - what do we do?
518
                  if ((cache_spr_block_flush | cache_spr_block_writeback) &
519
                      dirty) begin
520
                     // Need to writeback
521
                     // Address for writeback (spr_dat_i has already changed so
522
                     // use line number from addr_r)
523
                     addr_r <=  {tag, addr_r[`OR1200_DCINDXH:2],2'd0};
524
                     load <= 1'b0;
525
                     store <= 1'b1;
526
`ifdef OR1200_VERBOSE
527
                     $display("%t: block flush: dirty block", $time);
528 10 unneback
`endif
529 258 julius
                     state <= `OR1200_DCFSM_LOOP2;
530
                     // Set the counter for the burst accesses
531 481 julius
                     cnt <=  ((1 << `OR1200_DCLS) - 4);
532 258 julius
                  end
533
                  else if (cache_spr_block_flush & !dirty)
534
                    begin
535
                       // Line not dirty, just need to invalidate
536
                       state <=  `OR1200_DCFSM_INV6;
537
                    end // else: !if(dirty)
538
                  else if (cache_spr_block_writeback & !dirty)
539
                    begin
540
                       // Nothing to do - line is valid but not dirty
541
                       cache_spr_block_writeback <= 1'b0;
542
                       state <=  `OR1200_DCFSM_WAITSPRCS7;
543
                    end
544
          end // if (hitmiss_eval & tag_v)
545
          end
546
          `OR1200_DCFSM_INV6: begin
547
             cache_spr_block_flush <= 1'b0;
548
             // Wait until SPR CS goes low before going back to idle
549
             if (!spr_cswe)
550
               state <=  `OR1200_DCFSM_IDLE;
551
          end
552
          `OR1200_DCFSM_WAITSPRCS7: begin
553
             // Wait until SPR CS goes low before going back to idle
554
             if (!spr_cswe)
555
               state <=  `OR1200_DCFSM_IDLE;
556
          end
557 141 marcus.erl
 
558 258 julius
        endcase // case (state)
559
 
560 358 julius
   end // always @ (posedge clk or `OR1200_RST_EVENT rst)
561 258 julius
 
562 10 unneback
 
563
endmodule

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