| 1 |
10 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// OR1200's DC TAG RAMs ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// This file is part of the OpenRISC 1200 project ////
|
| 6 |
|
|
//// http://www.opencores.org/cores/or1k/ ////
|
| 7 |
|
|
//// ////
|
| 8 |
|
|
//// Description ////
|
| 9 |
|
|
//// Instatiation of data cache tag rams. ////
|
| 10 |
|
|
//// ////
|
| 11 |
|
|
//// To Do: ////
|
| 12 |
|
|
//// - make it smaller and faster ////
|
| 13 |
|
|
//// ////
|
| 14 |
|
|
//// Author(s): ////
|
| 15 |
|
|
//// - Damjan Lampret, lampret@opencores.org ////
|
| 16 |
|
|
//// ////
|
| 17 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 18 |
|
|
//// ////
|
| 19 |
|
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
| 20 |
|
|
//// ////
|
| 21 |
|
|
//// This source file may be used and distributed without ////
|
| 22 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 23 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 24 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 25 |
|
|
//// ////
|
| 26 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 27 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 28 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 29 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 30 |
|
|
//// later version. ////
|
| 31 |
|
|
//// ////
|
| 32 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 33 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 34 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 35 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 36 |
|
|
//// details. ////
|
| 37 |
|
|
//// ////
|
| 38 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 39 |
|
|
//// Public License along with this source; if not, download it ////
|
| 40 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 41 |
|
|
//// ////
|
| 42 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 43 |
|
|
//
|
| 44 |
|
|
// CVS Revision History
|
| 45 |
|
|
//
|
| 46 |
|
|
// $Log: not supported by cvs2svn $
|
| 47 |
|
|
// Revision 1.4 2004/04/05 08:29:57 lampret
|
| 48 |
|
|
// Merged branch_qmem into main tree.
|
| 49 |
|
|
//
|
| 50 |
|
|
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
|
| 51 |
|
|
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
|
| 52 |
|
|
//
|
| 53 |
|
|
// Revision 1.2 2002/10/17 20:04:40 lampret
|
| 54 |
|
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
| 55 |
|
|
//
|
| 56 |
|
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
| 57 |
|
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
| 58 |
|
|
//
|
| 59 |
|
|
// Revision 1.8 2001/10/21 17:57:16 lampret
|
| 60 |
|
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
|
| 61 |
|
|
//
|
| 62 |
|
|
// Revision 1.7 2001/10/14 13:12:09 lampret
|
| 63 |
|
|
// MP3 version.
|
| 64 |
|
|
//
|
| 65 |
|
|
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
|
| 66 |
|
|
// no message
|
| 67 |
|
|
//
|
| 68 |
|
|
// Revision 1.2 2001/08/09 13:39:33 lampret
|
| 69 |
|
|
// Major clean-up.
|
| 70 |
|
|
//
|
| 71 |
|
|
// Revision 1.1 2001/07/20 00:46:03 lampret
|
| 72 |
|
|
// Development version of RTL. Libraries are missing.
|
| 73 |
|
|
//
|
| 74 |
|
|
//
|
| 75 |
|
|
|
| 76 |
|
|
// synopsys translate_off
|
| 77 |
|
|
`include "timescale.v"
|
| 78 |
|
|
// synopsys translate_on
|
| 79 |
|
|
`include "or1200_defines.v"
|
| 80 |
|
|
|
| 81 |
|
|
module or1200_dc_tag(
|
| 82 |
|
|
// Clock and reset
|
| 83 |
|
|
clk, rst,
|
| 84 |
|
|
|
| 85 |
|
|
`ifdef OR1200_BIST
|
| 86 |
|
|
// RAM BIST
|
| 87 |
|
|
mbist_si_i, mbist_so_o, mbist_ctrl_i,
|
| 88 |
|
|
`endif
|
| 89 |
|
|
|
| 90 |
|
|
// Internal i/f
|
| 91 |
|
|
addr, en, we, datain, tag_v, tag
|
| 92 |
|
|
);
|
| 93 |
|
|
|
| 94 |
|
|
parameter dw = `OR1200_DCTAG_W;
|
| 95 |
|
|
parameter aw = `OR1200_DCTAG;
|
| 96 |
|
|
|
| 97 |
|
|
//
|
| 98 |
|
|
// I/O
|
| 99 |
|
|
//
|
| 100 |
|
|
input clk;
|
| 101 |
|
|
input rst;
|
| 102 |
|
|
input [aw-1:0] addr;
|
| 103 |
|
|
input en;
|
| 104 |
|
|
input we;
|
| 105 |
|
|
input [dw-1:0] datain;
|
| 106 |
|
|
output tag_v;
|
| 107 |
|
|
output [dw-2:0] tag;
|
| 108 |
|
|
|
| 109 |
|
|
`ifdef OR1200_BIST
|
| 110 |
|
|
//
|
| 111 |
|
|
// RAM BIST
|
| 112 |
|
|
//
|
| 113 |
|
|
input mbist_si_i;
|
| 114 |
|
|
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
|
| 115 |
|
|
output mbist_so_o;
|
| 116 |
|
|
`endif
|
| 117 |
|
|
|
| 118 |
|
|
`ifdef OR1200_NO_DC
|
| 119 |
|
|
|
| 120 |
|
|
//
|
| 121 |
|
|
// Data cache not implemented
|
| 122 |
|
|
//
|
| 123 |
|
|
assign tag = {dw-1{1'b0}};
|
| 124 |
|
|
assign tag_v = 1'b0;
|
| 125 |
|
|
`ifdef OR1200_BIST
|
| 126 |
|
|
assign mbist_so_o = mbist_si_i;
|
| 127 |
|
|
`endif
|
| 128 |
|
|
|
| 129 |
|
|
`else
|
| 130 |
|
|
|
| 131 |
|
|
//
|
| 132 |
|
|
// Instantiation of TAG RAM block
|
| 133 |
|
|
//
|
| 134 |
|
|
`ifdef OR1200_DC_1W_4KB
|
| 135 |
|
|
or1200_spram_256x21 dc_tag0(
|
| 136 |
|
|
`endif
|
| 137 |
|
|
`ifdef OR1200_DC_1W_8KB
|
| 138 |
|
|
or1200_spram_512x20 dc_tag0(
|
| 139 |
|
|
`endif
|
| 140 |
|
|
`ifdef OR1200_BIST
|
| 141 |
|
|
// RAM BIST
|
| 142 |
|
|
.mbist_si_i(mbist_si_i),
|
| 143 |
|
|
.mbist_so_o(mbist_so_o),
|
| 144 |
|
|
.mbist_ctrl_i(mbist_ctrl_i),
|
| 145 |
|
|
`endif
|
| 146 |
|
|
.clk(clk),
|
| 147 |
|
|
.rst(rst),
|
| 148 |
|
|
.ce(en),
|
| 149 |
|
|
.we(we),
|
| 150 |
|
|
.oe(1'b1),
|
| 151 |
|
|
.addr(addr),
|
| 152 |
|
|
.di(datain),
|
| 153 |
|
|
.doq({tag, tag_v})
|
| 154 |
|
|
);
|
| 155 |
|
|
|
| 156 |
|
|
`endif
|
| 157 |
|
|
|
| 158 |
|
|
endmodule
|
