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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Blame information for rev 141

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1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Instruction MMU top level                          ////
4
////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of all IMMU blocks.                           ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - cache inhibit                                            ////
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////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
18
////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
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////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 141 marcus.erl
// $Log: or1200_immu_top.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Major update: 
49
// Structure reordered and bugs fixed. 
50
//
51
// Revision 1.15  2004/06/08 18:17:36  lampret
52
// Non-functional changes. Coding style fixes.
53
//
54 10 unneback
// Revision 1.14  2004/04/05 08:29:57  lampret
55
// Merged branch_qmem into main tree.
56
//
57
// Revision 1.12.4.2  2003/12/09 11:46:48  simons
58
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
59
//
60
// Revision 1.12.4.1  2003/07/08 15:36:37  lampret
61
// Added embedded memory QMEM.
62
//
63
// Revision 1.12  2003/06/06 02:54:47  lampret
64
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
65
//
66
// Revision 1.11  2002/10/17 20:04:40  lampret
67
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
68
//
69
// Revision 1.10  2002/09/16 03:08:56  lampret
70
// Disabled cache inhibit atttribute.
71
//
72
// Revision 1.9  2002/08/18 19:54:17  lampret
73
// Added store buffer.
74
//
75
// Revision 1.8  2002/08/14 06:23:50  lampret
76
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
77
//
78
// Revision 1.7  2002/08/12 05:31:30  lampret
79
// Delayed external access at page crossing.
80
//
81
// Revision 1.6  2002/03/29 15:16:56  lampret
82
// Some of the warnings fixed.
83
//
84
// Revision 1.5  2002/02/11 04:33:17  lampret
85
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
86
//
87
// Revision 1.4  2002/02/01 19:56:54  lampret
88
// Fixed combinational loops.
89
//
90
// Revision 1.3  2002/01/28 01:16:00  lampret
91
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
92
//
93
// Revision 1.2  2002/01/14 06:18:22  lampret
94
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
95
//
96
// Revision 1.1  2002/01/03 08:16:15  lampret
97
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
98
//
99
// Revision 1.6  2001/10/21 17:57:16  lampret
100
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
101
//
102
// Revision 1.5  2001/10/14 13:12:09  lampret
103
// MP3 version.
104
//
105
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
106
// no message
107
//
108
// Revision 1.1  2001/08/17 08:03:35  lampret
109
// *** empty log message ***
110
//
111
// Revision 1.2  2001/07/22 03:31:53  lampret
112
// Fixed RAM's oen bug. Cache bypass under development.
113
//
114
// Revision 1.1  2001/07/20 00:46:03  lampret
115
// Development version of RTL. Libraries are missing.
116
//
117
//
118
 
119
// synopsys translate_off
120
`include "timescale.v"
121
// synopsys translate_on
122
`include "or1200_defines.v"
123
 
124
//
125
// Insn MMU
126
//
127
 
128
module or1200_immu_top(
129
        // Rst and clk
130
        clk, rst,
131
 
132
        // CPU i/f
133
        ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
134
        icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
135
 
136 141 marcus.erl
        // SR Interface
137
        boot_adr_sel_i,
138
 
139 10 unneback
        // SPR access
140
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
141
 
142
`ifdef OR1200_BIST
143
        // RAM BIST
144
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
145
`endif
146
 
147
        // QMEM i/f
148
        qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
149
);
150
 
151
parameter dw = `OR1200_OPERAND_WIDTH;
152
parameter aw = `OR1200_OPERAND_WIDTH;
153
 
154
//
155
// I/O
156
//
157
 
158
//
159
// Clock and reset
160
//
161
input                           clk;
162
input                           rst;
163
 
164
//
165
// CPU I/F
166
//
167
input                           ic_en;
168
input                           immu_en;
169
input                           supv;
170
input   [aw-1:0]         icpu_adr_i;
171
input                           icpu_cycstb_i;
172
output  [aw-1:0]         icpu_adr_o;
173
output  [3:0]                    icpu_tag_o;
174
output                          icpu_rty_o;
175
output                          icpu_err_o;
176
 
177
//
178 141 marcus.erl
// SR Interface
179
//
180
input                           boot_adr_sel_i;
181
 
182
//
183 10 unneback
// SPR access
184
//
185
input                           spr_cs;
186
input                           spr_write;
187
input   [aw-1:0]         spr_addr;
188
input   [31:0]                   spr_dat_i;
189
output  [31:0]                   spr_dat_o;
190
 
191
`ifdef OR1200_BIST
192
//
193
// RAM BIST
194
//
195
input mbist_si_i;
196
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
197
output mbist_so_o;
198
`endif
199
 
200
//
201
// IC I/F
202
//
203
input                           qmemimmu_rty_i;
204
input                           qmemimmu_err_i;
205
input   [3:0]                    qmemimmu_tag_i;
206
output  [aw-1:0]         qmemimmu_adr_o;
207
output                          qmemimmu_cycstb_o;
208
output                          qmemimmu_ci_o;
209
 
210
//
211
// Internal wires and regs
212
//
213
wire                            itlb_spr_access;
214
wire    [31:`OR1200_IMMU_PS]    itlb_ppn;
215
wire                            itlb_hit;
216
wire                            itlb_uxe;
217
wire                            itlb_sxe;
218
wire    [31:0]                   itlb_dat_o;
219
wire                            itlb_en;
220
wire                            itlb_ci;
221
wire                            itlb_done;
222
wire                            fault;
223
wire                            miss;
224
wire                            page_cross;
225 141 marcus.erl
reg     [31:0]                   icpu_adr_default;
226
wire    [31:0]                   icpu_adr_boot;
227
reg                             icpu_adr_select;
228
reg             [31:0]           icpu_adr_o;
229 10 unneback
reg     [31:`OR1200_IMMU_PS]    icpu_vpn_r;
230
`ifdef OR1200_NO_IMMU
231
`else
232
reg                             itlb_en_r;
233 141 marcus.erl
reg                             dis_spr_access_frst_clk;
234
reg                             dis_spr_access_scnd_clk;
235 10 unneback
`endif
236
 
237
//
238
// Implemented bits inside match and translate registers
239
//
240
// itlbwYmrX: vpn 31-10  v 0
241
// itlbwYtrX: ppn 31-10  uxe 7  sxe 6
242
//
243
// itlb memory width:
244
// 19 bits for ppn
245
// 13 bits for vpn
246
// 1 bit for valid
247
// 2 bits for protection
248
// 1 bit for cache inhibit
249
 
250
//
251
// icpu_adr_o
252
//
253
`ifdef OR1200_REGISTERED_OUTPUTS
254
always @(posedge rst or posedge clk)
255 141 marcus.erl
        // default value 
256
        if (rst) begin
257
                icpu_adr_default <= #1 32'h0000_0100;
258
                icpu_adr_select  <= #1 1'b1;            // select async. value due to reset state
259
        end
260
        // selected value (different from default) is written into FF after reset state
261
        else if (icpu_adr_select) begin
262
                icpu_adr_default <= #1 icpu_adr_boot;   // dynamic value can only be assigned to FF out of reset! 
263
                icpu_adr_select  <= #1 1'b0;            // select FF value 
264
        end
265
        else begin
266
                icpu_adr_default <= #1 icpu_adr_i;
267
        end
268
 
269
// select async. value for boot address after reset - PC jumps to the address selected after boot! 
270
//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), 12'h100} ;
271
   assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
272
 
273
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
274
        if (icpu_adr_select)
275
                icpu_adr_o = icpu_adr_boot ;            // async. value is selected due to reset state 
276 10 unneback
        else
277 141 marcus.erl
                icpu_adr_o = icpu_adr_default ;         // FF value is selected 2nd clock after reset state 
278 10 unneback
`else
279
Unsupported !!!
280
`endif
281
 
282
//
283
// Page cross
284
//
285
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
286
//
287
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
288
 
289
//
290
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
291
// one clock cycle after offset part.
292
//
293
always @(posedge clk or posedge rst)
294
        if (rst)
295
                icpu_vpn_r <= #1 {32-`OR1200_IMMU_PS{1'b0}};
296
        else
297
                icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS];
298
 
299
`ifdef OR1200_NO_IMMU
300
 
301
//
302
// Put all outputs in inactive state
303
//
304
assign spr_dat_o = 32'h00000000;
305
assign qmemimmu_adr_o = icpu_adr_i;
306
assign icpu_tag_o = qmemimmu_tag_i;
307
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
308
assign icpu_rty_o = qmemimmu_rty_i;
309
assign icpu_err_o = qmemimmu_err_i;
310
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
311
`ifdef OR1200_BIST
312
assign mbist_so_o = mbist_si_i;
313
`endif
314
`else
315
 
316
//
317
// ITLB SPR access
318
//
319
// 1200 - 12FF  itlbmr w0
320
// 1200 - 123F  itlbmr w0 [63:0]
321
//
322
// 1300 - 13FF  itlbtr w0
323
// 1300 - 133F  itlbtr w0 [63:0]
324
//
325 141 marcus.erl
assign itlb_spr_access = spr_cs & ~dis_spr_access_scnd_clk;
326 10 unneback
 
327
//
328
// Disable ITLB SPR access
329
//
330 141 marcus.erl
// This flops are used to mask ITLB miss/fault exception
331
// during first & second clock cycles of accessing ITLB SPR. In
332 10 unneback
// subsequent clock cycles it is assumed that ITLB SPR
333
// access was accomplished and that normal instruction fetching
334
// can proceed.
335
//
336 141 marcus.erl
// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
337
// dis_spr_access_frst_clk  sets dis_spr_access_scnd_clk and 
338
// icpu_rty_o clears it.
339 10 unneback
//
340
always @(posedge clk or posedge rst)
341
        if (rst)
342 141 marcus.erl
                dis_spr_access_frst_clk  <= #1 1'b0;
343 10 unneback
        else if (!icpu_rty_o)
344 141 marcus.erl
                dis_spr_access_frst_clk  <= #1 1'b0;
345 10 unneback
        else if (spr_cs)
346 141 marcus.erl
                dis_spr_access_frst_clk  <= #1 1'b1;
347 10 unneback
 
348 141 marcus.erl
always @(posedge clk or posedge rst)
349
        if (rst)
350
                dis_spr_access_scnd_clk  <= #1 1'b0;
351
        else if (!icpu_rty_o)
352
                dis_spr_access_scnd_clk  <= #1 1'b0;
353
        else if (dis_spr_access_frst_clk)
354
                dis_spr_access_scnd_clk  <= #1 1'b1;
355
 
356 10 unneback
//
357
// Tags:
358
//
359 141 marcus.erl
// OR1200_ITAG_TE - TLB miss Exception
360
// OR1200_ITAG_PE - Page fault Exception
361 10 unneback
//
362 141 marcus.erl
assign icpu_tag_o = miss ? `OR1200_ITAG_TE : fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
363 10 unneback
 
364
//
365
// icpu_rty_o
366
//
367
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
368 141 marcus.erl
//assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
369
assign icpu_rty_o = qmemimmu_rty_i;
370 10 unneback
 
371
//
372
// icpu_err_o
373
//
374
assign icpu_err_o = miss | fault | qmemimmu_err_i;
375
 
376
//
377
// Assert itlb_en_r after one clock cycle and when there is no
378
// ITLB SPR access
379
//
380
always @(posedge clk or posedge rst)
381
        if (rst)
382
                itlb_en_r <= #1 1'b0;
383
        else
384
                itlb_en_r <= #1 itlb_en & ~itlb_spr_access;
385
 
386
//
387
// ITLB lookup successful
388
//
389
assign itlb_done = itlb_en_r & ~page_cross;
390
 
391
//
392 141 marcus.erl
// Cut transfer when access (mtspr/mfspr) to/from ITLB occure or if something goes 
393
// wrong with translation. If IC is disabled, use delayed signals.
394 10 unneback
//
395
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
396 141 marcus.erl
//assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
397
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done & ~itlb_spr_access : icpu_cycstb_i & ~page_cross;
398 10 unneback
 
399
//
400
// Cache Inhibit
401
//
402
// Cache inhibit is not really needed for instruction memory subsystem.
403
// If we would doq it, we would doq it like this.
404
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
405 141 marcus.erl
// However this causes an async combinatorial loop so we stick to
406 10 unneback
// no cache inhibit.
407 141 marcus.erl
//assign qmemimmu_ci_o = `OR1200_IMMU_CI;
408
// Cache inhibit without an async combinatorial loop 
409
assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
410 10 unneback
 
411
 
412
//
413
// Physical address is either translated virtual address or
414
// simply equal when IMMU is disabled
415
//
416 141 marcus.erl
//assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
417
assign qmemimmu_adr_o = immu_en & itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
418 10 unneback
 
419 141 marcus.erl
reg     [31:0]                  spr_dat_reg;
420 10 unneback
//
421
// Output to SPRS unit
422
//
423 141 marcus.erl
// spr_dat_o is registered on the 1st clock of spr read 
424
// so itlb can continue with process during execution of mfspr.
425
always @(posedge clk or posedge rst)
426
        if (rst)
427
                spr_dat_reg <= #1 32'h0000_0000;
428
        else if (spr_cs & !dis_spr_access_scnd_clk)
429
                spr_dat_reg <= #1 itlb_dat_o;
430 10 unneback
 
431 141 marcus.erl
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
432
 
433 10 unneback
//
434
// Page fault exception logic
435
//
436
assign fault = itlb_done &
437
                        (  (!supv & !itlb_uxe)          // Execute in user mode not enabled
438
                        || (supv & !itlb_sxe));         // Execute in supv mode not enabled
439
 
440
//
441
// TLB Miss exception logic
442
//
443
assign miss = itlb_done & !itlb_hit;
444
 
445
//
446
// ITLB Enable
447
//
448
assign itlb_en = immu_en & icpu_cycstb_i;
449
 
450
//
451
// Instantiation of ITLB
452
//
453
or1200_immu_tlb or1200_immu_tlb(
454
        // Rst and clk
455
        .clk(clk),
456
        .rst(rst),
457
 
458
        // I/F for translation
459
        .tlb_en(itlb_en),
460
        .vaddr(icpu_adr_i),
461
        .hit(itlb_hit),
462
        .ppn(itlb_ppn),
463
        .uxe(itlb_uxe),
464
        .sxe(itlb_sxe),
465
        .ci(itlb_ci),
466
 
467
`ifdef OR1200_BIST
468
        // RAM BIST
469
        .mbist_si_i(mbist_si_i),
470
        .mbist_so_o(mbist_so_o),
471
        .mbist_ctrl_i(mbist_ctrl_i),
472
`endif
473
 
474
        // SPR access
475
        .spr_cs(itlb_spr_access),
476
        .spr_write(spr_write),
477
        .spr_addr(spr_addr),
478
        .spr_dat_i(spr_dat_i),
479
        .spr_dat_o(itlb_dat_o)
480
);
481
 
482
`endif
483
 
484
endmodule

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