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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x22.v] - Blame information for rev 142

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_64x22.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Coding style changed.
//
// Revision 1.9  2005/10/19 11:37:56  jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:41  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_64x22(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 22;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire    [9:0]            unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire    [9:0]            unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
 
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x22_bist artisan_ssp(
`else
art_hssp_64x22 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x22_bist vs_ssp(
`else
vs_hdsp_64x22 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(1'b0),
        .ADDR({2'b00, addr}),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(1'b0),
        .ADDR({2'b00, addr}),
        .DI({10'b0000000000, di[21:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq[21:16]})
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
RAMB16_S36 ramb16_s36(
        .CLK(clk),
        .SSR(1'b0),
        .ADDR({3'b000, addr}),
        .DI({10'b0000000000,di}),
        .DIP(4'h0),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq}),
        .DOP()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x22.v] - Blame information for rev 142

Line No.	Rev	Author	Line
1	10	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// - Altera LPM ////`
28			`//// ////`
29			`//// To Do: ////`
30			`//// - xilinx rams need external tri-state logic ////`
31			`//// - fix avant! two-port ram ////`
32			`//// - add additional RAMs ////`
33			`//// ////`
34			`//// Author(s): ////`
35			`//// - Damjan Lampret, lampret@opencores.org ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
40			`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66	142	marcus.erl	`// $Log: or1200_spram_64x22.v,v $`
67			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
68			`// Minor update:`
69			`// Coding style changed.`
70			`//`
71			`// Revision 1.9 2005/10/19 11:37:56 jcastillo`
72			`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
73			`//`
74	10	unneback	`// Revision 1.8 2004/06/08 18:15:32 lampret`
75			`// Changed behavior of the simulation generic models`
76			`//`
77			`// Revision 1.7 2004/04/05 08:29:57 lampret`
78			`// Merged branch_qmem into main tree.`
79			`//`
80			`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`
81			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
82			`//`
83			`// Revision 1.3 2003/04/07 01:19:07 lampret`
84			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
85			`//`
86			`// Revision 1.2 2002/10/17 20:04:41 lampret`
87			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
88			`//`
89			`// Revision 1.1 2002/01/03 08:16:15 lampret`
90			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
91			`//`
92			`// Revision 1.7 2001/11/02 18:57:14 lampret`
93			`// Modified virtual silicon instantiations.`
94			`//`
95			`// Revision 1.6 2001/10/21 17:57:16 lampret`
96			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
97			`//`
98			`// Revision 1.5 2001/10/14 13:12:09 lampret`
99			`// MP3 version.`
100			`//`
101			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
102			`// no message`
103			`//`
104			`// Revision 1.1 2001/08/09 13:39:33 lampret`
105			`// Major clean-up.`
106			`//`
107			`// Revision 1.2 2001/07/30 05:38:02 lampret`
108			`// Adding empty directories required by HDL coding guidelines`
109			`//`
110			`//`
111
112			`// synopsys translate_off`
113			`include "timescale.v"
114			`// synopsys translate_on`
115			`include "or1200_defines.v"
116
117			`module or1200_spram_64x22(`
118			`ifdef OR1200_BIST
119			`// RAM BIST`
120			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
121			`endif
122			`// Generic synchronous single-port RAM interface`
123			`clk, rst, ce, we, oe, addr, di, doq`
124			`);`
125
126			`//`
127			`// Default address and data buses width`
128			`//`
129			`parameter aw = 6;`
130			`parameter dw = 22;`
131
132			`ifdef OR1200_BIST
133			`//`
134			`// RAM BIST`
135			`//`
136			`input mbist_si_i;`
137			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
138			`output mbist_so_o;`
139			`endif
140
141			`//`
142			`// Generic synchronous single-port RAM interface`
143			`//`
144			`input clk; // Clock`
145			`input rst; // Reset`
146			`input ce; // Chip enable input`
147			`input we; // Write enable input`
148			`input oe; // Output enable input`
149			`input [aw-1:0] addr; // address bus inputs`
150			`input [dw-1:0] di; // input data bus`
151			`output [dw-1:0] doq; // output data bus`
152
153			`//`
154			`// Internal wires and registers`
155			`//`
156			`ifdef OR1200_XILINX_RAMB4
157			`wire [9:0] unconnected;`
158			`else
159			`ifdef OR1200_XILINX_RAMB16
160			`wire [9:0] unconnected;`
161			`endif // !OR1200_XILINX_RAMB16
162			`endif // !OR1200_XILINX_RAMB4
163
164
165			`ifdef OR1200_ARTISAN_SSP
166			`else
167			`ifdef OR1200_VIRTUALSILICON_SSP
168			`else
169			`ifdef OR1200_BIST
170			`assign mbist_so_o = mbist_si_i;`
171			`endif
172			`endif
173			`endif
174
175			`ifdef OR1200_ARTISAN_SSP
176
177			`//`
178			`// Instantiation of ASIC memory:`
179			`//`
180			`// Artisan Synchronous Single-Port RAM (ra1sh)`
181			`//`
182			`ifdef UNUSED
183			`art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(`
184			`else
185			`ifdef OR1200_BIST
186			`art_hssp_64x22_bist artisan_ssp(`
187			`else
188			`art_hssp_64x22 artisan_ssp(`
189			`endif
190			`endif
191			`ifdef OR1200_BIST
192			`// RAM BIST`
193			`.mbist_si_i(mbist_si_i),`
194			`.mbist_so_o(mbist_so_o),`
195			`.mbist_ctrl_i(mbist_ctrl_i),`
196			`endif
197			`.CLK(clk),`
198			`.CEN(~ce),`
199			`.WEN(~we),`
200			`.A(addr),`
201			`.D(di),`
202			`.OEN(~oe),`
203			`.Q(doq)`
204			`);`
205
206			`else
207
208			`ifdef OR1200_AVANT_ATP
209
210			`//`
211			`// Instantiation of ASIC memory:`
212			`//`
213			`// Avant! Asynchronous Two-Port RAM`
214			`//`
215			`avant_atp avant_atp(`
216			`.web(~we),`
217			`.reb(),`
218			`.oeb(~oe),`
219			`.rcsb(),`
220			`.wcsb(),`
221			`.ra(addr),`
222			`.wa(addr),`
223			`.di(di),`
224			`.doq(doq)`
225			`);`
226
227			`else
228
229			`ifdef OR1200_VIRAGE_SSP
230
231			`//`
232			`// Instantiation of ASIC memory:`
233			`//`
234			`// Virage Synchronous 1-port R/W RAM`
235			`//`
236			`virage_ssp virage_ssp(`
237			`.clk(clk),`
238			`.adr(addr),`
239			`.d(di),`
240			`.we(we),`
241			`.oe(oe),`
242			`.me(ce),`
243			`.q(doq)`
244			`);`
245
246			`else
247
248			`ifdef OR1200_VIRTUALSILICON_SSP
249
250			`//`
251			`// Instantiation of ASIC memory:`
252			`//`
253			`// Virtual Silicon Single-Port Synchronous SRAM`
254			`//`
255			`ifdef UNUSED
256			`vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(`
257			`else
258			`ifdef OR1200_BIST
259			`vs_hdsp_64x22_bist vs_ssp(`
260			`else
261			`vs_hdsp_64x22 vs_ssp(`
262			`endif
263			`endif
264			`ifdef OR1200_BIST
265			`// RAM BIST`
266			`.mbist_si_i(mbist_si_i),`
267			`.mbist_so_o(mbist_so_o),`
268			`.mbist_ctrl_i(mbist_ctrl_i),`
269			`endif
270			`.CK(clk),`
271			`.ADR(addr),`
272			`.DI(di),`
273			`.WEN(~we),`
274			`.CEN(~ce),`
275			`.OEN(~oe),`
276			`.DOUT(doq)`
277			`);`
278
279			`else
280
281			`ifdef OR1200_XILINX_RAMB4
282
283			`//`
284			`// Instantiation of FPGA memory:`
285			`//`
286			`// Virtex/Spartan2`
287			`//`
288
289			`//`
290			`// Block 0`
291			`//`
292			`RAMB4_S16 ramb4_s16_0(`
293			`.CLK(clk),`
294	142	marcus.erl	`.RST(1'b0),`
295	10	unneback	`.ADDR({2'b00, addr}),`
296			`.DI(di[15:0]),`
297			`.EN(ce),`
298			`.WE(we),`
299			`.DO(doq[15:0])`
300			`);`
301
302			`//`
303			`// Block 1`
304			`//`
305			`RAMB4_S16 ramb4_s16_1(`
306			`.CLK(clk),`
307	142	marcus.erl	`.RST(1'b0),`
308	10	unneback	`.ADDR({2'b00, addr}),`
309			`.DI({10'b0000000000, di[21:16]}),`
310			`.EN(ce),`
311			`.WE(we),`
312			`.DO({unconnected, doq[21:16]})`
313			`);`
314
315			`else
316
317			`ifdef OR1200_XILINX_RAMB16
318
319			`//`
320			`// Instantiation of FPGA memory:`
321			`//`
322			`// Virtex4/Spartan3E`
323			`//`
324			`// Added By Nir Mor`
325			`//`
326
327			`RAMB16_S36 ramb16_s36(`
328			`.CLK(clk),`
329	142	marcus.erl	`.SSR(1'b0),`
330	10	unneback	`.ADDR({3'b000, addr}),`
331			`.DI({10'b0000000000,di}),`
332			`.DIP(4'h0),`
333			`.EN(ce),`
334			`.WE(we),`
335			`.DO({unconnected, doq}),`
336			`.DOP()`
337			`);`
338
339			`else
340
341			`ifdef OR1200_ALTERA_LPM
342
343			`//`
344			`// Instantiation of FPGA memory:`
345			`//`
346			`// Altera LPM`
347			`//`
348			`// Added By Jamil Khatib`
349			`//`
350
351			`wire wr;`
352
353			`assign wr = ce & we;`
354
355			`initial $display("Using Altera LPM.");`
356
357			`lpm_ram_dq lpm_ram_dq_component (`
358			`.address(addr),`
359			`.inclock(clk),`
360			`.outclock(clk),`
361			`.data(di),`
362			`.we(wr),`
363			`.q(doq)`
364			`);`
365
366			`defparam lpm_ram_dq_component.lpm_width = dw,`
367			`lpm_ram_dq_component.lpm_widthad = aw,`
368			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
369			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
370			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
371			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
372			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
373
374			`else
375
376			`//`
377			`// Generic single-port synchronous RAM model`
378			`//`
379
380			`//`
381			`// Generic RAM's registers and wires`
382			`//`
383			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
384			`reg [aw-1:0] addr_reg; // RAM address register`
385
386			`//`
387			`// Data output drivers`
388			`//`
389			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
390
391			`//`
392			`// RAM address register`
393			`//`
394			`always @(posedge clk or posedge rst)`
395			`if (rst)`
396			`addr_reg <= #1 {aw{1'b0}};`
397			`else if (ce)`
398			`addr_reg <= #1 addr;`
399
400			`//`
401			`// RAM write`
402			`//`
403			`always @(posedge clk)`
404			`if (ce && we)`
405			`mem[addr] <= #1 di;`
406
407			`endif // !OR1200_ALTERA_LPM
408			`endif // !OR1200_XILINX_RAMB16
409			`endif // !OR1200_XILINX_RAMB4
410			`endif // !OR1200_VIRTUALSILICON_SSP
411			`endif // !OR1200_VIRAGE_SSP
412			`endif // !OR1200_AVANT_ATP
413			`endif // !OR1200_ARTISAN_SSP
414
415			`endmodule`