OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Blame information for rev 808

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's interface to SPRs                                  ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
8
////  Description                                                 ////
9
////  Decoding of SPR addresses and access to SPRs                ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44 142 marcus.erl
// $Log: or1200_sprs.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Major update: 
47
// Structure reordered and bugs fixed. 
48 10 unneback
 
49
// synopsys translate_off
50
`include "timescale.v"
51
// synopsys translate_on
52
`include "or1200_defines.v"
53
 
54
module or1200_sprs(
55 481 julius
                   // Clk & Rst
56
                   clk, rst,
57 10 unneback
 
58 481 julius
                   // Internal CPU interface
59
                   flagforw, flag_we, flag, cyforw, cy_we, carry,
60 808 julius
                   ovforw, ov_we, dsx,
61 481 julius
                   addrbase, addrofs, dat_i, branch_op, ex_spr_read,
62
                   ex_spr_write,
63
                   epcr, eear, esr, except_started,
64
                   to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
65
                   spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
66
                   spr_dat_mac,
67
 
68
                   boot_adr_sel_i,
69 10 unneback
 
70 481 julius
                   // Floating point SPR input
71
                   fpcsr, fpcsr_we, spr_dat_fpu,
72 10 unneback
 
73 481 julius
                   // From/to other RISC units
74
                   spr_dat_pic, spr_dat_tt, spr_dat_pm,
75
                   spr_dat_dmmu, spr_dat_immu, spr_dat_du,
76
                   spr_addr, spr_dat_o, spr_cs, spr_we,
77 10 unneback
 
78 481 julius
                   du_addr, du_dat_du, du_read,
79
                   du_write, du_dat_cpu
80 10 unneback
 
81 481 julius
                   );
82 10 unneback
 
83 481 julius
   parameter width = `OR1200_OPERAND_WIDTH;
84 10 unneback
 
85 481 julius
   //
86
   // I/O Ports
87
   //
88 10 unneback
 
89 481 julius
   //
90
   // Internal CPU interface
91
   //
92
   input                                clk;            // Clock
93
   input                                rst;            // Reset
94
   input                                flagforw;       // From ALU
95
   input                                flag_we;        // From ALU
96
   output                               flag;           // SR[F]
97
   input                                cyforw;         // From ALU
98
   input                                cy_we;          // From ALU
99
   output                               carry;          // SR[CY]
100 642 julius
   input                                ovforw;         // From ALU
101
   input                                ov_we;          // From ALU
102 808 julius
   input                                dsx;            // From except
103 481 julius
   input [width-1:0]                     addrbase;       // SPR base address
104
   input [15:0]                  addrofs;        // SPR offset
105
   input [width-1:0]                     dat_i;          // SPR write data
106
   input                                ex_spr_read;    // l.mfspr in EX
107
   input                                ex_spr_write;   // l.mtspr in EX
108
   input [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;      // Branch operation
109
   input [width-1:0]                     epcr /* verilator public */;// EPCR0
110
   input [width-1:0]                     eear /* verilator public */;// EEAR0
111
   input [`OR1200_SR_WIDTH-1:0]  esr /* verilator public */; // ESR0
112
   input                                except_started; // Exception was started
113
   output [width-1:0]                    to_wbmux;       // For l.mfspr
114
   output                               epcr_we;        // EPCR0 write enable
115
   output                               eear_we;        // EEAR0 write enable
116
   output                               esr_we;         // ESR0 write enable
117
   output                               pc_we;          // PC write enable
118
   output                               sr_we;          // Write enable SR
119
   output [`OR1200_SR_WIDTH-1:0]         to_sr;          // Data to SR
120
   output [`OR1200_SR_WIDTH-1:0]         sr /* verilator public */;// SR
121
   input [31:0]                  spr_dat_cfgr;   // Data from CFGR
122
   input [31:0]                  spr_dat_rf;     // Data from RF
123
   input [31:0]                  spr_dat_npc;    // Data from NPC
124
   input [31:0]                  spr_dat_ppc;    // Data from PPC   
125
   input [31:0]                  spr_dat_mac;    // Data from MAC
126
   input                                boot_adr_sel_i;
127
 
128
   input [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;  // FPCSR
129
   output                               fpcsr_we;       // Write enable FPCSR   
130
   input [31:0]                  spr_dat_fpu;    // Data from FPU
131 185 julius
 
132 481 julius
   //
133
   // To/from other RISC units
134
   //
135
   input [31:0]                  spr_dat_pic;    // Data from PIC
136
   input [31:0]                  spr_dat_tt;     // Data from TT
137
   input [31:0]                  spr_dat_pm;     // Data from PM
138
   input [31:0]                  spr_dat_dmmu;   // Data from DMMU
139
   input [31:0]                  spr_dat_immu;   // Data from IMMU
140
   input [31:0]                  spr_dat_du;     // Data from DU
141
   output [31:0]                         spr_addr;       // SPR Address
142
   output [31:0]                         spr_dat_o;      // Data to unit
143
   output [31:0]                         spr_cs;         // Unit select
144
   output                               spr_we;         // SPR write enable
145 10 unneback
 
146 481 julius
   //
147
   // To/from Debug Unit
148
   //
149
   input [width-1:0]                     du_addr;        // Address
150
   input [width-1:0]                     du_dat_du;      // Data from DU to SPRS
151
   input                                du_read;        // Read qualifier
152
   input                                du_write;       // Write qualifier
153
   output [width-1:0]                    du_dat_cpu;     // Data from SPRS to DU
154 10 unneback
 
155 481 julius
   //
156
   // Internal regs & wires
157
   //
158
   reg [`OR1200_SR_WIDTH-1:0]            sr_reg;         // SR
159
   reg                                  sr_reg_bit_eph; // SR_EPH bit
160
   reg                                  sr_reg_bit_eph_select;// SR_EPH select
161
   wire                                 sr_reg_bit_eph_muxed;// SR_EPH muxed bit
162
   reg [`OR1200_SR_WIDTH-1:0]            sr;                     // SR
163
   reg [width-1:0]                       to_wbmux;       // For l.mfspr
164
   wire                                 cfgr_sel;       // Select for cfg regs
165
   wire                                 rf_sel;         // Select for RF
166
   wire                                 npc_sel;        // Select for NPC
167
   wire                                 ppc_sel;        // Select for PPC
168
   wire                                 sr_sel;         // Select for SR        
169
   wire                                 epcr_sel;       // Select for EPCR0
170
   wire                                 eear_sel;       // Select for EEAR0
171
   wire                                 esr_sel;        // Select for ESR0
172
   wire                                 fpcsr_sel;      // Select for FPCSR   
173
   wire [31:0]                           sys_data;// Read data from system SPRs
174
   wire                                 du_access;// Debug unit access
175
   reg [31:0]                            unqualified_cs; // Unqualified selects
176
   wire                                 ex_spr_write; // jb
177 142 marcus.erl
 
178 481 julius
   //
179
   // Decide if it is debug unit access
180
   //
181
   assign du_access = du_read | du_write;
182 10 unneback
 
183 481 julius
   //
184
   // Generate SPR address from base address and offset
185
   // OR from debug unit address
186
   //
187
   assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});
188 10 unneback
 
189 481 julius
   //
190
   // SPR is written by debug unit or by l.mtspr
191
   //
192
   assign spr_dat_o = du_write ? du_dat_du : dat_i;
193 10 unneback
 
194 481 julius
   //
195
   // debug unit data input:
196
   //  - read of SPRS by debug unit
197
   //  - write into debug unit SPRs by debug unit itself
198
   //  - write into debug unit SPRs by l.mtspr
199
   //
200
   assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;
201 10 unneback
 
202 481 julius
   //
203
   // Write into SPRs when DU or l.mtspr
204
   //
205
   assign spr_we = du_write | ( ex_spr_write & !du_access );
206 10 unneback
 
207 151 marcus.erl
 
208 481 julius
   //
209
   // Qualify chip selects
210
   //
211
   assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read |
212
                                        (ex_spr_write & sr[`OR1200_SR_SM])}};
213 10 unneback
 
214 481 julius
   //
215
   // Decoding of groups
216
   //
217
   always @(spr_addr)
218
     case (spr_addr[`OR1200_SPR_GROUP_BITS])    // synopsys parallel_case
219
       `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs
220
         = 32'b00000000_00000000_00000000_00000001;
221
       `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs
222
         = 32'b00000000_00000000_00000000_00000010;
223
       `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs
224
         = 32'b00000000_00000000_00000000_00000100;
225
       `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs
226
         = 32'b00000000_00000000_00000000_00001000;
227
       `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs
228
         = 32'b00000000_00000000_00000000_00010000;
229
       `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs
230
         = 32'b00000000_00000000_00000000_00100000;
231
       `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs
232
         = 32'b00000000_00000000_00000000_01000000;
233
       `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs
234
         = 32'b00000000_00000000_00000000_10000000;
235
       `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs
236
         = 32'b00000000_00000000_00000001_00000000;
237
       `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs
238
         = 32'b00000000_00000000_00000010_00000000;
239
       `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs
240
         = 32'b00000000_00000000_00000100_00000000;
241
       `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs
242
         = 32'b00000000_00000000_00001000_00000000;
243
       `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs
244
         = 32'b00000000_00000000_00010000_00000000;
245
       `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs
246
         = 32'b00000000_00000000_00100000_00000000;
247
       `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs
248
         = 32'b00000000_00000000_01000000_00000000;
249
       `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs
250
         = 32'b00000000_00000000_10000000_00000000;
251
       `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs
252
         = 32'b00000000_00000001_00000000_00000000;
253
       `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs
254
         = 32'b00000000_00000010_00000000_00000000;
255
       `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs
256
         = 32'b00000000_00000100_00000000_00000000;
257
       `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs
258
         = 32'b00000000_00001000_00000000_00000000;
259
       `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs
260
         = 32'b00000000_00010000_00000000_00000000;
261
       `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs
262
         = 32'b00000000_00100000_00000000_00000000;
263
       `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs
264
         = 32'b00000000_01000000_00000000_00000000;
265
       `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs
266
         = 32'b00000000_10000000_00000000_00000000;
267
       `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs
268
         = 32'b00000001_00000000_00000000_00000000;
269
       `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs
270
         = 32'b00000010_00000000_00000000_00000000;
271
       `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs
272
         = 32'b00000100_00000000_00000000_00000000;
273
       `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs
274
         = 32'b00001000_00000000_00000000_00000000;
275
       `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs
276
         = 32'b00010000_00000000_00000000_00000000;
277
       `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs
278
         = 32'b00100000_00000000_00000000_00000000;
279
       `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs
280
         = 32'b01000000_00000000_00000000_00000000;
281
       `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs
282
         = 32'b10000000_00000000_00000000_00000000;
283
     endcase
284 10 unneback
 
285 481 julius
   //
286
   // SPRs System Group
287
   //
288 10 unneback
 
289 481 julius
   //
290
   // What to write into SR
291
   //
292 642 julius
   assign to_sr[`OR1200_SR_FO:`OR1200_SR_OVE]
293 808 julius
            = (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_EPH],dsx,1'b0} :
294 481 julius
              (branch_op == `OR1200_BRANCHOP_RFE) ?
295 642 julius
              esr[`OR1200_SR_FO:`OR1200_SR_OVE] : (spr_we && sr_sel) ?
296
              {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OVE]} :
297
              sr[`OR1200_SR_FO:`OR1200_SR_OVE];
298 481 julius
   assign to_sr[`OR1200_SR_TED]
299
            = (except_started) ? 1'b1 :
300
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
301
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
302
              sr[`OR1200_SR_TED];
303 642 julius
   assign to_sr[`OR1200_SR_OV]
304
            = (except_started) ? sr[`OR1200_SR_OV] :
305
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_OV] :
306
              ov_we ? ovforw :
307
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_OV] :
308
              sr[`OR1200_SR_OV];
309 481 julius
   assign to_sr[`OR1200_SR_CY]
310
            = (except_started) ? sr[`OR1200_SR_CY] :
311
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
312
              cy_we ? cyforw :
313
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
314
              sr[`OR1200_SR_CY];
315
   assign to_sr[`OR1200_SR_F]
316
            = (except_started) ? sr[`OR1200_SR_F] :
317
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
318
              flag_we ? flagforw :
319
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
320
              sr[`OR1200_SR_F];
321
 
322
   assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM]
323
            = (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00,
324
                                  sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
325
              (branch_op == `OR1200_BRANCHOP_RFE) ?
326
              esr[`OR1200_SR_CE:`OR1200_SR_SM] : (spr_we && sr_sel) ?
327
              spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM] :
328
              sr[`OR1200_SR_CE:`OR1200_SR_SM];
329 10 unneback
 
330 481 julius
   //
331
   // Selects for system SPRs
332
   //
333
   assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
334
                      (spr_addr[10:4] == `OR1200_SPR_CFGR));
335
   assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
336
                    (spr_addr[10:5] == `OR1200_SPR_RF));
337
   assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
338
                     (spr_addr[10:0] == `OR1200_SPR_NPC));
339
   assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
340
                     (spr_addr[10:0] == `OR1200_SPR_PPC));
341
   assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
342
                    (spr_addr[10:0] == `OR1200_SPR_SR));
343
   assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
344
                      (spr_addr[10:0] == `OR1200_SPR_EPCR));
345
   assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
346
                      (spr_addr[10:0] == `OR1200_SPR_EEAR));
347
   assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
348
                     (spr_addr[10:0] == `OR1200_SPR_ESR));
349
   assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
350
                       (spr_addr[10:0] == `OR1200_SPR_FPCSR));
351 10 unneback
 
352 258 julius
 
353 481 julius
   //
354
   // Write enables for system SPRs
355
   //
356
   assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) |
357 642 julius
                  flag_we | cy_we | ov_we;
358 481 julius
   assign pc_we = (du_write && (npc_sel | ppc_sel));
359
   assign epcr_we = (spr_we && epcr_sel);
360
   assign eear_we = (spr_we && eear_sel);
361
   assign esr_we = (spr_we && esr_sel);
362
   assign fpcsr_we = (spr_we && fpcsr_sel);
363 258 julius
 
364 481 julius
   //
365
   // Output from system SPRs
366
   //
367
   assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
368
                     (spr_dat_rf & {32{rf_sel}}) |
369
                     (spr_dat_npc & {32{npc_sel}}) |
370
                     (spr_dat_ppc & {32{ppc_sel}}) |
371
                     ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
372
                     (epcr & {32{epcr_sel}}) |
373
                     (eear & {32{eear_sel}}) |
374
                     ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} &
375
                      {32{fpcsr_sel}}) |
376
                     ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
377 10 unneback
 
378 481 julius
   //
379
   // Flag alias
380
   //
381
   assign flag = sr[`OR1200_SR_F];
382 10 unneback
 
383 481 julius
   //
384
   // Carry alias
385
   //
386
   assign carry = sr[`OR1200_SR_CY];
387 642 julius
 
388 481 julius
   //
389
   // Supervision register
390
   //
391
   always @(posedge clk or `OR1200_RST_EVENT rst)
392
     if (rst == `OR1200_RST_VALUE)
393
       sr_reg <=  {2'b01, // Fixed one.
394
                   `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
395
     else if (except_started)
396
       sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
397
     else if (sr_we)
398
       sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
399 10 unneback
 
400 481 julius
   // EPH part of Supervision register
401
   always @(posedge clk or `OR1200_RST_EVENT rst)
402
     // default value 
403
     if (rst == `OR1200_RST_VALUE) begin
404
        sr_reg_bit_eph <=  `OR1200_SR_EPH_DEF;
405
        // select async. value due to reset state
406
        sr_reg_bit_eph_select <=  1'b1;
407
     end
408
   // selected value (different from default) is written into FF after reset 
409
   // state
410
     else if (sr_reg_bit_eph_select) begin
411
        // dynamic value can only be assigned to FF out of reset!
412
        sr_reg_bit_eph <=  boot_adr_sel_i;
413
        sr_reg_bit_eph_select <=  1'b0; // select FF value
414
     end
415
     else if (sr_we) begin
416
        sr_reg_bit_eph <=  to_sr[`OR1200_SR_EPH];
417
     end
418 142 marcus.erl
 
419 481 julius
   // select async. value of EPH bit after reset 
420
   assign       sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ?
421
                                       boot_adr_sel_i : sr_reg_bit_eph;
422 142 marcus.erl
 
423 481 julius
   // EPH part joined together with rest of Supervision register
424
   always @(sr_reg or sr_reg_bit_eph_muxed)
425
     sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed,
426
           sr_reg[`OR1200_SR_WIDTH-4:0]};
427 142 marcus.erl
 
428 353 julius
`ifdef verilator
429
   // Function to access various sprs (for Verilator). Have to hide this from
430
   // simulator, since functions with no inputs are not allowed in IEEE
431
   // 1364-2001.
432
 
433
   function [31:0] get_sr;
434
      // verilator public
435 364 julius
      get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
436 353 julius
   endfunction // get_sr
437
 
438
   function [31:0] get_epcr;
439
      // verilator public
440
      get_epcr = epcr;
441
   endfunction // get_epcr
442
 
443
   function [31:0] get_eear;
444
      // verilator public
445
      get_eear = eear;
446
   endfunction // get_eear
447
 
448
   function [31:0] get_esr;
449
      // verilator public
450 364 julius
      get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
451 353 julius
   endfunction // get_esr
452
 
453
`endif
454
 
455 481 julius
   //
456
   // MTSPR/MFSPR interface
457
   //
458
   always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
459
            spr_dat_fpu or
460
            spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
461
      casez (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
462
        `OR1200_SPR_GROUP_SYS:
463
          to_wbmux = sys_data;
464
        `OR1200_SPR_GROUP_TT:
465
          to_wbmux = spr_dat_tt;
466
        `OR1200_SPR_GROUP_PIC:
467
          to_wbmux = spr_dat_pic;
468
        `OR1200_SPR_GROUP_PM:
469
          to_wbmux = spr_dat_pm;
470
        `OR1200_SPR_GROUP_DMMU:
471
          to_wbmux = spr_dat_dmmu;
472
        `OR1200_SPR_GROUP_IMMU:
473
          to_wbmux = spr_dat_immu;
474
        `OR1200_SPR_GROUP_MAC:
475
          to_wbmux = spr_dat_mac;
476
        `OR1200_SPR_GROUP_FPU:
477
          to_wbmux = spr_dat_fpu;
478
        default: //`OR1200_SPR_GROUP_DU:
479
          to_wbmux = spr_dat_du;
480
      endcase
481
   end
482 10 unneback
 
483
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.