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1 10 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's interface to SPRs                                  ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
6 185 julius
////  http://www.opencores.org/project,or1k                       ////
7 10 unneback
////                                                              ////
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////  Description                                                 ////
9
////  Decoding of SPR addresses and access to SPRs                ////
10
////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
44 142 marcus.erl
// $Log: or1200_sprs.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Major update: 
47
// Structure reordered and bugs fixed. 
48 10 unneback
 
49
// synopsys translate_off
50
`include "timescale.v"
51
// synopsys translate_on
52
`include "or1200_defines.v"
53
 
54
module or1200_sprs(
55
                // Clk & Rst
56
                clk, rst,
57
 
58
                // Internal CPU interface
59
                flagforw, flag_we, flag, cyforw, cy_we, carry,
60 142 marcus.erl
                addrbase, addrofs, dat_i, branch_op, ex_spr_read, ex_spr_write,
61 10 unneback
                epcr, eear, esr, except_started,
62
                to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
63
                spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
64 142 marcus.erl
                boot_adr_sel_i,
65 185 julius
 
66 258 julius
                // Floating point SPR input
67 186 julius
                fpcsr, fpcsr_we, spr_dat_fpu,
68 10 unneback
 
69
                // From/to other RISC units
70
                spr_dat_pic, spr_dat_tt, spr_dat_pm,
71
                spr_dat_dmmu, spr_dat_immu, spr_dat_du,
72
                spr_addr, spr_dat_o, spr_cs, spr_we,
73
 
74
                du_addr, du_dat_du, du_read,
75
                du_write, du_dat_cpu
76
 
77
);
78
 
79
parameter width = `OR1200_OPERAND_WIDTH;
80
 
81
//
82
// I/O Ports
83
//
84
 
85
//
86
// Internal CPU interface
87
//
88
input                           clk;            // Clock
89
input                           rst;            // Reset
90
input                           flagforw;       // From ALU
91
input                           flag_we;        // From ALU
92
output                          flag;           // SR[F]
93
input                           cyforw;         // From ALU
94
input                           cy_we;          // From ALU
95
output                          carry;          // SR[CY]
96
input   [width-1:0]              addrbase;       // SPR base address
97
input   [15:0]                   addrofs;        // SPR offset
98
input   [width-1:0]              dat_i;          // SPR write data
99 142 marcus.erl
input                           ex_spr_read;    // l.mfspr in EX
100
input                           ex_spr_write;   // l.mtspr in EX
101 10 unneback
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch operation
102 353 julius
input   [width-1:0]              epcr /* verilator public */;            // EPCR0
103
input   [width-1:0]              eear /* verilator public */;            // EEAR0
104
input   [`OR1200_SR_WIDTH-1:0]   esr /* verilator public */;             // ESR0
105 10 unneback
input                           except_started; // Exception was started
106
output  [width-1:0]              to_wbmux;       // For l.mfspr
107
output                          epcr_we;        // EPCR0 write enable
108
output                          eear_we;        // EEAR0 write enable
109
output                          esr_we;         // ESR0 write enable
110
output                          pc_we;          // PC write enable
111
output                          sr_we;          // Write enable SR
112
output  [`OR1200_SR_WIDTH-1:0]   to_sr;          // Data to SR
113 353 julius
output  [`OR1200_SR_WIDTH-1:0]   sr /* verilator public */;              // SR
114 10 unneback
input   [31:0]                   spr_dat_cfgr;   // Data from CFGR
115
input   [31:0]                   spr_dat_rf;     // Data from RF
116
input   [31:0]                   spr_dat_npc;    // Data from NPC
117
input   [31:0]                   spr_dat_ppc;    // Data from PPC   
118
input   [31:0]                   spr_dat_mac;    // Data from MAC
119 142 marcus.erl
input                           boot_adr_sel_i;
120 10 unneback
 
121 185 julius
input   [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;   // FPCSR
122
output                          fpcsr_we;       // Write enable FPCSR   
123
input [31:0]                     spr_dat_fpu;    // Data from FPU
124
 
125 10 unneback
//
126
// To/from other RISC units
127
//
128
input   [31:0]                   spr_dat_pic;    // Data from PIC
129
input   [31:0]                   spr_dat_tt;     // Data from TT
130
input   [31:0]                   spr_dat_pm;     // Data from PM
131
input   [31:0]                   spr_dat_dmmu;   // Data from DMMU
132
input   [31:0]                   spr_dat_immu;   // Data from IMMU
133
input   [31:0]                   spr_dat_du;     // Data from DU
134
output  [31:0]                   spr_addr;       // SPR Address
135
output  [31:0]                   spr_dat_o;      // Data to unit
136
output  [31:0]                   spr_cs;         // Unit select
137
output                          spr_we;         // SPR write enable
138
 
139
//
140
// To/from Debug Unit
141
//
142
input   [width-1:0]              du_addr;        // Address
143
input   [width-1:0]              du_dat_du;      // Data from DU to SPRS
144
input                           du_read;        // Read qualifier
145
input                           du_write;       // Write qualifier
146
output  [width-1:0]              du_dat_cpu;     // Data from SPRS to DU
147
 
148
//
149
// Internal regs & wires
150
//
151 142 marcus.erl
reg     [`OR1200_SR_WIDTH-1:0]   sr_reg;                 // SR
152
reg                             sr_reg_bit_eph;         // SR_EPH bit
153
reg                             sr_reg_bit_eph_select;  // SR_EPH select
154
wire                            sr_reg_bit_eph_muxed;   // SR_EPH muxed bit
155
reg     [`OR1200_SR_WIDTH-1:0]   sr;                     // SR
156 10 unneback
reg     [width-1:0]              to_wbmux;       // For l.mfspr
157
wire                            cfgr_sel;       // Select for cfg regs
158
wire                            rf_sel;         // Select for RF
159
wire                            npc_sel;        // Select for NPC
160
wire                            ppc_sel;        // Select for PPC
161
wire                            sr_sel;         // Select for SR        
162
wire                            epcr_sel;       // Select for EPCR0
163
wire                            eear_sel;       // Select for EEAR0
164
wire                            esr_sel;        // Select for ESR0
165 185 julius
wire                            fpcsr_sel;      // Select for FPCSR   
166 10 unneback
wire    [31:0]                   sys_data;       // Read data from system SPRs
167
wire                            du_access;      // Debug unit access
168
reg     [31:0]                   unqualified_cs; // Unqualified chip selects
169 142 marcus.erl
   wire                         ex_spr_write; // jb
170
 
171 10 unneback
//
172
// Decide if it is debug unit access
173
//
174
assign du_access = du_read | du_write;
175
 
176
//
177
// Generate SPR address from base address and offset
178
// OR from debug unit address
179
//
180 142 marcus.erl
assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});
181 10 unneback
 
182
//
183
// SPR is written by debug unit or by l.mtspr
184
//
185
assign spr_dat_o = du_write ? du_dat_du : dat_i;
186
 
187
//
188
// debug unit data input:
189 142 marcus.erl
//  - read of SPRS by debug unit
190 10 unneback
//  - write into debug unit SPRs by debug unit itself
191
//  - write into debug unit SPRs by l.mtspr
192
//
193 142 marcus.erl
assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;
194 10 unneback
 
195
//
196 142 marcus.erl
// Write into SPRs when DU or l.mtspr
197 10 unneback
//
198 151 marcus.erl
assign spr_we = du_write | ( ex_spr_write & !du_access );
199 10 unneback
 
200 151 marcus.erl
 
201 10 unneback
//
202
// Qualify chip selects
203
//
204 142 marcus.erl
assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read | (ex_spr_write & sr[`OR1200_SR_SM])}};
205 10 unneback
 
206
//
207
// Decoding of groups
208
//
209
always @(spr_addr)
210
        case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
211
                `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
212
                `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
213
                `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
214
                `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
215
                `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
216
                `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
217
                `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
218
                `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
219
                `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
220
                `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
221
                `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
222
                `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
223
                `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
224
                `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
225
                `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
226
                `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
227
                `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
228
                `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
229
                `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
230
                `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
231
                `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
232
                `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
233
                `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
234
                `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
235
                `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
236
                `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
237
                `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
238
                `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
239
                `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
240
                `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
241
                `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
242
                `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
243
        endcase
244
 
245
//
246
// SPRs System Group
247
//
248
 
249
//
250
// What to write into SR
251
//
252
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
253 142 marcus.erl
                (except_started) ? sr[`OR1200_SR_FO:`OR1200_SR_OV] :
254 10 unneback
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
255 142 marcus.erl
                (spr_we && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
256 10 unneback
                sr[`OR1200_SR_FO:`OR1200_SR_OV];
257 142 marcus.erl
assign to_sr[`OR1200_SR_TED] =
258
                (except_started) ? 1'b1 :
259
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
260
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED]:
261
                sr[`OR1200_SR_TED];
262 10 unneback
assign to_sr[`OR1200_SR_CY] =
263 142 marcus.erl
                (except_started) ? sr[`OR1200_SR_CY] :
264 10 unneback
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
265
                cy_we ? cyforw :
266 142 marcus.erl
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
267 10 unneback
                sr[`OR1200_SR_CY];
268
assign to_sr[`OR1200_SR_F] =
269 142 marcus.erl
                (except_started) ? sr[`OR1200_SR_F] :
270 10 unneback
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
271
                flag_we ? flagforw :
272 142 marcus.erl
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
273 10 unneback
                sr[`OR1200_SR_F];
274
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
275 142 marcus.erl
                (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00, sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
276 10 unneback
                (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
277 142 marcus.erl
                (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
278 10 unneback
                sr[`OR1200_SR_CE:`OR1200_SR_SM];
279
 
280
//
281
// Selects for system SPRs
282
//
283
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
284
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
285
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
286
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
287
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
288
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
289
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
290
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
291 185 julius
assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_FPCSR));
292 10 unneback
 
293 258 julius
 
294 10 unneback
//
295
// Write enables for system SPRs
296
//
297 142 marcus.erl
assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
298
assign pc_we = (du_write && (npc_sel | ppc_sel));
299
assign epcr_we = (spr_we && epcr_sel);
300
assign eear_we = (spr_we && eear_sel);
301
assign esr_we = (spr_we && esr_sel);
302 185 julius
assign fpcsr_we = (spr_we && fpcsr_sel);
303 258 julius
 
304 10 unneback
//
305
// Output from system SPRs
306
//
307 142 marcus.erl
assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
308
                  (spr_dat_rf & {32{rf_sel}}) |
309
                  (spr_dat_npc & {32{npc_sel}}) |
310
                  (spr_dat_ppc & {32{ppc_sel}}) |
311
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
312
                  (epcr & {32{epcr_sel}}) |
313
                  (eear & {32{eear_sel}}) |
314 187 julius
                  ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & {32{fpcsr_sel}}) |
315 142 marcus.erl
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
316 10 unneback
 
317
//
318
// Flag alias
319
//
320
assign flag = sr[`OR1200_SR_F];
321
 
322
//
323
// Carry alias
324
//
325
assign carry = sr[`OR1200_SR_CY];
326
 
327
//
328
// Supervision register
329
//
330
always @(posedge clk or posedge rst)
331
        if (rst)
332 258 julius
                sr_reg <=  {2'h1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
333 142 marcus.erl
        else if (except_started)
334 258 julius
                sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
335 10 unneback
        else if (sr_we)
336 258 julius
                sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
337 10 unneback
 
338 142 marcus.erl
// EPH part of Supervision register
339
always @(posedge clk or posedge rst)
340
        // default value 
341
        if (rst) begin
342 258 julius
                sr_reg_bit_eph <=  `OR1200_SR_EPH_DEF;
343
                sr_reg_bit_eph_select <=  1'b1; // select async. value due to reset state
344 142 marcus.erl
        end
345
        // selected value (different from default) is written into FF after reset state
346
        else if (sr_reg_bit_eph_select) begin
347 258 julius
                sr_reg_bit_eph <=  boot_adr_sel_i;      // dynamic value can only be assigned to FF out of reset! 
348
                sr_reg_bit_eph_select <=  1'b0; // select FF value 
349 142 marcus.erl
        end
350
        else if (sr_we) begin
351 258 julius
                sr_reg_bit_eph <=  to_sr[`OR1200_SR_EPH];
352 142 marcus.erl
        end
353
 
354
// select async. value of EPH bit after reset 
355
assign  sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ? boot_adr_sel_i : sr_reg_bit_eph;
356
 
357
// EPH part joined together with rest of Supervision register
358
always @(sr_reg or sr_reg_bit_eph_muxed)
359
        sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed, sr_reg[`OR1200_SR_WIDTH-4:0]};
360
 
361 353 julius
`ifdef verilator
362
   // Function to access various sprs (for Verilator). Have to hide this from
363
   // simulator, since functions with no inputs are not allowed in IEEE
364
   // 1364-2001.
365
 
366
   function [31:0] get_sr;
367
      // verilator public
368
      get_sr = sr;
369
   endfunction // get_sr
370
 
371
   function [31:0] get_epcr;
372
      // verilator public
373
      get_epcr = epcr;
374
   endfunction // get_epcr
375
 
376
   function [31:0] get_eear;
377
      // verilator public
378
      get_eear = eear;
379
   endfunction // get_eear
380
 
381
   function [31:0] get_esr;
382
      // verilator public
383
      get_esr = esr;
384
   endfunction // get_esr
385
 
386
`endif
387
 
388
 
389 10 unneback
//
390
// MTSPR/MFSPR interface
391
//
392 142 marcus.erl
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
393 185 julius
         spr_dat_fpu or
394 10 unneback
        spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
395 142 marcus.erl
                casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
396
                        `OR1200_SPR_GROUP_SYS:
397
                                to_wbmux = sys_data;
398
                        `OR1200_SPR_GROUP_TT:
399
                                to_wbmux = spr_dat_tt;
400
                        `OR1200_SPR_GROUP_PIC:
401
                                to_wbmux = spr_dat_pic;
402
                        `OR1200_SPR_GROUP_PM:
403
                                to_wbmux = spr_dat_pm;
404
                        `OR1200_SPR_GROUP_DMMU:
405
                                to_wbmux = spr_dat_dmmu;
406
                        `OR1200_SPR_GROUP_IMMU:
407
                                to_wbmux = spr_dat_immu;
408
                        `OR1200_SPR_GROUP_MAC:
409
                                to_wbmux = spr_dat_mac;
410 185 julius
                        `OR1200_SPR_GROUP_FPU:
411
                                 to_wbmux = spr_dat_fpu;
412 142 marcus.erl
                        default: //`OR1200_SPR_GROUP_DU:
413
                                to_wbmux = spr_dat_du;
414
                endcase
415 10 unneback
end
416
 
417
endmodule

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