OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [SprCache.h] - Blame information for rev 63

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 63 julius
// ----------------------------------------------------------------------------
2
 
3
// Debug Unit SPR cache: definition
4
 
5
// Copyright (C) 2008  Embecosm Limited <info@embecosm.com>
6
 
7
// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8
 
9
// This file is part of the GDB interface to the cycle accurate model of the
10
// OpenRISC 1000 based system-on-chip, ORPSoC, built using Verilator.
11
 
12
// This program is free software: you can redistribute it and/or modify it
13
// under the terms of the GNU Lesser General Public License as published by
14
// the Free Software Foundation, either version 3 of the License, or (at your
15
// option) any later version.
16
 
17
// This program is distributed in the hope that it will be useful, but WITHOUT
18
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
20
// License for more details.
21
 
22
// You should have received a copy of the GNU Lesser General Public License
23
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
24
 
25
// ----------------------------------------------------------------------------
26
 
27
// $Id: SprCache.h 331 2009-03-12 17:01:48Z jeremy $
28
 
29
#ifndef SPR_CACHE__H
30
#define SPR_CACHE__H
31
 
32
#include <stdint.h>
33
 
34
 
35
//-----------------------------------------------------------------------------
36
//! Module for cacheing SPR accesses by the debug unit
37
 
38
//! SPR reads and writes through the Debug Unit via JTAG are time
39
//! consuming - of the order of 1000 CPU clock cycles. However when the
40
//! processor is stalled the values cannot change, other than through the
41
//! debug unit, so it makes sense to cache values.
42
 
43
//! @note It is not strictly true that SPRs do not change. If the NPC is
44
//!       written, it flushes the pipeline, and subsequent reads will return
45
//!       zero until the processor is unstalled and the pipeline has
46
//!       refilled. However for our purposes, it is convenient to return the
47
//!       value written into the NPC in such circumstances.
48
//!
49
//! The cache is represented as a closed hash table, which is generally
50
//! allowed to be no more than 70% full (however NPC is always
51
//! cacheable). The hash function is a simple modulo function, stepping
52
//! forward to the first free slot. This works because there is no function to
53
//! delete an entry - just to clear the whole table, so holes cannot appear.
54
//-----------------------------------------------------------------------------
55
class SprCache
56
{
57
public:
58
 
59
  // Constructor and destructor
60
  SprCache (int  _tableSize = 257);
61
  ~SprCache ();
62
 
63
  // Functions
64
  void  clear ();
65
  void  write (uint16_t  sprNum,
66
               uint32_t  value,
67
               bool      force);
68
  bool  read (uint16_t  sprNum,
69
              uint32_t &value);
70
 
71
private:
72
 
73
  //! The size of the hash table
74
  int  tableSize;
75
 
76
  //! Maximum amount of cache left to use, before cacheing is rejected.
77
  int  maxToUse;
78
 
79
  // The cache, keyed by sprNum. Done as two parallel vectors,
80
  // allowing unambiguous clearing by use of memset for efficiency.
81
  bool     *sprIsValid;
82
  uint16_t *sprKeyNum;
83
  uint32_t *sprValue;
84
 
85
 
86
};      // SprCache ()
87
 
88
#endif  // SPR_CACHE__H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.