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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [SIETransmitter_simlib.v] - Blame information for rev 408

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1 408 julius
 
2
// File        : ../RTL/serialInterfaceEngine/SIETransmitter.v
3
// Generated   : 10/15/06 20:31:22
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// From        : ../RTL/serialInterfaceEngine/SIETransmitter.asf
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// By          : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// SIETransmitter
10
////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// http://www.opencores.org/cores/usbhostslave/                 ////
13
////                                                              ////
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//// Module Description:                                          ////
15
//// 
16
////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
29
//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
31
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
50
`include "timescale.v"
51
`include "usbSerialInterfaceEngine_h.v"
52
`include "usbConstants_h.v"
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54
 
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module SIETransmitter_simlib (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOutFullSpeedRate, TxByteOut, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, fullSpeedRateIn, processTxByteRdy, processTxByteWEn, rst, rstCRC);
56
input   [15:0] CRC16Result;
57
input   CRC16UpdateRdy;
58
input   [4:0] CRC5Result;
59
input   CRC5UpdateRdy;
60
input   [1:0] JBit;
61
input   [1:0] KBit;
62
input   [7:0] SIEPortCtrlIn;
63
input   [7:0] SIEPortDataIn;
64
input   SIEPortWEn;
65
input   USBWireGnt;
66
input   USBWireRdy;
67
input   clk;
68
input   fullSpeedRateIn;
69
input   processTxByteRdy;
70
input   rst;
71
output  CRC16En;
72
output  CRC5En;
73
output  CRC5_8Bit;
74
output  [7:0] CRCData;
75
output  SIEPortTxRdy;
76
output  [7:0] TxByteOutCtrl;
77
output  TxByteOutFullSpeedRate;
78
output  [7:0] TxByteOut;
79
output  USBWireCtrl;
80
output  [1:0] USBWireData;
81
output  USBWireFullSpeedRate;
82
output  USBWireReq;
83
output  USBWireWEn;
84
output  processTxByteWEn;
85
output  rstCRC;
86
 
87
reg     CRC16En, next_CRC16En;
88
wire    [15:0] CRC16Result;
89
wire    CRC16UpdateRdy;
90
reg     CRC5En, next_CRC5En;
91
wire    [4:0] CRC5Result;
92
wire    CRC5UpdateRdy;
93
reg     CRC5_8Bit, next_CRC5_8Bit;
94
reg     [7:0] CRCData, next_CRCData;
95
wire    [1:0] JBit;
96
wire    [1:0] KBit;
97
wire    [7:0] SIEPortCtrlIn;
98
wire    [7:0] SIEPortDataIn;
99
reg     SIEPortTxRdy, next_SIEPortTxRdy;
100
wire    SIEPortWEn;
101
reg     [7:0] TxByteOutCtrl, next_TxByteOutCtrl;
102
reg     TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
103
reg     [7:0] TxByteOut, next_TxByteOut;
104
reg     USBWireCtrl, next_USBWireCtrl;
105
reg     [1:0] USBWireData, next_USBWireData;
106
reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
107
wire    USBWireGnt;
108
wire    USBWireRdy;
109
reg     USBWireReq, next_USBWireReq;
110
reg     USBWireWEn, next_USBWireWEn;
111
wire    clk;
112
wire    fullSpeedRateIn;
113
wire    processTxByteRdy;
114
reg     processTxByteWEn, next_processTxByteWEn;
115
wire    rst;
116
reg     rstCRC, next_rstCRC;
117
 
118
// diagram signals declarations
119
reg  [7:0]SIEPortCtrl, next_SIEPortCtrl;
120
reg  [7:0]SIEPortData, next_SIEPortData;
121
reg  [2:0]i, next_i;
122
reg  [15:0]resumeCnt, next_resumeCnt;
123
 
124
// BINARY ENCODED state machine: SIETx
125
// State codes definitions:
126
`define DIR_CTL_CHK_FIN 6'b000000
127
`define RES_ST_CHK_FIN 6'b000001
128
`define PKT_ST_CHK_PID 6'b000010
129
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
130
`define IDLE 6'b000100
131
`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
132
`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
133
`define PKT_ST_HS_PKT_SENT 6'b000111
134
`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
135
`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
136
`define PKT_ST_SPCL_PKT_SENT 6'b001010
137
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
138
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
139
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
140
`define RES_ST_SND_J_1 6'b001110
141
`define RES_ST_SND_J_2 6'b001111
142
`define RES_ST_SND_SE0_1 6'b010000
143
`define RES_ST_SND_SE0_2 6'b010001
144
`define START_SIETX 6'b010010
145
`define STX_CHK_ST 6'b010011
146
`define STX_WAIT_BYTE 6'b010100
147
`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
148
`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
149
`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
150
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011000
151
`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011001
152
`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011010
153
`define DIR_CTL_WAIT_GNT 6'b011011
154
`define RES_ST_WAIT_GNT 6'b011100
155
`define PKT_ST_HS_WAIT_RDY 6'b011101
156
`define DIR_CTL_WAIT_RDY 6'b011110
157
`define PKT_ST_SPCL_WAIT_RDY 6'b011111
158
`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
159
`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
160
`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100010
161
`define RES_ST_WAIT_RDY 6'b100011
162
`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
163
`define PKT_ST_DATA_PID_WAIT_RDY 6'b100101
164
`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100110
165
`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b100111
166
`define PKT_ST_WAIT_RDY_PKT 6'b101000
167
`define RES_ST_W_RDY1 6'b101001
168
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
169
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
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`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
171
`define TX_LS_EOP_WAIT_GNT1 6'b101101
172
`define TX_LS_EOP_SND_SE0_2 6'b101110
173
`define TX_LS_EOP_SND_SE0_1 6'b101111
174
`define TX_LS_EOP_W_RDY1 6'b110000
175
`define TX_LS_EOP_SND_J 6'b110001
176
`define TX_LS_EOP_W_RDY2 6'b110010
177
`define TX_LS_EOP_W_RDY3 6'b110011
178
`define RES_ST_DELAY 6'b110100
179
`define RES_ST_W_RDY2 6'b110101
180
`define RES_ST_W_RDY3 6'b110110
181
`define RES_ST_W_RDY4 6'b110111
182
`define DIR_CTL_DELAY 6'b111000
183
 
184
reg [5:0] CurrState_SIETx;
185
reg [5:0] NextState_SIETx;
186
 
187
 
188
//--------------------------------------------------------------------
189
// Machine: SIETx
190
//--------------------------------------------------------------------
191
//----------------------------------
192
// Next State Logic (combinatorial)
193
//----------------------------------
194
always @ (SIEPortDataIn or SIEPortCtrlIn or fullSpeedRateIn or i or SIEPortData or CRC16Result or CRC5Result or KBit or resumeCnt or JBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or USBWireFullSpeedRate or CurrState_SIETx)
195
begin : SIETx_NextState
196
  NextState_SIETx <= CurrState_SIETx;
197
  // Set default values for outputs and signals
198
  next_processTxByteWEn <= processTxByteWEn;
199
  next_TxByteOut <= TxByteOut;
200
  next_TxByteOutCtrl <= TxByteOutCtrl;
201
  next_USBWireData <= USBWireData;
202
  next_USBWireCtrl <= USBWireCtrl;
203
  next_USBWireReq <= USBWireReq;
204
  next_USBWireWEn <= USBWireWEn;
205
  next_rstCRC <= rstCRC;
206
  next_CRCData <= CRCData;
207
  next_CRC5En <= CRC5En;
208
  next_CRC5_8Bit <= CRC5_8Bit;
209
  next_CRC16En <= CRC16En;
210
  next_SIEPortTxRdy <= SIEPortTxRdy;
211
  next_SIEPortData <= SIEPortData;
212
  next_SIEPortCtrl <= SIEPortCtrl;
213
  next_i <= i;
214
  next_resumeCnt <= resumeCnt;
215
  next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
216
  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
217
  case (CurrState_SIETx)
218
    `IDLE:
219
      NextState_SIETx <= `STX_WAIT_BYTE;
220
    `START_SIETX:
221
    begin
222
      next_processTxByteWEn <= 1'b0;
223
      next_TxByteOut <= 8'h00;
224
      next_TxByteOutCtrl <= 8'h00;
225
      next_USBWireData <= 2'b00;
226
      next_USBWireCtrl <= `TRI_STATE;
227
      next_USBWireReq <= 1'b0;
228
      next_USBWireWEn <= 1'b0;
229
      next_rstCRC <= 1'b0;
230
      next_CRCData <= 8'h00;
231
      next_CRC5En <= 1'b0;
232
      next_CRC5_8Bit <= 1'b0;
233
      next_CRC16En <= 1'b0;
234
      next_SIEPortTxRdy <= 1'b0;
235
      next_SIEPortData <= 8'h00;
236
      next_SIEPortCtrl <= 8'h00;
237
      next_i <= 3'h0;
238
      next_resumeCnt <= 16'h0000;
239
      next_TxByteOutFullSpeedRate <= 1'b0;
240
      next_USBWireFullSpeedRate <= 1'b0;
241
      NextState_SIETx <= `STX_WAIT_BYTE;
242
    end
243
    `STX_CHK_ST:
244
      if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
245
      begin
246
        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
247
        next_TxByteOutFullSpeedRate <= 1'b1;
248
        //SOF and PRE always at full speed
249
      end
250
      else if (SIEPortCtrl == `TX_PACKET_START)
251
        NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
252
      else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
253
      begin
254
        NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
255
        next_USBWireReq <= 1'b1;
256
      end
257
      else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
258
      begin
259
        NextState_SIETx <= `DIR_CTL_WAIT_GNT;
260
        next_USBWireReq <= 1'b1;
261
      end
262
      else if (SIEPortCtrl == `TX_IDLE)
263
        NextState_SIETx <= `IDLE;
264
      else if (SIEPortCtrl == `TX_RESUME_START)
265
      begin
266
        NextState_SIETx <= `RES_ST_WAIT_GNT;
267
        next_USBWireReq <= 1'b1;
268
        next_resumeCnt <= 16'h0000;
269
        next_USBWireFullSpeedRate <= 1'b0;
270
        //resume always uses low speed timing
271
      end
272
    `STX_WAIT_BYTE:
273
    begin
274
      next_SIEPortTxRdy <= 1'b1;
275
      if (SIEPortWEn == 1'b1)
276
      begin
277
        NextState_SIETx <= `STX_CHK_ST;
278
        next_SIEPortData <= SIEPortDataIn;
279
        next_SIEPortCtrl <= SIEPortCtrlIn;
280
        next_SIEPortTxRdy <= 1'b0;
281
        next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
282
        next_USBWireFullSpeedRate <= fullSpeedRateIn;
283
      end
284
    end
285
    `DIR_CTL_CHK_FIN:
286
    begin
287
      next_USBWireWEn <= 1'b0;
288
      next_i <= i + 1'b1;
289
      if (i == 3'h7)
290
      begin
291
        NextState_SIETx <= `STX_WAIT_BYTE;
292
        next_USBWireReq <= 1'b0;
293
      end
294
      else
295
        NextState_SIETx <= `DIR_CTL_DELAY;
296
    end
297
    `DIR_CTL_WAIT_GNT:
298
    begin
299
      next_i <= 3'h0;
300
      if (USBWireGnt == 1'b1)
301
        NextState_SIETx <= `DIR_CTL_WAIT_RDY;
302
    end
303
    `DIR_CTL_WAIT_RDY:
304
      if (USBWireRdy == 1'b1)
305
      begin
306
        NextState_SIETx <= `DIR_CTL_CHK_FIN;
307
        next_USBWireData <= SIEPortData[1:0];
308
        next_USBWireCtrl <= `DRIVE;
309
        next_USBWireWEn <= 1'b1;
310
      end
311
    `DIR_CTL_DELAY:
312
      NextState_SIETx <= `DIR_CTL_WAIT_RDY;
313
    `PKT_ST_CHK_PID:
314
    begin
315
      next_processTxByteWEn <= 1'b0;
316
      if (SIEPortData[1:0] == `TOKEN)
317
        NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
318
      else if (SIEPortData[1:0] == `HANDSHAKE)
319
        NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
320
      else if (SIEPortData[1:0] == `DATA)
321
        NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
322
      else if (SIEPortData[1:0] == `SPECIAL)
323
        NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
324
    end
325
    `PKT_ST_WAIT_RDY_PKT:
326
      if (processTxByteRdy == 1'b1)
327
      begin
328
        NextState_SIETx <= `PKT_ST_CHK_PID;
329
        next_processTxByteWEn <= 1'b1;
330
        next_TxByteOut <= `SYNC_BYTE;
331
        next_TxByteOutCtrl <= `DATA_START;
332
      end
333
    `PKT_ST_DATA_CRC_PKT_SENT1:
334
    begin
335
      next_processTxByteWEn <= 1'b0;
336
      NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
337
    end
338
    `PKT_ST_DATA_CRC_PKT_SENT2:
339
    begin
340
      next_processTxByteWEn <= 1'b0;
341
      NextState_SIETx <= `STX_WAIT_BYTE;
342
    end
343
    `PKT_ST_DATA_CRC_WAIT_RDY1:
344
      if (processTxByteRdy == 1'b1)
345
      begin
346
        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
347
        next_processTxByteWEn <= 1'b1;
348
        next_TxByteOut <= ~CRC16Result[7:0];
349
        next_TxByteOutCtrl <= `DATA_STREAM;
350
      end
351
    `PKT_ST_DATA_CRC_WAIT_RDY2:
352
      if (processTxByteRdy == 1'b1)
353
      begin
354
        NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
355
        next_processTxByteWEn <= 1'b1;
356
        next_TxByteOut <= ~CRC16Result[15:8];
357
        next_TxByteOutCtrl <= `DATA_STOP;
358
      end
359
    `PKT_ST_DATA_DATA_CHK_STOP:
360
      if (SIEPortCtrl == `TX_PACKET_STOP)
361
        NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
362
      else
363
        NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
364
    `PKT_ST_DATA_DATA_PKT_SENT:
365
    begin
366
      next_processTxByteWEn <= 1'b0;
367
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
368
    end
369
    `PKT_ST_DATA_DATA_UPD_CRC:
370
    begin
371
      next_CRCData <= SIEPortData;
372
      next_CRC16En <= 1'b1;
373
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
374
    end
375
    `PKT_ST_DATA_DATA_WAIT_BYTE:
376
    begin
377
      next_SIEPortTxRdy <= 1'b1;
378
      if (SIEPortWEn == 1'b1)
379
      begin
380
        NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
381
        next_SIEPortData <= SIEPortDataIn;
382
        next_SIEPortCtrl <= SIEPortCtrlIn;
383
        next_SIEPortTxRdy <= 1'b0;
384
      end
385
    end
386
    `PKT_ST_DATA_DATA_WAIT_RDY:
387
    begin
388
      next_CRC16En <= 1'b0;
389
      if (processTxByteRdy == 1'b1)
390
      begin
391
        NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
392
        next_processTxByteWEn <= 1'b1;
393
        next_TxByteOut <= SIEPortData;
394
        next_TxByteOutCtrl <= `DATA_STREAM;
395
      end
396
    end
397
    `PKT_ST_DATA_DATA_WAIT_CRC_RDY:
398
      if (CRC16UpdateRdy == 1'b1)
399
        NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
400
    `PKT_ST_DATA_PID_PKT_SENT:
401
    begin
402
      next_processTxByteWEn <= 1'b0;
403
      next_rstCRC <= 1'b0;
404
      NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
405
    end
406
    `PKT_ST_DATA_PID_WAIT_RDY:
407
      if (processTxByteRdy == 1'b1)
408
      begin
409
        NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
410
        next_processTxByteWEn <= 1'b1;
411
        next_TxByteOut <= SIEPortData;
412
        next_TxByteOutCtrl <= `DATA_STREAM;
413
        next_rstCRC <= 1'b1;
414
      end
415
    `PKT_ST_HS_PKT_SENT:
416
    begin
417
      next_processTxByteWEn <= 1'b0;
418
      NextState_SIETx <= `STX_WAIT_BYTE;
419
    end
420
    `PKT_ST_HS_WAIT_RDY:
421
      if (processTxByteRdy == 1'b1)
422
      begin
423
        NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
424
        next_processTxByteWEn <= 1'b1;
425
        next_TxByteOut <= SIEPortData;
426
        next_TxByteOutCtrl <= `DATA_STOP;
427
      end
428
    `PKT_ST_SPCL_PKT_SENT:
429
    begin
430
      next_processTxByteWEn <= 1'b0;
431
      NextState_SIETx <= `STX_WAIT_BYTE;
432
    end
433
    `PKT_ST_SPCL_WAIT_RDY:
434
      if (processTxByteRdy == 1'b1)
435
      begin
436
        NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
437
        next_processTxByteWEn <= 1'b1;
438
        next_TxByteOut <= SIEPortData;
439
        next_TxByteOutCtrl <= `DATA_STOP;
440
      end
441
    `PKT_ST_TKN_BYTE1_PKT_SENT1:
442
    begin
443
      next_processTxByteWEn <= 1'b0;
444
      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
445
    end
446
    `PKT_ST_TKN_BYTE1_UPD_CRC:
447
    begin
448
      next_CRCData <= SIEPortData;
449
      next_CRC5_8Bit <= 1'b1;
450
      next_CRC5En <= 1'b1;
451
      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
452
    end
453
    `PKT_ST_TKN_BYTE1_WAIT_BYTE:
454
    begin
455
      next_SIEPortTxRdy <= 1'b1;
456
      if (SIEPortWEn == 1'b1)
457
      begin
458
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
459
        next_SIEPortData <= SIEPortDataIn;
460
        next_SIEPortCtrl <= SIEPortCtrlIn;
461
        next_SIEPortTxRdy <= 1'b0;
462
      end
463
    end
464
    `PKT_ST_TKN_BYTE1_WAIT_RDY:
465
    begin
466
      next_CRC5En <= 1'b0;
467
      if (processTxByteRdy == 1'b1)
468
      begin
469
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
470
        next_processTxByteWEn <= 1'b1;
471
        next_TxByteOut <= SIEPortData;
472
        next_TxByteOutCtrl <= `DATA_STREAM;
473
      end
474
    end
475
    `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
476
      if (CRC5UpdateRdy == 1'b1)
477
        NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
478
    `PKT_ST_TKN_CRC_PKT_SENT:
479
    begin
480
      next_processTxByteWEn <= 1'b0;
481
      NextState_SIETx <= `STX_WAIT_BYTE;
482
    end
483
    `PKT_ST_TKN_CRC_UPD_CRC:
484
    begin
485
      next_CRCData <= SIEPortData;
486
      next_CRC5_8Bit <= 1'b0;
487
      next_CRC5En <= 1'b1;
488
      NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
489
    end
490
    `PKT_ST_TKN_CRC_WAIT_BYTE:
491
    begin
492
      next_SIEPortTxRdy <= 1'b1;
493
      if (SIEPortWEn == 1'b1)
494
      begin
495
        NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
496
        next_SIEPortData <= SIEPortDataIn;
497
        next_SIEPortCtrl <= SIEPortCtrlIn;
498
        next_SIEPortTxRdy <= 1'b0;
499
      end
500
    end
501
    `PKT_ST_TKN_CRC_WAIT_RDY:
502
    begin
503
      next_CRC5En <= 1'b0;
504
      if (processTxByteRdy == 1'b1)
505
      begin
506
        NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
507
        next_processTxByteWEn <= 1'b1;
508
        next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
509
        next_TxByteOutCtrl <= `DATA_STOP;
510
      end
511
    end
512
    `PKT_ST_TKN_CRC_WAIT_CRC_RDY:
513
      if (CRC5UpdateRdy == 1'b1)
514
        NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
515
    `PKT_ST_TKN_PID_PKT_SENT:
516
    begin
517
      next_processTxByteWEn <= 1'b0;
518
      next_rstCRC <= 1'b0;
519
      NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
520
    end
521
    `PKT_ST_TKN_PID_WAIT_RDY:
522
      if (processTxByteRdy == 1'b1)
523
      begin
524
        NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
525
        next_processTxByteWEn <= 1'b1;
526
        next_TxByteOut <= SIEPortData;
527
        next_TxByteOutCtrl <= `DATA_STREAM;
528
        next_rstCRC <= 1'b1;
529
      end
530
    `RES_ST_CHK_FIN:
531
    begin
532
      next_USBWireWEn <= 1'b0;
533
      if (resumeCnt == `HOST_TX_RESUME_TIME)
534
        NextState_SIETx <= `RES_ST_W_RDY1;
535
      else
536
        NextState_SIETx <= `RES_ST_DELAY;
537
    end
538
    `RES_ST_SND_J_1:
539
    begin
540
      next_USBWireWEn <= 1'b0;
541
      NextState_SIETx <= `RES_ST_W_RDY4;
542
    end
543
    `RES_ST_SND_J_2:
544
    begin
545
      next_USBWireWEn <= 1'b0;
546
      next_USBWireReq <= 1'b0;
547
      NextState_SIETx <= `STX_WAIT_BYTE;
548
      next_USBWireFullSpeedRate <= fullSpeedRateIn;
549
    end
550
    `RES_ST_SND_SE0_1:
551
    begin
552
      next_USBWireWEn <= 1'b0;
553
      NextState_SIETx <= `RES_ST_W_RDY2;
554
    end
555
    `RES_ST_SND_SE0_2:
556
    begin
557
      next_USBWireWEn <= 1'b0;
558
      NextState_SIETx <= `RES_ST_W_RDY3;
559
    end
560
    `RES_ST_WAIT_GNT:
561
      if (USBWireGnt == 1'b1)
562
        NextState_SIETx <= `RES_ST_WAIT_RDY;
563
    `RES_ST_WAIT_RDY:
564
      if (USBWireRdy == 1'b1)
565
      begin
566
        NextState_SIETx <= `RES_ST_CHK_FIN;
567
        next_USBWireData <= KBit;
568
        next_USBWireCtrl <= `DRIVE;
569
        next_USBWireWEn <= 1'b1;
570
        next_resumeCnt <= resumeCnt  + 1'b1;
571
      end
572
    `RES_ST_W_RDY1:
573
      if (USBWireRdy == 1'b1)
574
      begin
575
        NextState_SIETx <= `RES_ST_SND_SE0_1;
576
        next_USBWireData <= `SE0;
577
        next_USBWireCtrl <= `DRIVE;
578
        next_USBWireWEn <= 1'b1;
579
      end
580
    `RES_ST_DELAY:
581
      NextState_SIETx <= `RES_ST_WAIT_RDY;
582
    `RES_ST_W_RDY2:
583
      if (USBWireRdy == 1'b1)
584
      begin
585
        NextState_SIETx <= `RES_ST_SND_SE0_2;
586
        next_USBWireData <= `SE0;
587
        next_USBWireCtrl <= `DRIVE;
588
        next_USBWireWEn <= 1'b1;
589
      end
590
    `RES_ST_W_RDY3:
591
      if (USBWireRdy == 1'b1)
592
      begin
593
        NextState_SIETx <= `RES_ST_SND_J_1;
594
        next_USBWireData <= JBit;
595
        next_USBWireCtrl <= `DRIVE;
596
        next_USBWireWEn <= 1'b1;
597
      end
598
    `RES_ST_W_RDY4:
599
      if (USBWireRdy == 1'b1)
600
      begin
601
        NextState_SIETx <= `RES_ST_SND_J_2;
602
        next_USBWireData <= JBit;
603
        next_USBWireCtrl <= `TRI_STATE;
604
        next_USBWireWEn <= 1'b1;
605
      end
606
    `TX_LS_EOP_WAIT_GNT1:
607
      if (USBWireGnt == 1'b1)
608
        NextState_SIETx <= `TX_LS_EOP_W_RDY1;
609
    `TX_LS_EOP_SND_SE0_2:
610
    begin
611
      next_USBWireWEn <= 1'b0;
612
      NextState_SIETx <= `TX_LS_EOP_W_RDY3;
613
    end
614
    `TX_LS_EOP_SND_SE0_1:
615
    begin
616
      next_USBWireWEn <= 1'b0;
617
      NextState_SIETx <= `TX_LS_EOP_W_RDY2;
618
    end
619
    `TX_LS_EOP_W_RDY1:
620
      if (USBWireRdy == 1'b1)
621
      begin
622
        NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
623
        next_USBWireData <= `SE0;
624
        next_USBWireCtrl <= `DRIVE;
625
        next_USBWireWEn <= 1'b1;
626
      end
627
    `TX_LS_EOP_SND_J:
628
    begin
629
      next_USBWireWEn <= 1'b0;
630
      next_USBWireReq <= 1'b0;
631
      NextState_SIETx <= `STX_WAIT_BYTE;
632
    end
633
    `TX_LS_EOP_W_RDY2:
634
      if (USBWireRdy == 1'b1)
635
      begin
636
        NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
637
        next_USBWireData <= `SE0;
638
        next_USBWireCtrl <= `DRIVE;
639
        next_USBWireWEn <= 1'b1;
640
      end
641
    `TX_LS_EOP_W_RDY3:
642
      if (USBWireRdy == 1'b1)
643
      begin
644
        NextState_SIETx <= `TX_LS_EOP_SND_J;
645
        next_USBWireData <= JBit;
646
        next_USBWireCtrl <= `DRIVE;
647
        next_USBWireWEn <= 1'b1;
648
      end
649
  endcase
650
end
651
 
652
//----------------------------------
653
// Current State Logic (sequential)
654
//----------------------------------
655
always @ (posedge clk)
656
begin : SIETx_CurrentState
657
  if (rst)
658
    CurrState_SIETx <= `START_SIETX;
659
  else
660
    CurrState_SIETx <= NextState_SIETx;
661
end
662
 
663
//----------------------------------
664
// Registered outputs logic
665
//----------------------------------
666
always @ (posedge clk)
667
begin : SIETx_RegOutput
668
  if (rst)
669
  begin
670
    SIEPortData <= 8'h00;
671
    SIEPortCtrl <= 8'h00;
672
    i <= 3'h0;
673
    resumeCnt <= 16'h0000;
674
    processTxByteWEn <= 1'b0;
675
    TxByteOut <= 8'h00;
676
    TxByteOutCtrl <= 8'h00;
677
    USBWireData <= 2'b00;
678
    USBWireCtrl <= `TRI_STATE;
679
    USBWireReq <= 1'b0;
680
    USBWireWEn <= 1'b0;
681
    rstCRC <= 1'b0;
682
    CRCData <= 8'h00;
683
    CRC5En <= 1'b0;
684
    CRC5_8Bit <= 1'b0;
685
    CRC16En <= 1'b0;
686
    SIEPortTxRdy <= 1'b0;
687
    TxByteOutFullSpeedRate <= 1'b0;
688
    USBWireFullSpeedRate <= 1'b0;
689
  end
690
  else
691
  begin
692
    SIEPortData <= next_SIEPortData;
693
    SIEPortCtrl <= next_SIEPortCtrl;
694
    i <= next_i;
695
    resumeCnt <= next_resumeCnt;
696
    processTxByteWEn <= next_processTxByteWEn;
697
    TxByteOut <= next_TxByteOut;
698
    TxByteOutCtrl <= next_TxByteOutCtrl;
699
    USBWireData <= next_USBWireData;
700
    USBWireCtrl <= next_USBWireCtrl;
701
    USBWireReq <= next_USBWireReq;
702
    USBWireWEn <= next_USBWireWEn;
703
    rstCRC <= next_rstCRC;
704
    CRCData <= next_CRCData;
705
    CRC5En <= next_CRC5En;
706
    CRC5_8Bit <= next_CRC5_8Bit;
707
    CRC16En <= next_CRC16En;
708
    SIEPortTxRdy <= next_SIEPortTxRdy;
709
    TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
710
    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
711
  end
712
end
713
 
714
endmodule

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